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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Marvell MMC/SD/SDIO driver
0004  *
0005  * Authors: Maen Suleiman, Nicolas Pitre
0006  * Copyright (C) 2008-2009 Marvell Ltd.
0007  */
0008 
0009 #include <linux/module.h>
0010 #include <linux/init.h>
0011 #include <linux/io.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/mbus.h>
0014 #include <linux/delay.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/dma-mapping.h>
0017 #include <linux/scatterlist.h>
0018 #include <linux/irq.h>
0019 #include <linux/clk.h>
0020 #include <linux/of_irq.h>
0021 #include <linux/mmc/host.h>
0022 #include <linux/mmc/slot-gpio.h>
0023 
0024 #include <linux/sizes.h>
0025 #include <asm/unaligned.h>
0026 
0027 #include "mvsdio.h"
0028 
0029 #define DRIVER_NAME "mvsdio"
0030 
0031 static int maxfreq;
0032 static int nodma;
0033 
0034 struct mvsd_host {
0035     void __iomem *base;
0036     struct mmc_request *mrq;
0037     spinlock_t lock;
0038     unsigned int xfer_mode;
0039     unsigned int intr_en;
0040     unsigned int ctrl;
0041     unsigned int pio_size;
0042     void *pio_ptr;
0043     unsigned int sg_frags;
0044     unsigned int ns_per_clk;
0045     unsigned int clock;
0046     unsigned int base_clock;
0047     struct timer_list timer;
0048     struct mmc_host *mmc;
0049     struct device *dev;
0050     struct clk *clk;
0051 };
0052 
0053 #define mvsd_write(offs, val)   writel(val, iobase + (offs))
0054 #define mvsd_read(offs)     readl(iobase + (offs))
0055 
0056 static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
0057 {
0058     void __iomem *iobase = host->base;
0059     unsigned int tmout;
0060     int tmout_index;
0061 
0062     /*
0063      * Hardware weirdness.  The FIFO_EMPTY bit of the HW_STATE
0064      * register is sometimes not set before a while when some
0065      * "unusual" data block sizes are used (such as with the SWITCH
0066      * command), even despite the fact that the XFER_DONE interrupt
0067      * was raised.  And if another data transfer starts before
0068      * this bit comes to good sense (which eventually happens by
0069      * itself) then the new transfer simply fails with a timeout.
0070      */
0071     if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
0072         unsigned long t = jiffies + HZ;
0073         unsigned int hw_state,  count = 0;
0074         do {
0075             hw_state = mvsd_read(MVSD_HW_STATE);
0076             if (time_after(jiffies, t)) {
0077                 dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
0078                 break;
0079             }
0080             count++;
0081         } while (!(hw_state & (1 << 13)));
0082         dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
0083                    "(hw=0x%04x, count=%d, jiffies=%ld)\n",
0084                    hw_state, count, jiffies - (t - HZ));
0085     }
0086 
0087     /* If timeout=0 then maximum timeout index is used. */
0088     tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
0089     tmout += data->timeout_clks;
0090     tmout_index = fls(tmout - 1) - 12;
0091     if (tmout_index < 0)
0092         tmout_index = 0;
0093     if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
0094         tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
0095 
0096     dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
0097         (data->flags & MMC_DATA_READ) ? "read" : "write",
0098         (u32)sg_virt(data->sg), data->blocks, data->blksz,
0099         tmout, tmout_index);
0100 
0101     host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
0102     host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
0103     mvsd_write(MVSD_HOST_CTRL, host->ctrl);
0104     mvsd_write(MVSD_BLK_COUNT, data->blocks);
0105     mvsd_write(MVSD_BLK_SIZE, data->blksz);
0106 
0107     if (nodma || (data->blksz | data->sg->offset) & 3 ||
0108         ((!(data->flags & MMC_DATA_READ) && data->sg->offset & 0x3f))) {
0109         /*
0110          * We cannot do DMA on a buffer which offset or size
0111          * is not aligned on a 4-byte boundary.
0112          *
0113          * It also appears the host to card DMA can corrupt
0114          * data when the buffer is not aligned on a 64 byte
0115          * boundary.
0116          */
0117         host->pio_size = data->blocks * data->blksz;
0118         host->pio_ptr = sg_virt(data->sg);
0119         if (!nodma)
0120             dev_dbg(host->dev, "fallback to PIO for data at 0x%p size %d\n",
0121                 host->pio_ptr, host->pio_size);
0122         return 1;
0123     } else {
0124         dma_addr_t phys_addr;
0125 
0126         host->sg_frags = dma_map_sg(mmc_dev(host->mmc),
0127                         data->sg, data->sg_len,
0128                         mmc_get_dma_dir(data));
0129         phys_addr = sg_dma_address(data->sg);
0130         mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
0131         mvsd_write(MVSD_SYS_ADDR_HI,  (u32)phys_addr >> 16);
0132         return 0;
0133     }
0134 }
0135 
0136 static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
0137 {
0138     struct mvsd_host *host = mmc_priv(mmc);
0139     void __iomem *iobase = host->base;
0140     struct mmc_command *cmd = mrq->cmd;
0141     u32 cmdreg = 0, xfer = 0, intr = 0;
0142     unsigned long flags;
0143     unsigned int timeout;
0144 
0145     BUG_ON(host->mrq != NULL);
0146     host->mrq = mrq;
0147 
0148     dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
0149         cmd->opcode, mvsd_read(MVSD_HW_STATE));
0150 
0151     cmdreg = MVSD_CMD_INDEX(cmd->opcode);
0152 
0153     if (cmd->flags & MMC_RSP_BUSY)
0154         cmdreg |= MVSD_CMD_RSP_48BUSY;
0155     else if (cmd->flags & MMC_RSP_136)
0156         cmdreg |= MVSD_CMD_RSP_136;
0157     else if (cmd->flags & MMC_RSP_PRESENT)
0158         cmdreg |= MVSD_CMD_RSP_48;
0159     else
0160         cmdreg |= MVSD_CMD_RSP_NONE;
0161 
0162     if (cmd->flags & MMC_RSP_CRC)
0163         cmdreg |= MVSD_CMD_CHECK_CMDCRC;
0164 
0165     if (cmd->flags & MMC_RSP_OPCODE)
0166         cmdreg |= MVSD_CMD_INDX_CHECK;
0167 
0168     if (cmd->flags & MMC_RSP_PRESENT) {
0169         cmdreg |= MVSD_UNEXPECTED_RESP;
0170         intr |= MVSD_NOR_UNEXP_RSP;
0171     }
0172 
0173     if (mrq->data) {
0174         struct mmc_data *data = mrq->data;
0175         int pio;
0176 
0177         cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
0178         xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
0179         if (data->flags & MMC_DATA_READ)
0180             xfer |= MVSD_XFER_MODE_TO_HOST;
0181 
0182         pio = mvsd_setup_data(host, data);
0183         if (pio) {
0184             xfer |= MVSD_XFER_MODE_PIO;
0185             /* PIO section of mvsd_irq has comments on those bits */
0186             if (data->flags & MMC_DATA_WRITE)
0187                 intr |= MVSD_NOR_TX_AVAIL;
0188             else if (host->pio_size > 32)
0189                 intr |= MVSD_NOR_RX_FIFO_8W;
0190             else
0191                 intr |= MVSD_NOR_RX_READY;
0192         }
0193 
0194         if (data->stop) {
0195             struct mmc_command *stop = data->stop;
0196             u32 cmd12reg = 0;
0197 
0198             mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
0199             mvsd_write(MVSD_AUTOCMD12_ARG_HI,  stop->arg >> 16);
0200 
0201             if (stop->flags & MMC_RSP_BUSY)
0202                 cmd12reg |= MVSD_AUTOCMD12_BUSY;
0203             if (stop->flags & MMC_RSP_OPCODE)
0204                 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
0205             cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
0206             mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
0207 
0208             xfer |= MVSD_XFER_MODE_AUTO_CMD12;
0209             intr |= MVSD_NOR_AUTOCMD12_DONE;
0210         } else {
0211             intr |= MVSD_NOR_XFER_DONE;
0212         }
0213     } else {
0214         intr |= MVSD_NOR_CMD_DONE;
0215     }
0216 
0217     mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
0218     mvsd_write(MVSD_ARG_HI,  cmd->arg >> 16);
0219 
0220     spin_lock_irqsave(&host->lock, flags);
0221 
0222     host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
0223     host->xfer_mode |= xfer;
0224     mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
0225 
0226     mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
0227     mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
0228     mvsd_write(MVSD_CMD, cmdreg);
0229 
0230     host->intr_en &= MVSD_NOR_CARD_INT;
0231     host->intr_en |= intr | MVSD_NOR_ERROR;
0232     mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
0233     mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
0234 
0235     timeout = cmd->busy_timeout ? cmd->busy_timeout : 5000;
0236     mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout));
0237 
0238     spin_unlock_irqrestore(&host->lock, flags);
0239 }
0240 
0241 static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
0242                u32 err_status)
0243 {
0244     void __iomem *iobase = host->base;
0245 
0246     if (cmd->flags & MMC_RSP_136) {
0247         unsigned int response[8], i;
0248         for (i = 0; i < 8; i++)
0249             response[i] = mvsd_read(MVSD_RSP(i));
0250         cmd->resp[0] =      ((response[0] & 0x03ff) << 22) |
0251                     ((response[1] & 0xffff) << 6) |
0252                     ((response[2] & 0xfc00) >> 10);
0253         cmd->resp[1] =      ((response[2] & 0x03ff) << 22) |
0254                     ((response[3] & 0xffff) << 6) |
0255                     ((response[4] & 0xfc00) >> 10);
0256         cmd->resp[2] =      ((response[4] & 0x03ff) << 22) |
0257                     ((response[5] & 0xffff) << 6) |
0258                     ((response[6] & 0xfc00) >> 10);
0259         cmd->resp[3] =      ((response[6] & 0x03ff) << 22) |
0260                     ((response[7] & 0x3fff) << 8);
0261     } else if (cmd->flags & MMC_RSP_PRESENT) {
0262         unsigned int response[3], i;
0263         for (i = 0; i < 3; i++)
0264             response[i] = mvsd_read(MVSD_RSP(i));
0265         cmd->resp[0] =      ((response[2] & 0x003f) << (8 - 8)) |
0266                     ((response[1] & 0xffff) << (14 - 8)) |
0267                     ((response[0] & 0x03ff) << (30 - 8));
0268         cmd->resp[1] =      ((response[0] & 0xfc00) >> 10);
0269         cmd->resp[2] = 0;
0270         cmd->resp[3] = 0;
0271     }
0272 
0273     if (err_status & MVSD_ERR_CMD_TIMEOUT) {
0274         cmd->error = -ETIMEDOUT;
0275     } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
0276                  MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
0277         cmd->error = -EILSEQ;
0278     }
0279     err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
0280             MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
0281             MVSD_ERR_CMD_STARTBIT);
0282 
0283     return err_status;
0284 }
0285 
0286 static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
0287                 u32 err_status)
0288 {
0289     void __iomem *iobase = host->base;
0290 
0291     if (host->pio_ptr) {
0292         host->pio_ptr = NULL;
0293         host->pio_size = 0;
0294     } else {
0295         dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
0296                  mmc_get_dma_dir(data));
0297     }
0298 
0299     if (err_status & MVSD_ERR_DATA_TIMEOUT)
0300         data->error = -ETIMEDOUT;
0301     else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
0302         data->error = -EILSEQ;
0303     else if (err_status & MVSD_ERR_XFER_SIZE)
0304         data->error = -EBADE;
0305     err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
0306             MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
0307 
0308     dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
0309         mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
0310     data->bytes_xfered =
0311         (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
0312     /* We can't be sure about the last block when errors are detected */
0313     if (data->bytes_xfered && data->error)
0314         data->bytes_xfered -= data->blksz;
0315 
0316     /* Handle Auto cmd 12 response */
0317     if (data->stop) {
0318         unsigned int response[3], i;
0319         for (i = 0; i < 3; i++)
0320             response[i] = mvsd_read(MVSD_AUTO_RSP(i));
0321         data->stop->resp[0] =   ((response[2] & 0x003f) << (8 - 8)) |
0322                     ((response[1] & 0xffff) << (14 - 8)) |
0323                     ((response[0] & 0x03ff) << (30 - 8));
0324         data->stop->resp[1] =   ((response[0] & 0xfc00) >> 10);
0325         data->stop->resp[2] = 0;
0326         data->stop->resp[3] = 0;
0327 
0328         if (err_status & MVSD_ERR_AUTOCMD12) {
0329             u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
0330             dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
0331             if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
0332                 data->stop->error = -ENOEXEC;
0333             else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
0334                 data->stop->error = -ETIMEDOUT;
0335             else if (err_cmd12)
0336                 data->stop->error = -EILSEQ;
0337             err_status &= ~MVSD_ERR_AUTOCMD12;
0338         }
0339     }
0340 
0341     return err_status;
0342 }
0343 
0344 static irqreturn_t mvsd_irq(int irq, void *dev)
0345 {
0346     struct mvsd_host *host = dev;
0347     void __iomem *iobase = host->base;
0348     u32 intr_status, intr_done_mask;
0349     int irq_handled = 0;
0350 
0351     intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
0352     dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
0353         intr_status, mvsd_read(MVSD_NOR_INTR_EN),
0354         mvsd_read(MVSD_HW_STATE));
0355 
0356     /*
0357      * It looks like, SDIO IP can issue one late, spurious irq
0358      * although all irqs should be disabled. To work around this,
0359      * bail out early, if we didn't expect any irqs to occur.
0360      */
0361     if (!mvsd_read(MVSD_NOR_INTR_EN) && !mvsd_read(MVSD_ERR_INTR_EN)) {
0362         dev_dbg(host->dev, "spurious irq detected intr 0x%04x intr_en 0x%04x erri 0x%04x erri_en 0x%04x\n",
0363             mvsd_read(MVSD_NOR_INTR_STATUS),
0364             mvsd_read(MVSD_NOR_INTR_EN),
0365             mvsd_read(MVSD_ERR_INTR_STATUS),
0366             mvsd_read(MVSD_ERR_INTR_EN));
0367         return IRQ_HANDLED;
0368     }
0369 
0370     spin_lock(&host->lock);
0371 
0372     /* PIO handling, if needed. Messy business... */
0373     if (host->pio_size &&
0374         (intr_status & host->intr_en &
0375          (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
0376         u16 *p = host->pio_ptr;
0377         int s = host->pio_size;
0378         while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
0379             readsw(iobase + MVSD_FIFO, p, 16);
0380             p += 16;
0381             s -= 32;
0382             intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
0383         }
0384         /*
0385          * Normally we'd use < 32 here, but the RX_FIFO_8W bit
0386          * doesn't appear to assert when there is exactly 32 bytes
0387          * (8 words) left to fetch in a transfer.
0388          */
0389         if (s <= 32) {
0390             while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
0391                 put_unaligned(mvsd_read(MVSD_FIFO), p++);
0392                 put_unaligned(mvsd_read(MVSD_FIFO), p++);
0393                 s -= 4;
0394                 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
0395             }
0396             if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
0397                 u16 val[2] = {0, 0};
0398                 val[0] = mvsd_read(MVSD_FIFO);
0399                 val[1] = mvsd_read(MVSD_FIFO);
0400                 memcpy(p, ((void *)&val) + 4 - s, s);
0401                 s = 0;
0402                 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
0403             }
0404             if (s == 0) {
0405                 host->intr_en &=
0406                      ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
0407                 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
0408             } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
0409                 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
0410                 host->intr_en |= MVSD_NOR_RX_READY;
0411                 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
0412             }
0413         }
0414         dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
0415             s, intr_status, mvsd_read(MVSD_HW_STATE));
0416         host->pio_ptr = p;
0417         host->pio_size = s;
0418         irq_handled = 1;
0419     } else if (host->pio_size &&
0420            (intr_status & host->intr_en &
0421             (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
0422         u16 *p = host->pio_ptr;
0423         int s = host->pio_size;
0424         /*
0425          * The TX_FIFO_8W bit is unreliable. When set, bursting
0426          * 16 halfwords all at once in the FIFO drops data. Actually
0427          * TX_AVAIL does go off after only one word is pushed even if
0428          * TX_FIFO_8W remains set.
0429          */
0430         while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
0431             mvsd_write(MVSD_FIFO, get_unaligned(p++));
0432             mvsd_write(MVSD_FIFO, get_unaligned(p++));
0433             s -= 4;
0434             intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
0435         }
0436         if (s < 4) {
0437             if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
0438                 u16 val[2] = {0, 0};
0439                 memcpy(((void *)&val) + 4 - s, p, s);
0440                 mvsd_write(MVSD_FIFO, val[0]);
0441                 mvsd_write(MVSD_FIFO, val[1]);
0442                 s = 0;
0443                 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
0444             }
0445             if (s == 0) {
0446                 host->intr_en &=
0447                      ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
0448                 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
0449             }
0450         }
0451         dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
0452             s, intr_status, mvsd_read(MVSD_HW_STATE));
0453         host->pio_ptr = p;
0454         host->pio_size = s;
0455         irq_handled = 1;
0456     }
0457 
0458     mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
0459 
0460     intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
0461              MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
0462     if (intr_status & host->intr_en & ~intr_done_mask) {
0463         struct mmc_request *mrq = host->mrq;
0464         struct mmc_command *cmd = mrq->cmd;
0465         u32 err_status = 0;
0466 
0467         del_timer(&host->timer);
0468         host->mrq = NULL;
0469 
0470         host->intr_en &= MVSD_NOR_CARD_INT;
0471         mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
0472         mvsd_write(MVSD_ERR_INTR_EN, 0);
0473 
0474         spin_unlock(&host->lock);
0475 
0476         if (intr_status & MVSD_NOR_UNEXP_RSP) {
0477             cmd->error = -EPROTO;
0478         } else if (intr_status & MVSD_NOR_ERROR) {
0479             err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
0480             dev_dbg(host->dev, "err 0x%04x\n", err_status);
0481         }
0482 
0483         err_status = mvsd_finish_cmd(host, cmd, err_status);
0484         if (mrq->data)
0485             err_status = mvsd_finish_data(host, mrq->data, err_status);
0486         if (err_status) {
0487             dev_err(host->dev, "unhandled error status %#04x\n",
0488                 err_status);
0489             cmd->error = -ENOMSG;
0490         }
0491 
0492         mmc_request_done(host->mmc, mrq);
0493         irq_handled = 1;
0494     } else
0495         spin_unlock(&host->lock);
0496 
0497     if (intr_status & MVSD_NOR_CARD_INT) {
0498         mmc_signal_sdio_irq(host->mmc);
0499         irq_handled = 1;
0500     }
0501 
0502     if (irq_handled)
0503         return IRQ_HANDLED;
0504 
0505     dev_err(host->dev, "unhandled interrupt status=0x%04x en=0x%04x pio=%d\n",
0506         intr_status, host->intr_en, host->pio_size);
0507     return IRQ_NONE;
0508 }
0509 
0510 static void mvsd_timeout_timer(struct timer_list *t)
0511 {
0512     struct mvsd_host *host = from_timer(host, t, timer);
0513     void __iomem *iobase = host->base;
0514     struct mmc_request *mrq;
0515     unsigned long flags;
0516 
0517     spin_lock_irqsave(&host->lock, flags);
0518     mrq = host->mrq;
0519     if (mrq) {
0520         dev_err(host->dev, "Timeout waiting for hardware interrupt.\n");
0521         dev_err(host->dev, "hw_state=0x%04x, intr_status=0x%04x intr_en=0x%04x\n",
0522             mvsd_read(MVSD_HW_STATE),
0523             mvsd_read(MVSD_NOR_INTR_STATUS),
0524             mvsd_read(MVSD_NOR_INTR_EN));
0525 
0526         host->mrq = NULL;
0527 
0528         mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
0529 
0530         host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
0531         mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
0532 
0533         host->intr_en &= MVSD_NOR_CARD_INT;
0534         mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
0535         mvsd_write(MVSD_ERR_INTR_EN, 0);
0536         mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
0537 
0538         mrq->cmd->error = -ETIMEDOUT;
0539         mvsd_finish_cmd(host, mrq->cmd, 0);
0540         if (mrq->data) {
0541             mrq->data->error = -ETIMEDOUT;
0542             mvsd_finish_data(host, mrq->data, 0);
0543         }
0544     }
0545     spin_unlock_irqrestore(&host->lock, flags);
0546 
0547     if (mrq)
0548         mmc_request_done(host->mmc, mrq);
0549 }
0550 
0551 static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
0552 {
0553     struct mvsd_host *host = mmc_priv(mmc);
0554     void __iomem *iobase = host->base;
0555     unsigned long flags;
0556 
0557     spin_lock_irqsave(&host->lock, flags);
0558     if (enable) {
0559         host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
0560         host->intr_en |= MVSD_NOR_CARD_INT;
0561     } else {
0562         host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
0563         host->intr_en &= ~MVSD_NOR_CARD_INT;
0564     }
0565     mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
0566     mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
0567     spin_unlock_irqrestore(&host->lock, flags);
0568 }
0569 
0570 static void mvsd_power_up(struct mvsd_host *host)
0571 {
0572     void __iomem *iobase = host->base;
0573     dev_dbg(host->dev, "power up\n");
0574     mvsd_write(MVSD_NOR_INTR_EN, 0);
0575     mvsd_write(MVSD_ERR_INTR_EN, 0);
0576     mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
0577     mvsd_write(MVSD_XFER_MODE, 0);
0578     mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
0579     mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
0580     mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
0581     mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
0582 }
0583 
0584 static void mvsd_power_down(struct mvsd_host *host)
0585 {
0586     void __iomem *iobase = host->base;
0587     dev_dbg(host->dev, "power down\n");
0588     mvsd_write(MVSD_NOR_INTR_EN, 0);
0589     mvsd_write(MVSD_ERR_INTR_EN, 0);
0590     mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
0591     mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
0592     mvsd_write(MVSD_NOR_STATUS_EN, 0);
0593     mvsd_write(MVSD_ERR_STATUS_EN, 0);
0594     mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
0595     mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
0596 }
0597 
0598 static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0599 {
0600     struct mvsd_host *host = mmc_priv(mmc);
0601     void __iomem *iobase = host->base;
0602     u32 ctrl_reg = 0;
0603 
0604     if (ios->power_mode == MMC_POWER_UP)
0605         mvsd_power_up(host);
0606 
0607     if (ios->clock == 0) {
0608         mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
0609         mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
0610         host->clock = 0;
0611         dev_dbg(host->dev, "clock off\n");
0612     } else if (ios->clock != host->clock) {
0613         u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
0614         if (m > MVSD_BASE_DIV_MAX)
0615             m = MVSD_BASE_DIV_MAX;
0616         mvsd_write(MVSD_CLK_DIV, m);
0617         host->clock = ios->clock;
0618         host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
0619         dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
0620             ios->clock, host->base_clock / (m+1), m);
0621     }
0622 
0623     /* default transfer mode */
0624     ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
0625     ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
0626 
0627     /* default to maximum timeout */
0628     ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
0629     ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
0630 
0631     if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
0632         ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
0633 
0634     if (ios->bus_width == MMC_BUS_WIDTH_4)
0635         ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
0636 
0637     /*
0638      * The HI_SPEED_EN bit is causing trouble with many (but not all)
0639      * high speed SD, SDHC and SDIO cards.  Not enabling that bit
0640      * makes all cards work.  So let's just ignore that bit for now
0641      * and revisit this issue if problems for not enabling this bit
0642      * are ever reported.
0643      */
0644 #if 0
0645     if (ios->timing == MMC_TIMING_MMC_HS ||
0646         ios->timing == MMC_TIMING_SD_HS)
0647         ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
0648 #endif
0649 
0650     host->ctrl = ctrl_reg;
0651     mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
0652     dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
0653         (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
0654             "push-pull" : "open-drain",
0655         (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
0656             "4bit-width" : "1bit-width",
0657         (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
0658             "high-speed" : "");
0659 
0660     if (ios->power_mode == MMC_POWER_OFF)
0661         mvsd_power_down(host);
0662 }
0663 
0664 static const struct mmc_host_ops mvsd_ops = {
0665     .request        = mvsd_request,
0666     .get_ro         = mmc_gpio_get_ro,
0667     .set_ios        = mvsd_set_ios,
0668     .enable_sdio_irq    = mvsd_enable_sdio_irq,
0669 };
0670 
0671 static void
0672 mv_conf_mbus_windows(struct mvsd_host *host,
0673              const struct mbus_dram_target_info *dram)
0674 {
0675     void __iomem *iobase = host->base;
0676     int i;
0677 
0678     for (i = 0; i < 4; i++) {
0679         writel(0, iobase + MVSD_WINDOW_CTRL(i));
0680         writel(0, iobase + MVSD_WINDOW_BASE(i));
0681     }
0682 
0683     for (i = 0; i < dram->num_cs; i++) {
0684         const struct mbus_dram_window *cs = dram->cs + i;
0685         writel(((cs->size - 1) & 0xffff0000) |
0686                (cs->mbus_attr << 8) |
0687                (dram->mbus_dram_target_id << 4) | 1,
0688                iobase + MVSD_WINDOW_CTRL(i));
0689         writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
0690     }
0691 }
0692 
0693 static int mvsd_probe(struct platform_device *pdev)
0694 {
0695     struct device_node *np = pdev->dev.of_node;
0696     struct mmc_host *mmc = NULL;
0697     struct mvsd_host *host = NULL;
0698     const struct mbus_dram_target_info *dram;
0699     int ret, irq;
0700 
0701     if (!np) {
0702         dev_err(&pdev->dev, "no DT node\n");
0703         return -ENODEV;
0704     }
0705     irq = platform_get_irq(pdev, 0);
0706     if (irq < 0)
0707         return -ENXIO;
0708 
0709     mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
0710     if (!mmc) {
0711         ret = -ENOMEM;
0712         goto out;
0713     }
0714 
0715     host = mmc_priv(mmc);
0716     host->mmc = mmc;
0717     host->dev = &pdev->dev;
0718 
0719     /*
0720      * Some non-DT platforms do not pass a clock, and the clock
0721      * frequency is passed through platform_data. On DT platforms,
0722      * a clock must always be passed, even if there is no gatable
0723      * clock associated to the SDIO interface (it can simply be a
0724      * fixed rate clock).
0725      */
0726     host->clk = devm_clk_get(&pdev->dev, NULL);
0727     if (IS_ERR(host->clk)) {
0728         dev_err(&pdev->dev, "no clock associated\n");
0729         ret = -EINVAL;
0730         goto out;
0731     }
0732     clk_prepare_enable(host->clk);
0733 
0734     mmc->ops = &mvsd_ops;
0735 
0736     mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
0737 
0738     mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
0739     mmc->f_max = MVSD_CLOCKRATE_MAX;
0740 
0741     mmc->max_blk_size = 2048;
0742     mmc->max_blk_count = 65535;
0743 
0744     mmc->max_segs = 1;
0745     mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
0746     mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
0747 
0748     host->base_clock = clk_get_rate(host->clk) / 2;
0749     ret = mmc_of_parse(mmc);
0750     if (ret < 0)
0751         goto out;
0752     if (maxfreq)
0753         mmc->f_max = maxfreq;
0754 
0755     spin_lock_init(&host->lock);
0756 
0757     host->base = devm_platform_ioremap_resource(pdev, 0);
0758     if (IS_ERR(host->base)) {
0759         ret = PTR_ERR(host->base);
0760         goto out;
0761     }
0762 
0763     /* (Re-)program MBUS remapping windows if we are asked to. */
0764     dram = mv_mbus_dram_info();
0765     if (dram)
0766         mv_conf_mbus_windows(host, dram);
0767 
0768     mvsd_power_down(host);
0769 
0770     ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host);
0771     if (ret) {
0772         dev_err(&pdev->dev, "cannot assign irq %d\n", irq);
0773         goto out;
0774     }
0775 
0776     timer_setup(&host->timer, mvsd_timeout_timer, 0);
0777     platform_set_drvdata(pdev, mmc);
0778     ret = mmc_add_host(mmc);
0779     if (ret)
0780         goto out;
0781 
0782     if (!(mmc->caps & MMC_CAP_NEEDS_POLL))
0783         dev_dbg(&pdev->dev, "using GPIO for card detection\n");
0784     else
0785         dev_dbg(&pdev->dev, "lacking card detect (fall back to polling)\n");
0786 
0787     return 0;
0788 
0789 out:
0790     if (mmc) {
0791         if (!IS_ERR(host->clk))
0792             clk_disable_unprepare(host->clk);
0793         mmc_free_host(mmc);
0794     }
0795 
0796     return ret;
0797 }
0798 
0799 static int mvsd_remove(struct platform_device *pdev)
0800 {
0801     struct mmc_host *mmc = platform_get_drvdata(pdev);
0802 
0803     struct mvsd_host *host = mmc_priv(mmc);
0804 
0805     mmc_remove_host(mmc);
0806     del_timer_sync(&host->timer);
0807     mvsd_power_down(host);
0808 
0809     if (!IS_ERR(host->clk))
0810         clk_disable_unprepare(host->clk);
0811     mmc_free_host(mmc);
0812 
0813     return 0;
0814 }
0815 
0816 static const struct of_device_id mvsdio_dt_ids[] = {
0817     { .compatible = "marvell,orion-sdio" },
0818     { /* sentinel */ }
0819 };
0820 MODULE_DEVICE_TABLE(of, mvsdio_dt_ids);
0821 
0822 static struct platform_driver mvsd_driver = {
0823     .probe      = mvsd_probe,
0824     .remove     = mvsd_remove,
0825     .driver     = {
0826         .name   = DRIVER_NAME,
0827         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0828         .of_match_table = mvsdio_dt_ids,
0829     },
0830 };
0831 
0832 module_platform_driver(mvsd_driver);
0833 
0834 /* maximum card clock frequency (default 50MHz) */
0835 module_param(maxfreq, int, 0);
0836 
0837 /* force PIO transfers all the time */
0838 module_param(nodma, int, 0);
0839 
0840 MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
0841 MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
0842 MODULE_LICENSE("GPL");
0843 MODULE_ALIAS("platform:mvsdio");
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