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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014-2015, 2022 MediaTek Inc.
0004  * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
0005  */
0006 
0007 #include <linux/module.h>
0008 #include <linux/bitops.h>
0009 #include <linux/clk.h>
0010 #include <linux/delay.h>
0011 #include <linux/dma-mapping.h>
0012 #include <linux/iopoll.h>
0013 #include <linux/ioport.h>
0014 #include <linux/irq.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_device.h>
0017 #include <linux/of_irq.h>
0018 #include <linux/of_gpio.h>
0019 #include <linux/pinctrl/consumer.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/pm.h>
0022 #include <linux/pm_runtime.h>
0023 #include <linux/pm_wakeirq.h>
0024 #include <linux/regulator/consumer.h>
0025 #include <linux/slab.h>
0026 #include <linux/spinlock.h>
0027 #include <linux/interrupt.h>
0028 #include <linux/reset.h>
0029 
0030 #include <linux/mmc/card.h>
0031 #include <linux/mmc/core.h>
0032 #include <linux/mmc/host.h>
0033 #include <linux/mmc/mmc.h>
0034 #include <linux/mmc/sd.h>
0035 #include <linux/mmc/sdio.h>
0036 #include <linux/mmc/slot-gpio.h>
0037 
0038 #include "cqhci.h"
0039 
0040 #define MAX_BD_NUM          1024
0041 #define MSDC_NR_CLOCKS      3
0042 
0043 /*--------------------------------------------------------------------------*/
0044 /* Common Definition                                                        */
0045 /*--------------------------------------------------------------------------*/
0046 #define MSDC_BUS_1BITS          0x0
0047 #define MSDC_BUS_4BITS          0x1
0048 #define MSDC_BUS_8BITS          0x2
0049 
0050 #define MSDC_BURST_64B          0x6
0051 
0052 /*--------------------------------------------------------------------------*/
0053 /* Register Offset                                                          */
0054 /*--------------------------------------------------------------------------*/
0055 #define MSDC_CFG         0x0
0056 #define MSDC_IOCON       0x04
0057 #define MSDC_PS          0x08
0058 #define MSDC_INT         0x0c
0059 #define MSDC_INTEN       0x10
0060 #define MSDC_FIFOCS      0x14
0061 #define SDC_CFG          0x30
0062 #define SDC_CMD          0x34
0063 #define SDC_ARG          0x38
0064 #define SDC_STS          0x3c
0065 #define SDC_RESP0        0x40
0066 #define SDC_RESP1        0x44
0067 #define SDC_RESP2        0x48
0068 #define SDC_RESP3        0x4c
0069 #define SDC_BLK_NUM      0x50
0070 #define SDC_ADV_CFG0     0x64
0071 #define EMMC_IOCON       0x7c
0072 #define SDC_ACMD_RESP    0x80
0073 #define DMA_SA_H4BIT     0x8c
0074 #define MSDC_DMA_SA      0x90
0075 #define MSDC_DMA_CTRL    0x98
0076 #define MSDC_DMA_CFG     0x9c
0077 #define MSDC_PATCH_BIT   0xb0
0078 #define MSDC_PATCH_BIT1  0xb4
0079 #define MSDC_PATCH_BIT2  0xb8
0080 #define MSDC_PAD_TUNE    0xec
0081 #define MSDC_PAD_TUNE0   0xf0
0082 #define PAD_DS_TUNE      0x188
0083 #define PAD_CMD_TUNE     0x18c
0084 #define EMMC51_CFG0  0x204
0085 #define EMMC50_CFG0      0x208
0086 #define EMMC50_CFG1      0x20c
0087 #define EMMC50_CFG3      0x220
0088 #define SDC_FIFO_CFG     0x228
0089 #define CQHCI_SETTING    0x7fc
0090 
0091 /*--------------------------------------------------------------------------*/
0092 /* Top Pad Register Offset                                                  */
0093 /*--------------------------------------------------------------------------*/
0094 #define EMMC_TOP_CONTROL    0x00
0095 #define EMMC_TOP_CMD        0x04
0096 #define EMMC50_PAD_DS_TUNE  0x0c
0097 
0098 /*--------------------------------------------------------------------------*/
0099 /* Register Mask                                                            */
0100 /*--------------------------------------------------------------------------*/
0101 
0102 /* MSDC_CFG mask */
0103 #define MSDC_CFG_MODE           BIT(0)  /* RW */
0104 #define MSDC_CFG_CKPDN          BIT(1)  /* RW */
0105 #define MSDC_CFG_RST            BIT(2)  /* RW */
0106 #define MSDC_CFG_PIO            BIT(3)  /* RW */
0107 #define MSDC_CFG_CKDRVEN        BIT(4)  /* RW */
0108 #define MSDC_CFG_BV18SDT        BIT(5)  /* RW */
0109 #define MSDC_CFG_BV18PSS        BIT(6)  /* R  */
0110 #define MSDC_CFG_CKSTB          BIT(7)  /* R  */
0111 #define MSDC_CFG_CKDIV          GENMASK(15, 8)  /* RW */
0112 #define MSDC_CFG_CKMOD          GENMASK(17, 16) /* RW */
0113 #define MSDC_CFG_HS400_CK_MODE  BIT(18) /* RW */
0114 #define MSDC_CFG_HS400_CK_MODE_EXTRA  BIT(22)   /* RW */
0115 #define MSDC_CFG_CKDIV_EXTRA    GENMASK(19, 8)  /* RW */
0116 #define MSDC_CFG_CKMOD_EXTRA    GENMASK(21, 20) /* RW */
0117 
0118 /* MSDC_IOCON mask */
0119 #define MSDC_IOCON_SDR104CKS    BIT(0)  /* RW */
0120 #define MSDC_IOCON_RSPL         BIT(1)  /* RW */
0121 #define MSDC_IOCON_DSPL         BIT(2)  /* RW */
0122 #define MSDC_IOCON_DDLSEL       BIT(3)  /* RW */
0123 #define MSDC_IOCON_DDR50CKD     BIT(4)  /* RW */
0124 #define MSDC_IOCON_DSPLSEL      BIT(5)  /* RW */
0125 #define MSDC_IOCON_W_DSPL       BIT(8)  /* RW */
0126 #define MSDC_IOCON_D0SPL        BIT(16) /* RW */
0127 #define MSDC_IOCON_D1SPL        BIT(17) /* RW */
0128 #define MSDC_IOCON_D2SPL        BIT(18) /* RW */
0129 #define MSDC_IOCON_D3SPL        BIT(19) /* RW */
0130 #define MSDC_IOCON_D4SPL        BIT(20) /* RW */
0131 #define MSDC_IOCON_D5SPL        BIT(21) /* RW */
0132 #define MSDC_IOCON_D6SPL        BIT(22) /* RW */
0133 #define MSDC_IOCON_D7SPL        BIT(23) /* RW */
0134 #define MSDC_IOCON_RISCSZ       GENMASK(25, 24) /* RW */
0135 
0136 /* MSDC_PS mask */
0137 #define MSDC_PS_CDEN            BIT(0)  /* RW */
0138 #define MSDC_PS_CDSTS           BIT(1)  /* R  */
0139 #define MSDC_PS_CDDEBOUNCE      GENMASK(15, 12) /* RW */
0140 #define MSDC_PS_DAT             GENMASK(23, 16) /* R  */
0141 #define MSDC_PS_DATA1           BIT(17) /* R  */
0142 #define MSDC_PS_CMD             BIT(24) /* R  */
0143 #define MSDC_PS_WP              BIT(31) /* R  */
0144 
0145 /* MSDC_INT mask */
0146 #define MSDC_INT_MMCIRQ         BIT(0)  /* W1C */
0147 #define MSDC_INT_CDSC           BIT(1)  /* W1C */
0148 #define MSDC_INT_ACMDRDY        BIT(3)  /* W1C */
0149 #define MSDC_INT_ACMDTMO        BIT(4)  /* W1C */
0150 #define MSDC_INT_ACMDCRCERR     BIT(5)  /* W1C */
0151 #define MSDC_INT_DMAQ_EMPTY     BIT(6)  /* W1C */
0152 #define MSDC_INT_SDIOIRQ        BIT(7)  /* W1C */
0153 #define MSDC_INT_CMDRDY         BIT(8)  /* W1C */
0154 #define MSDC_INT_CMDTMO         BIT(9)  /* W1C */
0155 #define MSDC_INT_RSPCRCERR      BIT(10) /* W1C */
0156 #define MSDC_INT_CSTA           BIT(11) /* R */
0157 #define MSDC_INT_XFER_COMPL     BIT(12) /* W1C */
0158 #define MSDC_INT_DXFER_DONE     BIT(13) /* W1C */
0159 #define MSDC_INT_DATTMO         BIT(14) /* W1C */
0160 #define MSDC_INT_DATCRCERR      BIT(15) /* W1C */
0161 #define MSDC_INT_ACMD19_DONE    BIT(16) /* W1C */
0162 #define MSDC_INT_DMA_BDCSERR    BIT(17) /* W1C */
0163 #define MSDC_INT_DMA_GPDCSERR   BIT(18) /* W1C */
0164 #define MSDC_INT_DMA_PROTECT    BIT(19) /* W1C */
0165 #define MSDC_INT_CMDQ           BIT(28) /* W1C */
0166 
0167 /* MSDC_INTEN mask */
0168 #define MSDC_INTEN_MMCIRQ       BIT(0)  /* RW */
0169 #define MSDC_INTEN_CDSC         BIT(1)  /* RW */
0170 #define MSDC_INTEN_ACMDRDY      BIT(3)  /* RW */
0171 #define MSDC_INTEN_ACMDTMO      BIT(4)  /* RW */
0172 #define MSDC_INTEN_ACMDCRCERR   BIT(5)  /* RW */
0173 #define MSDC_INTEN_DMAQ_EMPTY   BIT(6)  /* RW */
0174 #define MSDC_INTEN_SDIOIRQ      BIT(7)  /* RW */
0175 #define MSDC_INTEN_CMDRDY       BIT(8)  /* RW */
0176 #define MSDC_INTEN_CMDTMO       BIT(9)  /* RW */
0177 #define MSDC_INTEN_RSPCRCERR    BIT(10) /* RW */
0178 #define MSDC_INTEN_CSTA         BIT(11) /* RW */
0179 #define MSDC_INTEN_XFER_COMPL   BIT(12) /* RW */
0180 #define MSDC_INTEN_DXFER_DONE   BIT(13) /* RW */
0181 #define MSDC_INTEN_DATTMO       BIT(14) /* RW */
0182 #define MSDC_INTEN_DATCRCERR    BIT(15) /* RW */
0183 #define MSDC_INTEN_ACMD19_DONE  BIT(16) /* RW */
0184 #define MSDC_INTEN_DMA_BDCSERR  BIT(17) /* RW */
0185 #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */
0186 #define MSDC_INTEN_DMA_PROTECT  BIT(19) /* RW */
0187 
0188 /* MSDC_FIFOCS mask */
0189 #define MSDC_FIFOCS_RXCNT       GENMASK(7, 0)   /* R */
0190 #define MSDC_FIFOCS_TXCNT       GENMASK(23, 16) /* R */
0191 #define MSDC_FIFOCS_CLR         BIT(31) /* RW */
0192 
0193 /* SDC_CFG mask */
0194 #define SDC_CFG_SDIOINTWKUP     BIT(0)  /* RW */
0195 #define SDC_CFG_INSWKUP         BIT(1)  /* RW */
0196 #define SDC_CFG_WRDTOC          GENMASK(14, 2)  /* RW */
0197 #define SDC_CFG_BUSWIDTH        GENMASK(17, 16) /* RW */
0198 #define SDC_CFG_SDIO            BIT(19) /* RW */
0199 #define SDC_CFG_SDIOIDE         BIT(20) /* RW */
0200 #define SDC_CFG_INTATGAP        BIT(21) /* RW */
0201 #define SDC_CFG_DTOC            GENMASK(31, 24) /* RW */
0202 
0203 /* SDC_STS mask */
0204 #define SDC_STS_SDCBUSY         BIT(0)  /* RW */
0205 #define SDC_STS_CMDBUSY         BIT(1)  /* RW */
0206 #define SDC_STS_SWR_COMPL       BIT(31) /* RW */
0207 
0208 #define SDC_DAT1_IRQ_TRIGGER    BIT(19) /* RW */
0209 /* SDC_ADV_CFG0 mask */
0210 #define SDC_RX_ENHANCE_EN   BIT(20) /* RW */
0211 
0212 /* DMA_SA_H4BIT mask */
0213 #define DMA_ADDR_HIGH_4BIT      GENMASK(3, 0)   /* RW */
0214 
0215 /* MSDC_DMA_CTRL mask */
0216 #define MSDC_DMA_CTRL_START     BIT(0)  /* W */
0217 #define MSDC_DMA_CTRL_STOP      BIT(1)  /* W */
0218 #define MSDC_DMA_CTRL_RESUME    BIT(2)  /* W */
0219 #define MSDC_DMA_CTRL_MODE      BIT(8)  /* RW */
0220 #define MSDC_DMA_CTRL_LASTBUF   BIT(10) /* RW */
0221 #define MSDC_DMA_CTRL_BRUSTSZ   GENMASK(14, 12) /* RW */
0222 
0223 /* MSDC_DMA_CFG mask */
0224 #define MSDC_DMA_CFG_STS        BIT(0)  /* R */
0225 #define MSDC_DMA_CFG_DECSEN     BIT(1)  /* RW */
0226 #define MSDC_DMA_CFG_AHBHPROT2  BIT(9)  /* RW */
0227 #define MSDC_DMA_CFG_ACTIVEEN   BIT(13) /* RW */
0228 #define MSDC_DMA_CFG_CS12B16B   BIT(16) /* RW */
0229 
0230 /* MSDC_PATCH_BIT mask */
0231 #define MSDC_PATCH_BIT_ODDSUPP    BIT(1)    /* RW */
0232 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
0233 #define MSDC_CKGEN_MSDC_DLY_SEL   GENMASK(14, 10)
0234 #define MSDC_PATCH_BIT_IODSSEL    BIT(16)   /* RW */
0235 #define MSDC_PATCH_BIT_IOINTSEL   BIT(17)   /* RW */
0236 #define MSDC_PATCH_BIT_BUSYDLY    GENMASK(21, 18)   /* RW */
0237 #define MSDC_PATCH_BIT_WDOD       GENMASK(25, 22)   /* RW */
0238 #define MSDC_PATCH_BIT_IDRTSEL    BIT(26)   /* RW */
0239 #define MSDC_PATCH_BIT_CMDFSEL    BIT(27)   /* RW */
0240 #define MSDC_PATCH_BIT_INTDLSEL   BIT(28)   /* RW */
0241 #define MSDC_PATCH_BIT_SPCPUSH    BIT(29)   /* RW */
0242 #define MSDC_PATCH_BIT_DECRCTMO   BIT(30)   /* RW */
0243 
0244 #define MSDC_PATCH_BIT1_CMDTA     GENMASK(5, 3)    /* RW */
0245 #define MSDC_PB1_BUSY_CHECK_SEL   BIT(7)    /* RW */
0246 #define MSDC_PATCH_BIT1_STOP_DLY  GENMASK(11, 8)    /* RW */
0247 
0248 #define MSDC_PATCH_BIT2_CFGRESP   BIT(15)   /* RW */
0249 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28)   /* RW */
0250 #define MSDC_PB2_SUPPORT_64G      BIT(1)    /* RW */
0251 #define MSDC_PB2_RESPWAIT         GENMASK(3, 2)   /* RW */
0252 #define MSDC_PB2_RESPSTSENSEL     GENMASK(18, 16) /* RW */
0253 #define MSDC_PB2_CRCSTSENSEL      GENMASK(31, 29) /* RW */
0254 
0255 #define MSDC_PAD_TUNE_DATWRDLY    GENMASK(4, 0)     /* RW */
0256 #define MSDC_PAD_TUNE_DATRRDLY    GENMASK(12, 8)    /* RW */
0257 #define MSDC_PAD_TUNE_CMDRDLY     GENMASK(20, 16)   /* RW */
0258 #define MSDC_PAD_TUNE_CMDRRDLY    GENMASK(26, 22)   /* RW */
0259 #define MSDC_PAD_TUNE_CLKTDLY     GENMASK(31, 27)   /* RW */
0260 #define MSDC_PAD_TUNE_RXDLYSEL    BIT(15)   /* RW */
0261 #define MSDC_PAD_TUNE_RD_SEL      BIT(13)   /* RW */
0262 #define MSDC_PAD_TUNE_CMD_SEL     BIT(21)   /* RW */
0263 
0264 #define PAD_DS_TUNE_DLY_SEL       BIT(0)      /* RW */
0265 #define PAD_DS_TUNE_DLY1      GENMASK(6, 2)   /* RW */
0266 #define PAD_DS_TUNE_DLY2      GENMASK(11, 7)  /* RW */
0267 #define PAD_DS_TUNE_DLY3      GENMASK(16, 12) /* RW */
0268 
0269 #define PAD_CMD_TUNE_RX_DLY3      GENMASK(5, 1)   /* RW */
0270 
0271 /* EMMC51_CFG0 mask */
0272 #define CMDQ_RDAT_CNT         GENMASK(21, 12) /* RW */
0273 
0274 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0)   /* RW */
0275 #define EMMC50_CFG_CRCSTS_EDGE    BIT(3)   /* RW */
0276 #define EMMC50_CFG_CFCSTS_SEL     BIT(4)   /* RW */
0277 #define EMMC50_CFG_CMD_RESP_SEL   BIT(9)   /* RW */
0278 
0279 /* EMMC50_CFG1 mask */
0280 #define EMMC50_CFG1_DS_CFG        BIT(28)  /* RW */
0281 
0282 #define EMMC50_CFG3_OUTS_WR       GENMASK(4, 0)  /* RW */
0283 
0284 #define SDC_FIFO_CFG_WRVALIDSEL   BIT(24)  /* RW */
0285 #define SDC_FIFO_CFG_RDVALIDSEL   BIT(25)  /* RW */
0286 
0287 /* CQHCI_SETTING */
0288 #define CQHCI_RD_CMD_WND_SEL      BIT(14) /* RW */
0289 #define CQHCI_WR_CMD_WND_SEL      BIT(15) /* RW */
0290 
0291 /* EMMC_TOP_CONTROL mask */
0292 #define PAD_RXDLY_SEL           BIT(0)      /* RW */
0293 #define DELAY_EN                BIT(1)      /* RW */
0294 #define PAD_DAT_RD_RXDLY2       GENMASK(6, 2)     /* RW */
0295 #define PAD_DAT_RD_RXDLY        GENMASK(11, 7)    /* RW */
0296 #define PAD_DAT_RD_RXDLY2_SEL   BIT(12)     /* RW */
0297 #define PAD_DAT_RD_RXDLY_SEL    BIT(13)     /* RW */
0298 #define DATA_K_VALUE_SEL        BIT(14)     /* RW */
0299 #define SDC_RX_ENH_EN           BIT(15)     /* TW */
0300 
0301 /* EMMC_TOP_CMD mask */
0302 #define PAD_CMD_RXDLY2          GENMASK(4, 0)   /* RW */
0303 #define PAD_CMD_RXDLY           GENMASK(9, 5)   /* RW */
0304 #define PAD_CMD_RD_RXDLY2_SEL   BIT(10)     /* RW */
0305 #define PAD_CMD_RD_RXDLY_SEL    BIT(11)     /* RW */
0306 #define PAD_CMD_TX_DLY          GENMASK(16, 12) /* RW */
0307 
0308 /* EMMC50_PAD_DS_TUNE mask */
0309 #define PAD_DS_DLY_SEL      BIT(16) /* RW */
0310 #define PAD_DS_DLY1     GENMASK(14, 10) /* RW */
0311 #define PAD_DS_DLY3     GENMASK(4, 0)   /* RW */
0312 
0313 #define REQ_CMD_EIO  BIT(0)
0314 #define REQ_CMD_TMO  BIT(1)
0315 #define REQ_DAT_ERR  BIT(2)
0316 #define REQ_STOP_EIO BIT(3)
0317 #define REQ_STOP_TMO BIT(4)
0318 #define REQ_CMD_BUSY BIT(5)
0319 
0320 #define MSDC_PREPARE_FLAG BIT(0)
0321 #define MSDC_ASYNC_FLAG BIT(1)
0322 #define MSDC_MMAP_FLAG BIT(2)
0323 
0324 #define MTK_MMC_AUTOSUSPEND_DELAY   50
0325 #define CMD_TIMEOUT         (HZ/10 * 5) /* 100ms x5 */
0326 #define DAT_TIMEOUT         (HZ    * 5) /* 1000ms x5 */
0327 
0328 #define DEFAULT_DEBOUNCE    (8) /* 8 cycles CD debounce */
0329 
0330 #define PAD_DELAY_MAX   32 /* PAD delay cells */
0331 /*--------------------------------------------------------------------------*/
0332 /* Descriptor Structure                                                     */
0333 /*--------------------------------------------------------------------------*/
0334 struct mt_gpdma_desc {
0335     u32 gpd_info;
0336 #define GPDMA_DESC_HWO      BIT(0)
0337 #define GPDMA_DESC_BDP      BIT(1)
0338 #define GPDMA_DESC_CHECKSUM GENMASK(15, 8)
0339 #define GPDMA_DESC_INT      BIT(16)
0340 #define GPDMA_DESC_NEXT_H4  GENMASK(27, 24)
0341 #define GPDMA_DESC_PTR_H4   GENMASK(31, 28)
0342     u32 next;
0343     u32 ptr;
0344     u32 gpd_data_len;
0345 #define GPDMA_DESC_BUFLEN   GENMASK(15, 0)
0346 #define GPDMA_DESC_EXTLEN   GENMASK(23, 16)
0347     u32 arg;
0348     u32 blknum;
0349     u32 cmd;
0350 };
0351 
0352 struct mt_bdma_desc {
0353     u32 bd_info;
0354 #define BDMA_DESC_EOL       BIT(0)
0355 #define BDMA_DESC_CHECKSUM  GENMASK(15, 8)
0356 #define BDMA_DESC_BLKPAD    BIT(17)
0357 #define BDMA_DESC_DWPAD     BIT(18)
0358 #define BDMA_DESC_NEXT_H4   GENMASK(27, 24)
0359 #define BDMA_DESC_PTR_H4    GENMASK(31, 28)
0360     u32 next;
0361     u32 ptr;
0362     u32 bd_data_len;
0363 #define BDMA_DESC_BUFLEN    GENMASK(15, 0)
0364 #define BDMA_DESC_BUFLEN_EXT    GENMASK(23, 0)
0365 };
0366 
0367 struct msdc_dma {
0368     struct scatterlist *sg; /* I/O scatter list */
0369     struct mt_gpdma_desc *gpd;      /* pointer to gpd array */
0370     struct mt_bdma_desc *bd;        /* pointer to bd array */
0371     dma_addr_t gpd_addr;    /* the physical address of gpd array */
0372     dma_addr_t bd_addr; /* the physical address of bd array */
0373 };
0374 
0375 struct msdc_save_para {
0376     u32 msdc_cfg;
0377     u32 iocon;
0378     u32 sdc_cfg;
0379     u32 pad_tune;
0380     u32 patch_bit0;
0381     u32 patch_bit1;
0382     u32 patch_bit2;
0383     u32 pad_ds_tune;
0384     u32 pad_cmd_tune;
0385     u32 emmc50_cfg0;
0386     u32 emmc50_cfg3;
0387     u32 sdc_fifo_cfg;
0388     u32 emmc_top_control;
0389     u32 emmc_top_cmd;
0390     u32 emmc50_pad_ds_tune;
0391 };
0392 
0393 struct mtk_mmc_compatible {
0394     u8 clk_div_bits;
0395     bool recheck_sdio_irq;
0396     bool hs400_tune; /* only used for MT8173 */
0397     u32 pad_tune_reg;
0398     bool async_fifo;
0399     bool data_tune;
0400     bool busy_check;
0401     bool stop_clk_fix;
0402     bool enhance_rx;
0403     bool support_64g;
0404     bool use_internal_cd;
0405 };
0406 
0407 struct msdc_tune_para {
0408     u32 iocon;
0409     u32 pad_tune;
0410     u32 pad_cmd_tune;
0411     u32 emmc_top_control;
0412     u32 emmc_top_cmd;
0413 };
0414 
0415 struct msdc_delay_phase {
0416     u8 maxlen;
0417     u8 start;
0418     u8 final_phase;
0419 };
0420 
0421 struct msdc_host {
0422     struct device *dev;
0423     const struct mtk_mmc_compatible *dev_comp;
0424     int cmd_rsp;
0425 
0426     spinlock_t lock;
0427     struct mmc_request *mrq;
0428     struct mmc_command *cmd;
0429     struct mmc_data *data;
0430     int error;
0431 
0432     void __iomem *base;     /* host base address */
0433     void __iomem *top_base;     /* host top register base address */
0434 
0435     struct msdc_dma dma;    /* dma channel */
0436     u64 dma_mask;
0437 
0438     u32 timeout_ns;     /* data timeout ns */
0439     u32 timeout_clks;   /* data timeout clks */
0440 
0441     struct pinctrl *pinctrl;
0442     struct pinctrl_state *pins_default;
0443     struct pinctrl_state *pins_uhs;
0444     struct pinctrl_state *pins_eint;
0445     struct delayed_work req_timeout;
0446     int irq;        /* host interrupt */
0447     int eint_irq;       /* interrupt from sdio device for waking up system */
0448     struct reset_control *reset;
0449 
0450     struct clk *src_clk;    /* msdc source clock */
0451     struct clk *h_clk;      /* msdc h_clk */
0452     struct clk *bus_clk;    /* bus clock which used to access register */
0453     struct clk *src_clk_cg; /* msdc source clock control gate */
0454     struct clk *sys_clk_cg; /* msdc subsys clock control gate */
0455     struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
0456     u32 mclk;       /* mmc subsystem clock frequency */
0457     u32 src_clk_freq;   /* source clock frequency */
0458     unsigned char timing;
0459     bool vqmmc_enabled;
0460     u32 latch_ck;
0461     u32 hs400_ds_delay;
0462     u32 hs400_ds_dly3;
0463     u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
0464     u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
0465     bool hs400_cmd_resp_sel_rising;
0466                  /* cmd response sample selection for HS400 */
0467     bool hs400_mode;    /* current eMMC will run at hs400 mode */
0468     bool hs400_tuning;  /* hs400 mode online tuning */
0469     bool internal_cd;   /* Use internal card-detect logic */
0470     bool cqhci;     /* support eMMC hw cmdq */
0471     struct msdc_save_para save_para; /* used when gate HCLK */
0472     struct msdc_tune_para def_tune_para; /* default tune setting */
0473     struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
0474     struct cqhci_host *cq_host;
0475 };
0476 
0477 static const struct mtk_mmc_compatible mt8135_compat = {
0478     .clk_div_bits = 8,
0479     .recheck_sdio_irq = true,
0480     .hs400_tune = false,
0481     .pad_tune_reg = MSDC_PAD_TUNE,
0482     .async_fifo = false,
0483     .data_tune = false,
0484     .busy_check = false,
0485     .stop_clk_fix = false,
0486     .enhance_rx = false,
0487     .support_64g = false,
0488 };
0489 
0490 static const struct mtk_mmc_compatible mt8173_compat = {
0491     .clk_div_bits = 8,
0492     .recheck_sdio_irq = true,
0493     .hs400_tune = true,
0494     .pad_tune_reg = MSDC_PAD_TUNE,
0495     .async_fifo = false,
0496     .data_tune = false,
0497     .busy_check = false,
0498     .stop_clk_fix = false,
0499     .enhance_rx = false,
0500     .support_64g = false,
0501 };
0502 
0503 static const struct mtk_mmc_compatible mt8183_compat = {
0504     .clk_div_bits = 12,
0505     .recheck_sdio_irq = false,
0506     .hs400_tune = false,
0507     .pad_tune_reg = MSDC_PAD_TUNE0,
0508     .async_fifo = true,
0509     .data_tune = true,
0510     .busy_check = true,
0511     .stop_clk_fix = true,
0512     .enhance_rx = true,
0513     .support_64g = true,
0514 };
0515 
0516 static const struct mtk_mmc_compatible mt2701_compat = {
0517     .clk_div_bits = 12,
0518     .recheck_sdio_irq = true,
0519     .hs400_tune = false,
0520     .pad_tune_reg = MSDC_PAD_TUNE0,
0521     .async_fifo = true,
0522     .data_tune = true,
0523     .busy_check = false,
0524     .stop_clk_fix = false,
0525     .enhance_rx = false,
0526     .support_64g = false,
0527 };
0528 
0529 static const struct mtk_mmc_compatible mt2712_compat = {
0530     .clk_div_bits = 12,
0531     .recheck_sdio_irq = false,
0532     .hs400_tune = false,
0533     .pad_tune_reg = MSDC_PAD_TUNE0,
0534     .async_fifo = true,
0535     .data_tune = true,
0536     .busy_check = true,
0537     .stop_clk_fix = true,
0538     .enhance_rx = true,
0539     .support_64g = true,
0540 };
0541 
0542 static const struct mtk_mmc_compatible mt7622_compat = {
0543     .clk_div_bits = 12,
0544     .recheck_sdio_irq = true,
0545     .hs400_tune = false,
0546     .pad_tune_reg = MSDC_PAD_TUNE0,
0547     .async_fifo = true,
0548     .data_tune = true,
0549     .busy_check = true,
0550     .stop_clk_fix = true,
0551     .enhance_rx = true,
0552     .support_64g = false,
0553 };
0554 
0555 static const struct mtk_mmc_compatible mt8516_compat = {
0556     .clk_div_bits = 12,
0557     .recheck_sdio_irq = true,
0558     .hs400_tune = false,
0559     .pad_tune_reg = MSDC_PAD_TUNE0,
0560     .async_fifo = true,
0561     .data_tune = true,
0562     .busy_check = true,
0563     .stop_clk_fix = true,
0564 };
0565 
0566 static const struct mtk_mmc_compatible mt7620_compat = {
0567     .clk_div_bits = 8,
0568     .recheck_sdio_irq = true,
0569     .hs400_tune = false,
0570     .pad_tune_reg = MSDC_PAD_TUNE,
0571     .async_fifo = false,
0572     .data_tune = false,
0573     .busy_check = false,
0574     .stop_clk_fix = false,
0575     .enhance_rx = false,
0576     .use_internal_cd = true,
0577 };
0578 
0579 static const struct mtk_mmc_compatible mt6779_compat = {
0580     .clk_div_bits = 12,
0581     .recheck_sdio_irq = false,
0582     .hs400_tune = false,
0583     .pad_tune_reg = MSDC_PAD_TUNE0,
0584     .async_fifo = true,
0585     .data_tune = true,
0586     .busy_check = true,
0587     .stop_clk_fix = true,
0588     .enhance_rx = true,
0589     .support_64g = true,
0590 };
0591 
0592 static const struct of_device_id msdc_of_ids[] = {
0593     { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
0594     { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
0595     { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
0596     { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
0597     { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
0598     { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
0599     { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
0600     { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
0601     { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
0602     {}
0603 };
0604 MODULE_DEVICE_TABLE(of, msdc_of_ids);
0605 
0606 static void sdr_set_bits(void __iomem *reg, u32 bs)
0607 {
0608     u32 val = readl(reg);
0609 
0610     val |= bs;
0611     writel(val, reg);
0612 }
0613 
0614 static void sdr_clr_bits(void __iomem *reg, u32 bs)
0615 {
0616     u32 val = readl(reg);
0617 
0618     val &= ~bs;
0619     writel(val, reg);
0620 }
0621 
0622 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
0623 {
0624     unsigned int tv = readl(reg);
0625 
0626     tv &= ~field;
0627     tv |= ((val) << (ffs((unsigned int)field) - 1));
0628     writel(tv, reg);
0629 }
0630 
0631 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
0632 {
0633     unsigned int tv = readl(reg);
0634 
0635     *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
0636 }
0637 
0638 static void msdc_reset_hw(struct msdc_host *host)
0639 {
0640     u32 val;
0641 
0642     sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
0643     readl_poll_timeout(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
0644 
0645     sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
0646     readl_poll_timeout(host->base + MSDC_FIFOCS, val,
0647                !(val & MSDC_FIFOCS_CLR), 0, 0);
0648 
0649     val = readl(host->base + MSDC_INT);
0650     writel(val, host->base + MSDC_INT);
0651 }
0652 
0653 static void msdc_cmd_next(struct msdc_host *host,
0654         struct mmc_request *mrq, struct mmc_command *cmd);
0655 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
0656 
0657 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
0658             MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
0659             MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
0660 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
0661             MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
0662             MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
0663 
0664 static u8 msdc_dma_calcs(u8 *buf, u32 len)
0665 {
0666     u32 i, sum = 0;
0667 
0668     for (i = 0; i < len; i++)
0669         sum += buf[i];
0670     return 0xff - (u8) sum;
0671 }
0672 
0673 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
0674         struct mmc_data *data)
0675 {
0676     unsigned int j, dma_len;
0677     dma_addr_t dma_address;
0678     u32 dma_ctrl;
0679     struct scatterlist *sg;
0680     struct mt_gpdma_desc *gpd;
0681     struct mt_bdma_desc *bd;
0682 
0683     sg = data->sg;
0684 
0685     gpd = dma->gpd;
0686     bd = dma->bd;
0687 
0688     /* modify gpd */
0689     gpd->gpd_info |= GPDMA_DESC_HWO;
0690     gpd->gpd_info |= GPDMA_DESC_BDP;
0691     /* need to clear first. use these bits to calc checksum */
0692     gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
0693     gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
0694 
0695     /* modify bd */
0696     for_each_sg(data->sg, sg, data->sg_count, j) {
0697         dma_address = sg_dma_address(sg);
0698         dma_len = sg_dma_len(sg);
0699 
0700         /* init bd */
0701         bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
0702         bd[j].bd_info &= ~BDMA_DESC_DWPAD;
0703         bd[j].ptr = lower_32_bits(dma_address);
0704         if (host->dev_comp->support_64g) {
0705             bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
0706             bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
0707                      << 28;
0708         }
0709 
0710         if (host->dev_comp->support_64g) {
0711             bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
0712             bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
0713         } else {
0714             bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
0715             bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
0716         }
0717 
0718         if (j == data->sg_count - 1) /* the last bd */
0719             bd[j].bd_info |= BDMA_DESC_EOL;
0720         else
0721             bd[j].bd_info &= ~BDMA_DESC_EOL;
0722 
0723         /* checksume need to clear first */
0724         bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
0725         bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
0726     }
0727 
0728     sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
0729     dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
0730     dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
0731     dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
0732     writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
0733     if (host->dev_comp->support_64g)
0734         sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
0735                   upper_32_bits(dma->gpd_addr) & 0xf);
0736     writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
0737 }
0738 
0739 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
0740 {
0741     if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
0742         data->host_cookie |= MSDC_PREPARE_FLAG;
0743         data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
0744                         mmc_get_dma_dir(data));
0745     }
0746 }
0747 
0748 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
0749 {
0750     if (data->host_cookie & MSDC_ASYNC_FLAG)
0751         return;
0752 
0753     if (data->host_cookie & MSDC_PREPARE_FLAG) {
0754         dma_unmap_sg(host->dev, data->sg, data->sg_len,
0755                  mmc_get_dma_dir(data));
0756         data->host_cookie &= ~MSDC_PREPARE_FLAG;
0757     }
0758 }
0759 
0760 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
0761 {
0762     struct mmc_host *mmc = mmc_from_priv(host);
0763     u64 timeout, clk_ns;
0764     u32 mode = 0;
0765 
0766     if (mmc->actual_clock == 0) {
0767         timeout = 0;
0768     } else {
0769         clk_ns  = 1000000000ULL;
0770         do_div(clk_ns, mmc->actual_clock);
0771         timeout = ns + clk_ns - 1;
0772         do_div(timeout, clk_ns);
0773         timeout += clks;
0774         /* in 1048576 sclk cycle unit */
0775         timeout = DIV_ROUND_UP(timeout, BIT(20));
0776         if (host->dev_comp->clk_div_bits == 8)
0777             sdr_get_field(host->base + MSDC_CFG,
0778                       MSDC_CFG_CKMOD, &mode);
0779         else
0780             sdr_get_field(host->base + MSDC_CFG,
0781                       MSDC_CFG_CKMOD_EXTRA, &mode);
0782         /*DDR mode will double the clk cycles for data timeout */
0783         timeout = mode >= 2 ? timeout * 2 : timeout;
0784         timeout = timeout > 1 ? timeout - 1 : 0;
0785     }
0786     return timeout;
0787 }
0788 
0789 /* clock control primitives */
0790 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
0791 {
0792     u64 timeout;
0793 
0794     host->timeout_ns = ns;
0795     host->timeout_clks = clks;
0796 
0797     timeout = msdc_timeout_cal(host, ns, clks);
0798     sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
0799               (u32)(timeout > 255 ? 255 : timeout));
0800 }
0801 
0802 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
0803 {
0804     u64 timeout;
0805 
0806     timeout = msdc_timeout_cal(host, ns, clks);
0807     sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
0808               (u32)(timeout > 8191 ? 8191 : timeout));
0809 }
0810 
0811 static void msdc_gate_clock(struct msdc_host *host)
0812 {
0813     clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
0814     clk_disable_unprepare(host->src_clk_cg);
0815     clk_disable_unprepare(host->src_clk);
0816     clk_disable_unprepare(host->bus_clk);
0817     clk_disable_unprepare(host->h_clk);
0818 }
0819 
0820 static int msdc_ungate_clock(struct msdc_host *host)
0821 {
0822     u32 val;
0823     int ret;
0824 
0825     clk_prepare_enable(host->h_clk);
0826     clk_prepare_enable(host->bus_clk);
0827     clk_prepare_enable(host->src_clk);
0828     clk_prepare_enable(host->src_clk_cg);
0829     ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
0830     if (ret) {
0831         dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
0832         return ret;
0833     }
0834 
0835     return readl_poll_timeout(host->base + MSDC_CFG, val,
0836                   (val & MSDC_CFG_CKSTB), 1, 20000);
0837 }
0838 
0839 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
0840 {
0841     struct mmc_host *mmc = mmc_from_priv(host);
0842     u32 mode;
0843     u32 flags;
0844     u32 div;
0845     u32 sclk;
0846     u32 tune_reg = host->dev_comp->pad_tune_reg;
0847     u32 val;
0848 
0849     if (!hz) {
0850         dev_dbg(host->dev, "set mclk to 0\n");
0851         host->mclk = 0;
0852         mmc->actual_clock = 0;
0853         sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
0854         return;
0855     }
0856 
0857     flags = readl(host->base + MSDC_INTEN);
0858     sdr_clr_bits(host->base + MSDC_INTEN, flags);
0859     if (host->dev_comp->clk_div_bits == 8)
0860         sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
0861     else
0862         sdr_clr_bits(host->base + MSDC_CFG,
0863                  MSDC_CFG_HS400_CK_MODE_EXTRA);
0864     if (timing == MMC_TIMING_UHS_DDR50 ||
0865         timing == MMC_TIMING_MMC_DDR52 ||
0866         timing == MMC_TIMING_MMC_HS400) {
0867         if (timing == MMC_TIMING_MMC_HS400)
0868             mode = 0x3;
0869         else
0870             mode = 0x2; /* ddr mode and use divisor */
0871 
0872         if (hz >= (host->src_clk_freq >> 2)) {
0873             div = 0; /* mean div = 1/4 */
0874             sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
0875         } else {
0876             div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
0877             sclk = (host->src_clk_freq >> 2) / div;
0878             div = (div >> 1);
0879         }
0880 
0881         if (timing == MMC_TIMING_MMC_HS400 &&
0882             hz >= (host->src_clk_freq >> 1)) {
0883             if (host->dev_comp->clk_div_bits == 8)
0884                 sdr_set_bits(host->base + MSDC_CFG,
0885                          MSDC_CFG_HS400_CK_MODE);
0886             else
0887                 sdr_set_bits(host->base + MSDC_CFG,
0888                          MSDC_CFG_HS400_CK_MODE_EXTRA);
0889             sclk = host->src_clk_freq >> 1;
0890             div = 0; /* div is ignore when bit18 is set */
0891         }
0892     } else if (hz >= host->src_clk_freq) {
0893         mode = 0x1; /* no divisor */
0894         div = 0;
0895         sclk = host->src_clk_freq;
0896     } else {
0897         mode = 0x0; /* use divisor */
0898         if (hz >= (host->src_clk_freq >> 1)) {
0899             div = 0; /* mean div = 1/2 */
0900             sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
0901         } else {
0902             div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
0903             sclk = (host->src_clk_freq >> 2) / div;
0904         }
0905     }
0906     sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
0907 
0908     clk_disable_unprepare(host->src_clk_cg);
0909     if (host->dev_comp->clk_div_bits == 8)
0910         sdr_set_field(host->base + MSDC_CFG,
0911                   MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
0912                   (mode << 8) | div);
0913     else
0914         sdr_set_field(host->base + MSDC_CFG,
0915                   MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
0916                   (mode << 12) | div);
0917 
0918     clk_prepare_enable(host->src_clk_cg);
0919     readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
0920     sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
0921     mmc->actual_clock = sclk;
0922     host->mclk = hz;
0923     host->timing = timing;
0924     /* need because clk changed. */
0925     msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
0926     sdr_set_bits(host->base + MSDC_INTEN, flags);
0927 
0928     /*
0929      * mmc_select_hs400() will drop to 50Mhz and High speed mode,
0930      * tune result of hs200/200Mhz is not suitable for 50Mhz
0931      */
0932     if (mmc->actual_clock <= 52000000) {
0933         writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
0934         if (host->top_base) {
0935             writel(host->def_tune_para.emmc_top_control,
0936                    host->top_base + EMMC_TOP_CONTROL);
0937             writel(host->def_tune_para.emmc_top_cmd,
0938                    host->top_base + EMMC_TOP_CMD);
0939         } else {
0940             writel(host->def_tune_para.pad_tune,
0941                    host->base + tune_reg);
0942         }
0943     } else {
0944         writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
0945         writel(host->saved_tune_para.pad_cmd_tune,
0946                host->base + PAD_CMD_TUNE);
0947         if (host->top_base) {
0948             writel(host->saved_tune_para.emmc_top_control,
0949                    host->top_base + EMMC_TOP_CONTROL);
0950             writel(host->saved_tune_para.emmc_top_cmd,
0951                    host->top_base + EMMC_TOP_CMD);
0952         } else {
0953             writel(host->saved_tune_para.pad_tune,
0954                    host->base + tune_reg);
0955         }
0956     }
0957 
0958     if (timing == MMC_TIMING_MMC_HS400 &&
0959         host->dev_comp->hs400_tune)
0960         sdr_set_field(host->base + tune_reg,
0961                   MSDC_PAD_TUNE_CMDRRDLY,
0962                   host->hs400_cmd_int_delay);
0963     dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
0964         timing);
0965 }
0966 
0967 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
0968         struct mmc_command *cmd)
0969 {
0970     u32 resp;
0971 
0972     switch (mmc_resp_type(cmd)) {
0973         /* Actually, R1, R5, R6, R7 are the same */
0974     case MMC_RSP_R1:
0975         resp = 0x1;
0976         break;
0977     case MMC_RSP_R1B:
0978         resp = 0x7;
0979         break;
0980     case MMC_RSP_R2:
0981         resp = 0x2;
0982         break;
0983     case MMC_RSP_R3:
0984         resp = 0x3;
0985         break;
0986     case MMC_RSP_NONE:
0987     default:
0988         resp = 0x0;
0989         break;
0990     }
0991 
0992     return resp;
0993 }
0994 
0995 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
0996         struct mmc_request *mrq, struct mmc_command *cmd)
0997 {
0998     struct mmc_host *mmc = mmc_from_priv(host);
0999     /* rawcmd :
1000      * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1001      * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1002      */
1003     u32 opcode = cmd->opcode;
1004     u32 resp = msdc_cmd_find_resp(host, cmd);
1005     u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1006 
1007     host->cmd_rsp = resp;
1008 
1009     if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1010         opcode == MMC_STOP_TRANSMISSION)
1011         rawcmd |= BIT(14);
1012     else if (opcode == SD_SWITCH_VOLTAGE)
1013         rawcmd |= BIT(30);
1014     else if (opcode == SD_APP_SEND_SCR ||
1015          opcode == SD_APP_SEND_NUM_WR_BLKS ||
1016          (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1017          (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1018          (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1019         rawcmd |= BIT(11);
1020 
1021     if (cmd->data) {
1022         struct mmc_data *data = cmd->data;
1023 
1024         if (mmc_op_multi(opcode)) {
1025             if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1026                 !(mrq->sbc->arg & 0xFFFF0000))
1027                 rawcmd |= BIT(29); /* AutoCMD23 */
1028         }
1029 
1030         rawcmd |= ((data->blksz & 0xFFF) << 16);
1031         if (data->flags & MMC_DATA_WRITE)
1032             rawcmd |= BIT(13);
1033         if (data->blocks > 1)
1034             rawcmd |= BIT(12);
1035         else
1036             rawcmd |= BIT(11);
1037         /* Always use dma mode */
1038         sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1039 
1040         if (host->timeout_ns != data->timeout_ns ||
1041             host->timeout_clks != data->timeout_clks)
1042             msdc_set_timeout(host, data->timeout_ns,
1043                     data->timeout_clks);
1044 
1045         writel(data->blocks, host->base + SDC_BLK_NUM);
1046     }
1047     return rawcmd;
1048 }
1049 
1050 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1051         struct mmc_data *data)
1052 {
1053     bool read;
1054 
1055     WARN_ON(host->data);
1056     host->data = data;
1057     read = data->flags & MMC_DATA_READ;
1058 
1059     mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1060     msdc_dma_setup(host, &host->dma, data);
1061     sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1062     sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1063     dev_dbg(host->dev, "DMA start\n");
1064     dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1065             __func__, cmd->opcode, data->blocks, read);
1066 }
1067 
1068 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1069         struct mmc_command *cmd)
1070 {
1071     u32 *rsp = cmd->resp;
1072 
1073     rsp[0] = readl(host->base + SDC_ACMD_RESP);
1074 
1075     if (events & MSDC_INT_ACMDRDY) {
1076         cmd->error = 0;
1077     } else {
1078         msdc_reset_hw(host);
1079         if (events & MSDC_INT_ACMDCRCERR) {
1080             cmd->error = -EILSEQ;
1081             host->error |= REQ_STOP_EIO;
1082         } else if (events & MSDC_INT_ACMDTMO) {
1083             cmd->error = -ETIMEDOUT;
1084             host->error |= REQ_STOP_TMO;
1085         }
1086         dev_err(host->dev,
1087             "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1088             __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1089     }
1090     return cmd->error;
1091 }
1092 
1093 /*
1094  * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1095  *
1096  * Host controller may lost interrupt in some special case.
1097  * Add SDIO irq recheck mechanism to make sure all interrupts
1098  * can be processed immediately
1099  */
1100 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1101 {
1102     struct mmc_host *mmc = mmc_from_priv(host);
1103     u32 reg_int, reg_inten, reg_ps;
1104 
1105     if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1106         reg_inten = readl(host->base + MSDC_INTEN);
1107         if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1108             reg_int = readl(host->base + MSDC_INT);
1109             reg_ps = readl(host->base + MSDC_PS);
1110             if (!(reg_int & MSDC_INT_SDIOIRQ ||
1111                   reg_ps & MSDC_PS_DATA1)) {
1112                 __msdc_enable_sdio_irq(host, 0);
1113                 sdio_signal_irq(mmc);
1114             }
1115         }
1116     }
1117 }
1118 
1119 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1120 {
1121     if (host->error)
1122         dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1123             __func__, cmd->opcode, cmd->arg, host->error);
1124 }
1125 
1126 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1127 {
1128     unsigned long flags;
1129 
1130     /*
1131      * No need check the return value of cancel_delayed_work, as only ONE
1132      * path will go here!
1133      */
1134     cancel_delayed_work(&host->req_timeout);
1135 
1136     spin_lock_irqsave(&host->lock, flags);
1137     host->mrq = NULL;
1138     spin_unlock_irqrestore(&host->lock, flags);
1139 
1140     msdc_track_cmd_data(host, mrq->cmd);
1141     if (mrq->data)
1142         msdc_unprepare_data(host, mrq->data);
1143     if (host->error)
1144         msdc_reset_hw(host);
1145     mmc_request_done(mmc_from_priv(host), mrq);
1146     if (host->dev_comp->recheck_sdio_irq)
1147         msdc_recheck_sdio_irq(host);
1148 }
1149 
1150 /* returns true if command is fully handled; returns false otherwise */
1151 static bool msdc_cmd_done(struct msdc_host *host, int events,
1152               struct mmc_request *mrq, struct mmc_command *cmd)
1153 {
1154     bool done = false;
1155     bool sbc_error;
1156     unsigned long flags;
1157     u32 *rsp;
1158 
1159     if (mrq->sbc && cmd == mrq->cmd &&
1160         (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1161                    | MSDC_INT_ACMDTMO)))
1162         msdc_auto_cmd_done(host, events, mrq->sbc);
1163 
1164     sbc_error = mrq->sbc && mrq->sbc->error;
1165 
1166     if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1167                     | MSDC_INT_RSPCRCERR
1168                     | MSDC_INT_CMDTMO)))
1169         return done;
1170 
1171     spin_lock_irqsave(&host->lock, flags);
1172     done = !host->cmd;
1173     host->cmd = NULL;
1174     spin_unlock_irqrestore(&host->lock, flags);
1175 
1176     if (done)
1177         return true;
1178     rsp = cmd->resp;
1179 
1180     sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1181 
1182     if (cmd->flags & MMC_RSP_PRESENT) {
1183         if (cmd->flags & MMC_RSP_136) {
1184             rsp[0] = readl(host->base + SDC_RESP3);
1185             rsp[1] = readl(host->base + SDC_RESP2);
1186             rsp[2] = readl(host->base + SDC_RESP1);
1187             rsp[3] = readl(host->base + SDC_RESP0);
1188         } else {
1189             rsp[0] = readl(host->base + SDC_RESP0);
1190         }
1191     }
1192 
1193     if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1194         if (events & MSDC_INT_CMDTMO ||
1195             (cmd->opcode != MMC_SEND_TUNING_BLOCK &&
1196              cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 &&
1197              !host->hs400_tuning))
1198             /*
1199              * should not clear fifo/interrupt as the tune data
1200              * may have alreay come when cmd19/cmd21 gets response
1201              * CRC error.
1202              */
1203             msdc_reset_hw(host);
1204         if (events & MSDC_INT_RSPCRCERR) {
1205             cmd->error = -EILSEQ;
1206             host->error |= REQ_CMD_EIO;
1207         } else if (events & MSDC_INT_CMDTMO) {
1208             cmd->error = -ETIMEDOUT;
1209             host->error |= REQ_CMD_TMO;
1210         }
1211     }
1212     if (cmd->error)
1213         dev_dbg(host->dev,
1214                 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1215                 __func__, cmd->opcode, cmd->arg, rsp[0],
1216                 cmd->error);
1217 
1218     msdc_cmd_next(host, mrq, cmd);
1219     return true;
1220 }
1221 
1222 /* It is the core layer's responsibility to ensure card status
1223  * is correct before issue a request. but host design do below
1224  * checks recommended.
1225  */
1226 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1227         struct mmc_request *mrq, struct mmc_command *cmd)
1228 {
1229     u32 val;
1230     int ret;
1231 
1232     /* The max busy time we can endure is 20ms */
1233     ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1234                     !(val & SDC_STS_CMDBUSY), 1, 20000);
1235     if (ret) {
1236         dev_err(host->dev, "CMD bus busy detected\n");
1237         host->error |= REQ_CMD_BUSY;
1238         msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1239         return false;
1240     }
1241 
1242     if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1243         /* R1B or with data, should check SDCBUSY */
1244         ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1245                         !(val & SDC_STS_SDCBUSY), 1, 20000);
1246         if (ret) {
1247             dev_err(host->dev, "Controller busy detected\n");
1248             host->error |= REQ_CMD_BUSY;
1249             msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1250             return false;
1251         }
1252     }
1253     return true;
1254 }
1255 
1256 static void msdc_start_command(struct msdc_host *host,
1257         struct mmc_request *mrq, struct mmc_command *cmd)
1258 {
1259     u32 rawcmd;
1260     unsigned long flags;
1261 
1262     WARN_ON(host->cmd);
1263     host->cmd = cmd;
1264 
1265     mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1266     if (!msdc_cmd_is_ready(host, mrq, cmd))
1267         return;
1268 
1269     if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1270         readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1271         dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1272         msdc_reset_hw(host);
1273     }
1274 
1275     cmd->error = 0;
1276     rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1277 
1278     spin_lock_irqsave(&host->lock, flags);
1279     sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1280     spin_unlock_irqrestore(&host->lock, flags);
1281 
1282     writel(cmd->arg, host->base + SDC_ARG);
1283     writel(rawcmd, host->base + SDC_CMD);
1284 }
1285 
1286 static void msdc_cmd_next(struct msdc_host *host,
1287         struct mmc_request *mrq, struct mmc_command *cmd)
1288 {
1289     if ((cmd->error &&
1290         !(cmd->error == -EILSEQ &&
1291           (cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1292            cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 ||
1293            host->hs400_tuning))) ||
1294         (mrq->sbc && mrq->sbc->error))
1295         msdc_request_done(host, mrq);
1296     else if (cmd == mrq->sbc)
1297         msdc_start_command(host, mrq, mrq->cmd);
1298     else if (!cmd->data)
1299         msdc_request_done(host, mrq);
1300     else
1301         msdc_start_data(host, cmd, cmd->data);
1302 }
1303 
1304 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1305 {
1306     struct msdc_host *host = mmc_priv(mmc);
1307 
1308     host->error = 0;
1309     WARN_ON(host->mrq);
1310     host->mrq = mrq;
1311 
1312     if (mrq->data)
1313         msdc_prepare_data(host, mrq->data);
1314 
1315     /* if SBC is required, we have HW option and SW option.
1316      * if HW option is enabled, and SBC does not have "special" flags,
1317      * use HW option,  otherwise use SW option
1318      */
1319     if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1320         (mrq->sbc->arg & 0xFFFF0000)))
1321         msdc_start_command(host, mrq, mrq->sbc);
1322     else
1323         msdc_start_command(host, mrq, mrq->cmd);
1324 }
1325 
1326 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1327 {
1328     struct msdc_host *host = mmc_priv(mmc);
1329     struct mmc_data *data = mrq->data;
1330 
1331     if (!data)
1332         return;
1333 
1334     msdc_prepare_data(host, data);
1335     data->host_cookie |= MSDC_ASYNC_FLAG;
1336 }
1337 
1338 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1339         int err)
1340 {
1341     struct msdc_host *host = mmc_priv(mmc);
1342     struct mmc_data *data = mrq->data;
1343 
1344     if (!data)
1345         return;
1346 
1347     if (data->host_cookie) {
1348         data->host_cookie &= ~MSDC_ASYNC_FLAG;
1349         msdc_unprepare_data(host, data);
1350     }
1351 }
1352 
1353 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1354 {
1355     if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1356         !mrq->sbc)
1357         msdc_start_command(host, mrq, mrq->stop);
1358     else
1359         msdc_request_done(host, mrq);
1360 }
1361 
1362 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1363                 struct mmc_request *mrq, struct mmc_data *data)
1364 {
1365     struct mmc_command *stop;
1366     unsigned long flags;
1367     bool done;
1368     unsigned int check_data = events &
1369         (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1370          | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1371          | MSDC_INT_DMA_PROTECT);
1372     u32 val;
1373     int ret;
1374 
1375     spin_lock_irqsave(&host->lock, flags);
1376     done = !host->data;
1377     if (check_data)
1378         host->data = NULL;
1379     spin_unlock_irqrestore(&host->lock, flags);
1380 
1381     if (done)
1382         return;
1383     stop = data->stop;
1384 
1385     if (check_data || (stop && stop->error)) {
1386         dev_dbg(host->dev, "DMA status: 0x%8X\n",
1387                 readl(host->base + MSDC_DMA_CFG));
1388         sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1389                 1);
1390 
1391         ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1392                         !(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1393         if (ret)
1394             dev_dbg(host->dev, "DMA stop timed out\n");
1395 
1396         ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1397                         !(val & MSDC_DMA_CFG_STS), 1, 20000);
1398         if (ret)
1399             dev_dbg(host->dev, "DMA inactive timed out\n");
1400 
1401         sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1402         dev_dbg(host->dev, "DMA stop\n");
1403 
1404         if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1405             data->bytes_xfered = data->blocks * data->blksz;
1406         } else {
1407             dev_dbg(host->dev, "interrupt events: %x\n", events);
1408             msdc_reset_hw(host);
1409             host->error |= REQ_DAT_ERR;
1410             data->bytes_xfered = 0;
1411 
1412             if (events & MSDC_INT_DATTMO)
1413                 data->error = -ETIMEDOUT;
1414             else if (events & MSDC_INT_DATCRCERR)
1415                 data->error = -EILSEQ;
1416 
1417             dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1418                 __func__, mrq->cmd->opcode, data->blocks);
1419             dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1420                 (int)data->error, data->bytes_xfered);
1421         }
1422 
1423         msdc_data_xfer_next(host, mrq);
1424     }
1425 }
1426 
1427 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1428 {
1429     u32 val = readl(host->base + SDC_CFG);
1430 
1431     val &= ~SDC_CFG_BUSWIDTH;
1432 
1433     switch (width) {
1434     default:
1435     case MMC_BUS_WIDTH_1:
1436         val |= (MSDC_BUS_1BITS << 16);
1437         break;
1438     case MMC_BUS_WIDTH_4:
1439         val |= (MSDC_BUS_4BITS << 16);
1440         break;
1441     case MMC_BUS_WIDTH_8:
1442         val |= (MSDC_BUS_8BITS << 16);
1443         break;
1444     }
1445 
1446     writel(val, host->base + SDC_CFG);
1447     dev_dbg(host->dev, "Bus Width = %d", width);
1448 }
1449 
1450 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1451 {
1452     struct msdc_host *host = mmc_priv(mmc);
1453     int ret;
1454 
1455     if (!IS_ERR(mmc->supply.vqmmc)) {
1456         if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1457             ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1458             dev_err(host->dev, "Unsupported signal voltage!\n");
1459             return -EINVAL;
1460         }
1461 
1462         ret = mmc_regulator_set_vqmmc(mmc, ios);
1463         if (ret < 0) {
1464             dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1465                 ret, ios->signal_voltage);
1466             return ret;
1467         }
1468 
1469         /* Apply different pinctrl settings for different signal voltage */
1470         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1471             pinctrl_select_state(host->pinctrl, host->pins_uhs);
1472         else
1473             pinctrl_select_state(host->pinctrl, host->pins_default);
1474     }
1475     return 0;
1476 }
1477 
1478 static int msdc_card_busy(struct mmc_host *mmc)
1479 {
1480     struct msdc_host *host = mmc_priv(mmc);
1481     u32 status = readl(host->base + MSDC_PS);
1482 
1483     /* only check if data0 is low */
1484     return !(status & BIT(16));
1485 }
1486 
1487 static void msdc_request_timeout(struct work_struct *work)
1488 {
1489     struct msdc_host *host = container_of(work, struct msdc_host,
1490             req_timeout.work);
1491 
1492     /* simulate HW timeout status */
1493     dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1494     if (host->mrq) {
1495         dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1496                 host->mrq, host->mrq->cmd->opcode);
1497         if (host->cmd) {
1498             dev_err(host->dev, "%s: aborting cmd=%d\n",
1499                     __func__, host->cmd->opcode);
1500             msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1501                     host->cmd);
1502         } else if (host->data) {
1503             dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1504                     __func__, host->mrq->cmd->opcode,
1505                     host->data->blocks);
1506             msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1507                     host->data);
1508         }
1509     }
1510 }
1511 
1512 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1513 {
1514     if (enb) {
1515         sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1516         sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1517         if (host->dev_comp->recheck_sdio_irq)
1518             msdc_recheck_sdio_irq(host);
1519     } else {
1520         sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1521         sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1522     }
1523 }
1524 
1525 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1526 {
1527     struct msdc_host *host = mmc_priv(mmc);
1528     unsigned long flags;
1529     int ret;
1530 
1531     spin_lock_irqsave(&host->lock, flags);
1532     __msdc_enable_sdio_irq(host, enb);
1533     spin_unlock_irqrestore(&host->lock, flags);
1534 
1535     if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1536         if (enb) {
1537             /*
1538              * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to
1539              * GPIO mode. We need to restore it to SDIO DAT1 mode after that.
1540              * Since the current pinstate is pins_uhs, to ensure pinctrl select take
1541              * affect successfully, we change the pinstate to pins_eint firstly.
1542              */
1543             pinctrl_select_state(host->pinctrl, host->pins_eint);
1544             ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1545 
1546             if (ret) {
1547                 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1548                 host->pins_eint = NULL;
1549                 pm_runtime_get_noresume(host->dev);
1550             } else {
1551                 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1552             }
1553 
1554             pinctrl_select_state(host->pinctrl, host->pins_uhs);
1555         } else {
1556             dev_pm_clear_wake_irq(host->dev);
1557         }
1558     } else {
1559         if (enb) {
1560             /* Ensure host->pins_eint is NULL */
1561             host->pins_eint = NULL;
1562             pm_runtime_get_noresume(host->dev);
1563         } else {
1564             pm_runtime_put_noidle(host->dev);
1565         }
1566     }
1567 }
1568 
1569 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1570 {
1571     struct mmc_host *mmc = mmc_from_priv(host);
1572     int cmd_err = 0, dat_err = 0;
1573 
1574     if (intsts & MSDC_INT_RSPCRCERR) {
1575         cmd_err = -EILSEQ;
1576         dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1577     } else if (intsts & MSDC_INT_CMDTMO) {
1578         cmd_err = -ETIMEDOUT;
1579         dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1580     }
1581 
1582     if (intsts & MSDC_INT_DATCRCERR) {
1583         dat_err = -EILSEQ;
1584         dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1585     } else if (intsts & MSDC_INT_DATTMO) {
1586         dat_err = -ETIMEDOUT;
1587         dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1588     }
1589 
1590     if (cmd_err || dat_err) {
1591         dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
1592             cmd_err, dat_err, intsts);
1593     }
1594 
1595     return cqhci_irq(mmc, 0, cmd_err, dat_err);
1596 }
1597 
1598 static irqreturn_t msdc_irq(int irq, void *dev_id)
1599 {
1600     struct msdc_host *host = (struct msdc_host *) dev_id;
1601     struct mmc_host *mmc = mmc_from_priv(host);
1602 
1603     while (true) {
1604         struct mmc_request *mrq;
1605         struct mmc_command *cmd;
1606         struct mmc_data *data;
1607         u32 events, event_mask;
1608 
1609         spin_lock(&host->lock);
1610         events = readl(host->base + MSDC_INT);
1611         event_mask = readl(host->base + MSDC_INTEN);
1612         if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1613             __msdc_enable_sdio_irq(host, 0);
1614         /* clear interrupts */
1615         writel(events & event_mask, host->base + MSDC_INT);
1616 
1617         mrq = host->mrq;
1618         cmd = host->cmd;
1619         data = host->data;
1620         spin_unlock(&host->lock);
1621 
1622         if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1623             sdio_signal_irq(mmc);
1624 
1625         if ((events & event_mask) & MSDC_INT_CDSC) {
1626             if (host->internal_cd)
1627                 mmc_detect_change(mmc, msecs_to_jiffies(20));
1628             events &= ~MSDC_INT_CDSC;
1629         }
1630 
1631         if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1632             break;
1633 
1634         if ((mmc->caps2 & MMC_CAP2_CQE) &&
1635             (events & MSDC_INT_CMDQ)) {
1636             msdc_cmdq_irq(host, events);
1637             /* clear interrupts */
1638             writel(events, host->base + MSDC_INT);
1639             return IRQ_HANDLED;
1640         }
1641 
1642         if (!mrq) {
1643             dev_err(host->dev,
1644                 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1645                 __func__, events, event_mask);
1646             WARN_ON(1);
1647             break;
1648         }
1649 
1650         dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1651 
1652         if (cmd)
1653             msdc_cmd_done(host, events, mrq, cmd);
1654         else if (data)
1655             msdc_data_xfer_done(host, events, mrq, data);
1656     }
1657 
1658     return IRQ_HANDLED;
1659 }
1660 
1661 static void msdc_init_hw(struct msdc_host *host)
1662 {
1663     u32 val;
1664     u32 tune_reg = host->dev_comp->pad_tune_reg;
1665     struct mmc_host *mmc = mmc_from_priv(host);
1666 
1667     if (host->reset) {
1668         reset_control_assert(host->reset);
1669         usleep_range(10, 50);
1670         reset_control_deassert(host->reset);
1671     }
1672 
1673     /* Configure to MMC/SD mode, clock free running */
1674     sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1675 
1676     /* Reset */
1677     msdc_reset_hw(host);
1678 
1679     /* Disable and clear all interrupts */
1680     writel(0, host->base + MSDC_INTEN);
1681     val = readl(host->base + MSDC_INT);
1682     writel(val, host->base + MSDC_INT);
1683 
1684     /* Configure card detection */
1685     if (host->internal_cd) {
1686         sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1687                   DEFAULT_DEBOUNCE);
1688         sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1689         sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1690         sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1691     } else {
1692         sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1693         sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1694         sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1695     }
1696 
1697     if (host->top_base) {
1698         writel(0, host->top_base + EMMC_TOP_CONTROL);
1699         writel(0, host->top_base + EMMC_TOP_CMD);
1700     } else {
1701         writel(0, host->base + tune_reg);
1702     }
1703     writel(0, host->base + MSDC_IOCON);
1704     sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1705     writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1706     sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1707     writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1708     sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1709 
1710     if (host->dev_comp->stop_clk_fix) {
1711         sdr_set_field(host->base + MSDC_PATCH_BIT1,
1712                   MSDC_PATCH_BIT1_STOP_DLY, 3);
1713         sdr_clr_bits(host->base + SDC_FIFO_CFG,
1714                  SDC_FIFO_CFG_WRVALIDSEL);
1715         sdr_clr_bits(host->base + SDC_FIFO_CFG,
1716                  SDC_FIFO_CFG_RDVALIDSEL);
1717     }
1718 
1719     if (host->dev_comp->busy_check)
1720         sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));
1721 
1722     if (host->dev_comp->async_fifo) {
1723         sdr_set_field(host->base + MSDC_PATCH_BIT2,
1724                   MSDC_PB2_RESPWAIT, 3);
1725         if (host->dev_comp->enhance_rx) {
1726             if (host->top_base)
1727                 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1728                          SDC_RX_ENH_EN);
1729             else
1730                 sdr_set_bits(host->base + SDC_ADV_CFG0,
1731                          SDC_RX_ENHANCE_EN);
1732         } else {
1733             sdr_set_field(host->base + MSDC_PATCH_BIT2,
1734                       MSDC_PB2_RESPSTSENSEL, 2);
1735             sdr_set_field(host->base + MSDC_PATCH_BIT2,
1736                       MSDC_PB2_CRCSTSENSEL, 2);
1737         }
1738         /* use async fifo, then no need tune internal delay */
1739         sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1740                  MSDC_PATCH_BIT2_CFGRESP);
1741         sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1742                  MSDC_PATCH_BIT2_CFGCRCSTS);
1743     }
1744 
1745     if (host->dev_comp->support_64g)
1746         sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1747                  MSDC_PB2_SUPPORT_64G);
1748     if (host->dev_comp->data_tune) {
1749         if (host->top_base) {
1750             sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1751                      PAD_DAT_RD_RXDLY_SEL);
1752             sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1753                      DATA_K_VALUE_SEL);
1754             sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1755                      PAD_CMD_RD_RXDLY_SEL);
1756         } else {
1757             sdr_set_bits(host->base + tune_reg,
1758                      MSDC_PAD_TUNE_RD_SEL |
1759                      MSDC_PAD_TUNE_CMD_SEL);
1760         }
1761     } else {
1762         /* choose clock tune */
1763         if (host->top_base)
1764             sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1765                      PAD_RXDLY_SEL);
1766         else
1767             sdr_set_bits(host->base + tune_reg,
1768                      MSDC_PAD_TUNE_RXDLYSEL);
1769     }
1770 
1771     if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
1772         sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1773         sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1774         sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1775     } else {
1776         /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */
1777         sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1778 
1779         /* Config SDIO device detect interrupt function */
1780         sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1781         sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1782     }
1783 
1784     /* Configure to default data timeout */
1785     sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1786 
1787     host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1788     host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1789     if (host->top_base) {
1790         host->def_tune_para.emmc_top_control =
1791             readl(host->top_base + EMMC_TOP_CONTROL);
1792         host->def_tune_para.emmc_top_cmd =
1793             readl(host->top_base + EMMC_TOP_CMD);
1794         host->saved_tune_para.emmc_top_control =
1795             readl(host->top_base + EMMC_TOP_CONTROL);
1796         host->saved_tune_para.emmc_top_cmd =
1797             readl(host->top_base + EMMC_TOP_CMD);
1798     } else {
1799         host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1800         host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1801     }
1802     dev_dbg(host->dev, "init hardware done!");
1803 }
1804 
1805 static void msdc_deinit_hw(struct msdc_host *host)
1806 {
1807     u32 val;
1808 
1809     if (host->internal_cd) {
1810         /* Disabled card-detect */
1811         sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1812         sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1813     }
1814 
1815     /* Disable and clear all interrupts */
1816     writel(0, host->base + MSDC_INTEN);
1817 
1818     val = readl(host->base + MSDC_INT);
1819     writel(val, host->base + MSDC_INT);
1820 }
1821 
1822 /* init gpd and bd list in msdc_drv_probe */
1823 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1824 {
1825     struct mt_gpdma_desc *gpd = dma->gpd;
1826     struct mt_bdma_desc *bd = dma->bd;
1827     dma_addr_t dma_addr;
1828     int i;
1829 
1830     memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1831 
1832     dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1833     gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1834     /* gpd->next is must set for desc DMA
1835      * That's why must alloc 2 gpd structure.
1836      */
1837     gpd->next = lower_32_bits(dma_addr);
1838     if (host->dev_comp->support_64g)
1839         gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1840 
1841     dma_addr = dma->bd_addr;
1842     gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1843     if (host->dev_comp->support_64g)
1844         gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1845 
1846     memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1847     for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1848         dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1849         bd[i].next = lower_32_bits(dma_addr);
1850         if (host->dev_comp->support_64g)
1851             bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1852     }
1853 }
1854 
1855 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1856 {
1857     struct msdc_host *host = mmc_priv(mmc);
1858     int ret;
1859 
1860     msdc_set_buswidth(host, ios->bus_width);
1861 
1862     /* Suspend/Resume will do power off/on */
1863     switch (ios->power_mode) {
1864     case MMC_POWER_UP:
1865         if (!IS_ERR(mmc->supply.vmmc)) {
1866             msdc_init_hw(host);
1867             ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1868                     ios->vdd);
1869             if (ret) {
1870                 dev_err(host->dev, "Failed to set vmmc power!\n");
1871                 return;
1872             }
1873         }
1874         break;
1875     case MMC_POWER_ON:
1876         if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1877             ret = regulator_enable(mmc->supply.vqmmc);
1878             if (ret)
1879                 dev_err(host->dev, "Failed to set vqmmc power!\n");
1880             else
1881                 host->vqmmc_enabled = true;
1882         }
1883         break;
1884     case MMC_POWER_OFF:
1885         if (!IS_ERR(mmc->supply.vmmc))
1886             mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1887 
1888         if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1889             regulator_disable(mmc->supply.vqmmc);
1890             host->vqmmc_enabled = false;
1891         }
1892         break;
1893     default:
1894         break;
1895     }
1896 
1897     if (host->mclk != ios->clock || host->timing != ios->timing)
1898         msdc_set_mclk(host, ios->timing, ios->clock);
1899 }
1900 
1901 static u32 test_delay_bit(u32 delay, u32 bit)
1902 {
1903     bit %= PAD_DELAY_MAX;
1904     return delay & BIT(bit);
1905 }
1906 
1907 static int get_delay_len(u32 delay, u32 start_bit)
1908 {
1909     int i;
1910 
1911     for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1912         if (test_delay_bit(delay, start_bit + i) == 0)
1913             return i;
1914     }
1915     return PAD_DELAY_MAX - start_bit;
1916 }
1917 
1918 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1919 {
1920     int start = 0, len = 0;
1921     int start_final = 0, len_final = 0;
1922     u8 final_phase = 0xff;
1923     struct msdc_delay_phase delay_phase = { 0, };
1924 
1925     if (delay == 0) {
1926         dev_err(host->dev, "phase error: [map:%x]\n", delay);
1927         delay_phase.final_phase = final_phase;
1928         return delay_phase;
1929     }
1930 
1931     while (start < PAD_DELAY_MAX) {
1932         len = get_delay_len(delay, start);
1933         if (len_final < len) {
1934             start_final = start;
1935             len_final = len;
1936         }
1937         start += len ? len : 1;
1938         if (len >= 12 && start_final < 4)
1939             break;
1940     }
1941 
1942     /* The rule is that to find the smallest delay cell */
1943     if (start_final == 0)
1944         final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1945     else
1946         final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1947     dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1948         delay, len_final, final_phase);
1949 
1950     delay_phase.maxlen = len_final;
1951     delay_phase.start = start_final;
1952     delay_phase.final_phase = final_phase;
1953     return delay_phase;
1954 }
1955 
1956 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
1957 {
1958     u32 tune_reg = host->dev_comp->pad_tune_reg;
1959 
1960     if (host->top_base)
1961         sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
1962                   value);
1963     else
1964         sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
1965                   value);
1966 }
1967 
1968 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
1969 {
1970     u32 tune_reg = host->dev_comp->pad_tune_reg;
1971 
1972     if (host->top_base)
1973         sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
1974                   PAD_DAT_RD_RXDLY, value);
1975     else
1976         sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
1977                   value);
1978 }
1979 
1980 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
1981 {
1982     struct msdc_host *host = mmc_priv(mmc);
1983     u32 rise_delay = 0, fall_delay = 0;
1984     struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
1985     struct msdc_delay_phase internal_delay_phase;
1986     u8 final_delay, final_maxlen;
1987     u32 internal_delay = 0;
1988     u32 tune_reg = host->dev_comp->pad_tune_reg;
1989     int cmd_err;
1990     int i, j;
1991 
1992     if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
1993         mmc->ios.timing == MMC_TIMING_UHS_SDR104)
1994         sdr_set_field(host->base + tune_reg,
1995                   MSDC_PAD_TUNE_CMDRRDLY,
1996                   host->hs200_cmd_int_delay);
1997 
1998     sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
1999     for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2000         msdc_set_cmd_delay(host, i);
2001         /*
2002          * Using the same parameters, it may sometimes pass the test,
2003          * but sometimes it may fail. To make sure the parameters are
2004          * more stable, we test each set of parameters 3 times.
2005          */
2006         for (j = 0; j < 3; j++) {
2007             mmc_send_tuning(mmc, opcode, &cmd_err);
2008             if (!cmd_err) {
2009                 rise_delay |= BIT(i);
2010             } else {
2011                 rise_delay &= ~BIT(i);
2012                 break;
2013             }
2014         }
2015     }
2016     final_rise_delay = get_best_delay(host, rise_delay);
2017     /* if rising edge has enough margin, then do not scan falling edge */
2018     if (final_rise_delay.maxlen >= 12 ||
2019         (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2020         goto skip_fall;
2021 
2022     sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2023     for (i = 0; i < PAD_DELAY_MAX; i++) {
2024         msdc_set_cmd_delay(host, i);
2025         /*
2026          * Using the same parameters, it may sometimes pass the test,
2027          * but sometimes it may fail. To make sure the parameters are
2028          * more stable, we test each set of parameters 3 times.
2029          */
2030         for (j = 0; j < 3; j++) {
2031             mmc_send_tuning(mmc, opcode, &cmd_err);
2032             if (!cmd_err) {
2033                 fall_delay |= BIT(i);
2034             } else {
2035                 fall_delay &= ~BIT(i);
2036                 break;
2037             }
2038         }
2039     }
2040     final_fall_delay = get_best_delay(host, fall_delay);
2041 
2042 skip_fall:
2043     final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2044     if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2045         final_maxlen = final_fall_delay.maxlen;
2046     if (final_maxlen == final_rise_delay.maxlen) {
2047         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2048         final_delay = final_rise_delay.final_phase;
2049     } else {
2050         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2051         final_delay = final_fall_delay.final_phase;
2052     }
2053     msdc_set_cmd_delay(host, final_delay);
2054 
2055     if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2056         goto skip_internal;
2057 
2058     for (i = 0; i < PAD_DELAY_MAX; i++) {
2059         sdr_set_field(host->base + tune_reg,
2060                   MSDC_PAD_TUNE_CMDRRDLY, i);
2061         mmc_send_tuning(mmc, opcode, &cmd_err);
2062         if (!cmd_err)
2063             internal_delay |= BIT(i);
2064     }
2065     dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2066     internal_delay_phase = get_best_delay(host, internal_delay);
2067     sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2068               internal_delay_phase.final_phase);
2069 skip_internal:
2070     dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2071     return final_delay == 0xff ? -EIO : 0;
2072 }
2073 
2074 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2075 {
2076     struct msdc_host *host = mmc_priv(mmc);
2077     u32 cmd_delay = 0;
2078     struct msdc_delay_phase final_cmd_delay = { 0,};
2079     u8 final_delay;
2080     int cmd_err;
2081     int i, j;
2082 
2083     /* select EMMC50 PAD CMD tune */
2084     sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2085     sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2086 
2087     if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2088         mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2089         sdr_set_field(host->base + MSDC_PAD_TUNE,
2090                   MSDC_PAD_TUNE_CMDRRDLY,
2091                   host->hs200_cmd_int_delay);
2092 
2093     if (host->hs400_cmd_resp_sel_rising)
2094         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2095     else
2096         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2097     for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2098         sdr_set_field(host->base + PAD_CMD_TUNE,
2099                   PAD_CMD_TUNE_RX_DLY3, i);
2100         /*
2101          * Using the same parameters, it may sometimes pass the test,
2102          * but sometimes it may fail. To make sure the parameters are
2103          * more stable, we test each set of parameters 3 times.
2104          */
2105         for (j = 0; j < 3; j++) {
2106             mmc_send_tuning(mmc, opcode, &cmd_err);
2107             if (!cmd_err) {
2108                 cmd_delay |= BIT(i);
2109             } else {
2110                 cmd_delay &= ~BIT(i);
2111                 break;
2112             }
2113         }
2114     }
2115     final_cmd_delay = get_best_delay(host, cmd_delay);
2116     sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2117               final_cmd_delay.final_phase);
2118     final_delay = final_cmd_delay.final_phase;
2119 
2120     dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2121     return final_delay == 0xff ? -EIO : 0;
2122 }
2123 
2124 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2125 {
2126     struct msdc_host *host = mmc_priv(mmc);
2127     u32 rise_delay = 0, fall_delay = 0;
2128     struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2129     u8 final_delay, final_maxlen;
2130     int i, ret;
2131 
2132     sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2133               host->latch_ck);
2134     sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2135     sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2136     for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2137         msdc_set_data_delay(host, i);
2138         ret = mmc_send_tuning(mmc, opcode, NULL);
2139         if (!ret)
2140             rise_delay |= BIT(i);
2141     }
2142     final_rise_delay = get_best_delay(host, rise_delay);
2143     /* if rising edge has enough margin, then do not scan falling edge */
2144     if (final_rise_delay.maxlen >= 12 ||
2145         (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2146         goto skip_fall;
2147 
2148     sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2149     sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2150     for (i = 0; i < PAD_DELAY_MAX; i++) {
2151         msdc_set_data_delay(host, i);
2152         ret = mmc_send_tuning(mmc, opcode, NULL);
2153         if (!ret)
2154             fall_delay |= BIT(i);
2155     }
2156     final_fall_delay = get_best_delay(host, fall_delay);
2157 
2158 skip_fall:
2159     final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2160     if (final_maxlen == final_rise_delay.maxlen) {
2161         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2162         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2163         final_delay = final_rise_delay.final_phase;
2164     } else {
2165         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2166         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2167         final_delay = final_fall_delay.final_phase;
2168     }
2169     msdc_set_data_delay(host, final_delay);
2170 
2171     dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2172     return final_delay == 0xff ? -EIO : 0;
2173 }
2174 
2175 /*
2176  * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2177  * together, which can save the tuning time.
2178  */
2179 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2180 {
2181     struct msdc_host *host = mmc_priv(mmc);
2182     u32 rise_delay = 0, fall_delay = 0;
2183     struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2184     u8 final_delay, final_maxlen;
2185     int i, ret;
2186 
2187     sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2188               host->latch_ck);
2189 
2190     sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2191     sdr_clr_bits(host->base + MSDC_IOCON,
2192              MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2193     for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2194         msdc_set_cmd_delay(host, i);
2195         msdc_set_data_delay(host, i);
2196         ret = mmc_send_tuning(mmc, opcode, NULL);
2197         if (!ret)
2198             rise_delay |= BIT(i);
2199     }
2200     final_rise_delay = get_best_delay(host, rise_delay);
2201     /* if rising edge has enough margin, then do not scan falling edge */
2202     if (final_rise_delay.maxlen >= 12 ||
2203         (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2204         goto skip_fall;
2205 
2206     sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2207     sdr_set_bits(host->base + MSDC_IOCON,
2208              MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2209     for (i = 0; i < PAD_DELAY_MAX; i++) {
2210         msdc_set_cmd_delay(host, i);
2211         msdc_set_data_delay(host, i);
2212         ret = mmc_send_tuning(mmc, opcode, NULL);
2213         if (!ret)
2214             fall_delay |= BIT(i);
2215     }
2216     final_fall_delay = get_best_delay(host, fall_delay);
2217 
2218 skip_fall:
2219     final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2220     if (final_maxlen == final_rise_delay.maxlen) {
2221         sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2222         sdr_clr_bits(host->base + MSDC_IOCON,
2223                  MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2224         final_delay = final_rise_delay.final_phase;
2225     } else {
2226         sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2227         sdr_set_bits(host->base + MSDC_IOCON,
2228                  MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2229         final_delay = final_fall_delay.final_phase;
2230     }
2231 
2232     msdc_set_cmd_delay(host, final_delay);
2233     msdc_set_data_delay(host, final_delay);
2234 
2235     dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2236     return final_delay == 0xff ? -EIO : 0;
2237 }
2238 
2239 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2240 {
2241     struct msdc_host *host = mmc_priv(mmc);
2242     int ret;
2243     u32 tune_reg = host->dev_comp->pad_tune_reg;
2244 
2245     if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2246         ret = msdc_tune_together(mmc, opcode);
2247         if (host->hs400_mode) {
2248             sdr_clr_bits(host->base + MSDC_IOCON,
2249                      MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2250             msdc_set_data_delay(host, 0);
2251         }
2252         goto tune_done;
2253     }
2254     if (host->hs400_mode &&
2255         host->dev_comp->hs400_tune)
2256         ret = hs400_tune_response(mmc, opcode);
2257     else
2258         ret = msdc_tune_response(mmc, opcode);
2259     if (ret == -EIO) {
2260         dev_err(host->dev, "Tune response fail!\n");
2261         return ret;
2262     }
2263     if (host->hs400_mode == false) {
2264         ret = msdc_tune_data(mmc, opcode);
2265         if (ret == -EIO)
2266             dev_err(host->dev, "Tune data fail!\n");
2267     }
2268 
2269 tune_done:
2270     host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2271     host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2272     host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2273     if (host->top_base) {
2274         host->saved_tune_para.emmc_top_control = readl(host->top_base +
2275                 EMMC_TOP_CONTROL);
2276         host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2277                 EMMC_TOP_CMD);
2278     }
2279     return ret;
2280 }
2281 
2282 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2283 {
2284     struct msdc_host *host = mmc_priv(mmc);
2285     host->hs400_mode = true;
2286 
2287     if (host->top_base)
2288         writel(host->hs400_ds_delay,
2289                host->top_base + EMMC50_PAD_DS_TUNE);
2290     else
2291         writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2292     /* hs400 mode must set it to 0 */
2293     sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2294     /* to improve read performance, set outstanding to 2 */
2295     sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2296 
2297     return 0;
2298 }
2299 
2300 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2301 {
2302     struct msdc_host *host = mmc_priv(mmc);
2303     struct msdc_delay_phase dly1_delay;
2304     u32 val, result_dly1 = 0;
2305     u8 *ext_csd;
2306     int i, ret;
2307 
2308     if (host->top_base) {
2309         sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2310                  PAD_DS_DLY_SEL);
2311         if (host->hs400_ds_dly3)
2312             sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2313                       PAD_DS_DLY3, host->hs400_ds_dly3);
2314     } else {
2315         sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2316         if (host->hs400_ds_dly3)
2317             sdr_set_field(host->base + PAD_DS_TUNE,
2318                       PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2319     }
2320 
2321     host->hs400_tuning = true;
2322     for (i = 0; i < PAD_DELAY_MAX; i++) {
2323         if (host->top_base)
2324             sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2325                       PAD_DS_DLY1, i);
2326         else
2327             sdr_set_field(host->base + PAD_DS_TUNE,
2328                       PAD_DS_TUNE_DLY1, i);
2329         ret = mmc_get_ext_csd(card, &ext_csd);
2330         if (!ret) {
2331             result_dly1 |= BIT(i);
2332             kfree(ext_csd);
2333         }
2334     }
2335     host->hs400_tuning = false;
2336 
2337     dly1_delay = get_best_delay(host, result_dly1);
2338     if (dly1_delay.maxlen == 0) {
2339         dev_err(host->dev, "Failed to get DLY1 delay!\n");
2340         goto fail;
2341     }
2342     if (host->top_base)
2343         sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2344                   PAD_DS_DLY1, dly1_delay.final_phase);
2345     else
2346         sdr_set_field(host->base + PAD_DS_TUNE,
2347                   PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2348 
2349     if (host->top_base)
2350         val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2351     else
2352         val = readl(host->base + PAD_DS_TUNE);
2353 
2354     dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2355 
2356     return 0;
2357 
2358 fail:
2359     dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2360     return -EIO;
2361 }
2362 
2363 static void msdc_hw_reset(struct mmc_host *mmc)
2364 {
2365     struct msdc_host *host = mmc_priv(mmc);
2366 
2367     sdr_set_bits(host->base + EMMC_IOCON, 1);
2368     udelay(10); /* 10us is enough */
2369     sdr_clr_bits(host->base + EMMC_IOCON, 1);
2370 }
2371 
2372 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2373 {
2374     unsigned long flags;
2375     struct msdc_host *host = mmc_priv(mmc);
2376 
2377     spin_lock_irqsave(&host->lock, flags);
2378     __msdc_enable_sdio_irq(host, 1);
2379     spin_unlock_irqrestore(&host->lock, flags);
2380 }
2381 
2382 static int msdc_get_cd(struct mmc_host *mmc)
2383 {
2384     struct msdc_host *host = mmc_priv(mmc);
2385     int val;
2386 
2387     if (mmc->caps & MMC_CAP_NONREMOVABLE)
2388         return 1;
2389 
2390     if (!host->internal_cd)
2391         return mmc_gpio_get_cd(mmc);
2392 
2393     val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2394     if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2395         return !!val;
2396     else
2397         return !val;
2398 }
2399 
2400 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2401                        struct mmc_ios *ios)
2402 {
2403     struct msdc_host *host = mmc_priv(mmc);
2404 
2405     if (ios->enhanced_strobe) {
2406         msdc_prepare_hs400_tuning(mmc, ios);
2407         sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2408         sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2409         sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2410 
2411         sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2412         sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2413         sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2414     } else {
2415         sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2416         sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2417         sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2418 
2419         sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2420         sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2421         sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2422     }
2423 }
2424 
2425 static void msdc_cqe_enable(struct mmc_host *mmc)
2426 {
2427     struct msdc_host *host = mmc_priv(mmc);
2428 
2429     /* enable cmdq irq */
2430     writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2431     /* enable busy check */
2432     sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2433     /* default write data / busy timeout 20s */
2434     msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2435     /* default read data timeout 1s */
2436     msdc_set_timeout(host, 1000000000ULL, 0);
2437 }
2438 
2439 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2440 {
2441     struct msdc_host *host = mmc_priv(mmc);
2442     unsigned int val = 0;
2443 
2444     /* disable cmdq irq */
2445     sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2446     /* disable busy check */
2447     sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2448 
2449     val = readl(host->base + MSDC_INT);
2450     writel(val, host->base + MSDC_INT);
2451 
2452     if (recovery) {
2453         sdr_set_field(host->base + MSDC_DMA_CTRL,
2454                   MSDC_DMA_CTRL_STOP, 1);
2455         if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2456             !(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2457             return;
2458         if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2459             !(val & MSDC_DMA_CFG_STS), 1, 3000)))
2460             return;
2461         msdc_reset_hw(host);
2462     }
2463 }
2464 
2465 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2466 {
2467     struct cqhci_host *cq_host = mmc->cqe_private;
2468     u32 reg;
2469 
2470     reg = cqhci_readl(cq_host, CQHCI_CFG);
2471     reg |= CQHCI_ENABLE;
2472     cqhci_writel(cq_host, reg, CQHCI_CFG);
2473 }
2474 
2475 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2476 {
2477     struct cqhci_host *cq_host = mmc->cqe_private;
2478     u32 reg;
2479 
2480     reg = cqhci_readl(cq_host, CQHCI_CFG);
2481     reg &= ~CQHCI_ENABLE;
2482     cqhci_writel(cq_host, reg, CQHCI_CFG);
2483 }
2484 
2485 static const struct mmc_host_ops mt_msdc_ops = {
2486     .post_req = msdc_post_req,
2487     .pre_req = msdc_pre_req,
2488     .request = msdc_ops_request,
2489     .set_ios = msdc_ops_set_ios,
2490     .get_ro = mmc_gpio_get_ro,
2491     .get_cd = msdc_get_cd,
2492     .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2493     .enable_sdio_irq = msdc_enable_sdio_irq,
2494     .ack_sdio_irq = msdc_ack_sdio_irq,
2495     .start_signal_voltage_switch = msdc_ops_switch_volt,
2496     .card_busy = msdc_card_busy,
2497     .execute_tuning = msdc_execute_tuning,
2498     .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2499     .execute_hs400_tuning = msdc_execute_hs400_tuning,
2500     .card_hw_reset = msdc_hw_reset,
2501 };
2502 
2503 static const struct cqhci_host_ops msdc_cmdq_ops = {
2504     .enable         = msdc_cqe_enable,
2505     .disable        = msdc_cqe_disable,
2506     .pre_enable = msdc_cqe_pre_enable,
2507     .post_disable = msdc_cqe_post_disable,
2508 };
2509 
2510 static void msdc_of_property_parse(struct platform_device *pdev,
2511                    struct msdc_host *host)
2512 {
2513     of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2514                  &host->latch_ck);
2515 
2516     of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2517                  &host->hs400_ds_delay);
2518 
2519     of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2520                  &host->hs400_ds_dly3);
2521 
2522     of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2523                  &host->hs200_cmd_int_delay);
2524 
2525     of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2526                  &host->hs400_cmd_int_delay);
2527 
2528     if (of_property_read_bool(pdev->dev.of_node,
2529                   "mediatek,hs400-cmd-resp-sel-rising"))
2530         host->hs400_cmd_resp_sel_rising = true;
2531     else
2532         host->hs400_cmd_resp_sel_rising = false;
2533 
2534     if (of_property_read_bool(pdev->dev.of_node,
2535                   "supports-cqe"))
2536         host->cqhci = true;
2537     else
2538         host->cqhci = false;
2539 }
2540 
2541 static int msdc_of_clock_parse(struct platform_device *pdev,
2542                    struct msdc_host *host)
2543 {
2544     int ret;
2545 
2546     host->src_clk = devm_clk_get(&pdev->dev, "source");
2547     if (IS_ERR(host->src_clk))
2548         return PTR_ERR(host->src_clk);
2549 
2550     host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2551     if (IS_ERR(host->h_clk))
2552         return PTR_ERR(host->h_clk);
2553 
2554     host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2555     if (IS_ERR(host->bus_clk))
2556         host->bus_clk = NULL;
2557 
2558     /*source clock control gate is optional clock*/
2559     host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2560     if (IS_ERR(host->src_clk_cg))
2561         return PTR_ERR(host->src_clk_cg);
2562 
2563     /*
2564      * Fallback for legacy device-trees: src_clk and HCLK use the same
2565      * bit to control gating but they are parented to a different mux,
2566      * hence if our intention is to gate only the source, required
2567      * during a clk mode switch to avoid hw hangs, we need to gate
2568      * its parent (specified as a different clock only on new DTs).
2569      */
2570     if (!host->src_clk_cg) {
2571         host->src_clk_cg = clk_get_parent(host->src_clk);
2572         if (IS_ERR(host->src_clk_cg))
2573             return PTR_ERR(host->src_clk_cg);
2574     }
2575 
2576     host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg");
2577     if (IS_ERR(host->sys_clk_cg))
2578         host->sys_clk_cg = NULL;
2579 
2580     /* If present, always enable for this clock gate */
2581     clk_prepare_enable(host->sys_clk_cg);
2582 
2583     host->bulk_clks[0].id = "pclk_cg";
2584     host->bulk_clks[1].id = "axi_cg";
2585     host->bulk_clks[2].id = "ahb_cg";
2586     ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2587                      host->bulk_clks);
2588     if (ret) {
2589         dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2590         return ret;
2591     }
2592 
2593     return 0;
2594 }
2595 
2596 static int msdc_drv_probe(struct platform_device *pdev)
2597 {
2598     struct mmc_host *mmc;
2599     struct msdc_host *host;
2600     struct resource *res;
2601     int ret;
2602 
2603     if (!pdev->dev.of_node) {
2604         dev_err(&pdev->dev, "No DT found\n");
2605         return -EINVAL;
2606     }
2607 
2608     /* Allocate MMC host for this device */
2609     mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2610     if (!mmc)
2611         return -ENOMEM;
2612 
2613     host = mmc_priv(mmc);
2614     ret = mmc_of_parse(mmc);
2615     if (ret)
2616         goto host_free;
2617 
2618     host->base = devm_platform_ioremap_resource(pdev, 0);
2619     if (IS_ERR(host->base)) {
2620         ret = PTR_ERR(host->base);
2621         goto host_free;
2622     }
2623 
2624     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2625     if (res) {
2626         host->top_base = devm_ioremap_resource(&pdev->dev, res);
2627         if (IS_ERR(host->top_base))
2628             host->top_base = NULL;
2629     }
2630 
2631     ret = mmc_regulator_get_supply(mmc);
2632     if (ret)
2633         goto host_free;
2634 
2635     ret = msdc_of_clock_parse(pdev, host);
2636     if (ret)
2637         goto host_free;
2638 
2639     host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2640                                 "hrst");
2641     if (IS_ERR(host->reset)) {
2642         ret = PTR_ERR(host->reset);
2643         goto host_free;
2644     }
2645 
2646     host->irq = platform_get_irq(pdev, 0);
2647     if (host->irq < 0) {
2648         ret = -EINVAL;
2649         goto host_free;
2650     }
2651 
2652     host->pinctrl = devm_pinctrl_get(&pdev->dev);
2653     if (IS_ERR(host->pinctrl)) {
2654         ret = PTR_ERR(host->pinctrl);
2655         dev_err(&pdev->dev, "Cannot find pinctrl!\n");
2656         goto host_free;
2657     }
2658 
2659     host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2660     if (IS_ERR(host->pins_default)) {
2661         ret = PTR_ERR(host->pins_default);
2662         dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2663         goto host_free;
2664     }
2665 
2666     host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2667     if (IS_ERR(host->pins_uhs)) {
2668         ret = PTR_ERR(host->pins_uhs);
2669         dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2670         goto host_free;
2671     }
2672 
2673     /* Support for SDIO eint irq ? */
2674     if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) {
2675         host->eint_irq = platform_get_irq_byname(pdev, "sdio_wakeup");
2676         if (host->eint_irq > 0) {
2677             host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
2678             if (IS_ERR(host->pins_eint)) {
2679                 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n");
2680                 host->pins_eint = NULL;
2681             } else {
2682                 device_init_wakeup(&pdev->dev, true);
2683             }
2684         }
2685     }
2686 
2687     msdc_of_property_parse(pdev, host);
2688 
2689     host->dev = &pdev->dev;
2690     host->dev_comp = of_device_get_match_data(&pdev->dev);
2691     host->src_clk_freq = clk_get_rate(host->src_clk);
2692     /* Set host parameters to mmc */
2693     mmc->ops = &mt_msdc_ops;
2694     if (host->dev_comp->clk_div_bits == 8)
2695         mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2696     else
2697         mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2698 
2699     if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2700         !mmc_can_gpio_cd(mmc) &&
2701         host->dev_comp->use_internal_cd) {
2702         /*
2703          * Is removable but no GPIO declared, so
2704          * use internal functionality.
2705          */
2706         host->internal_cd = true;
2707     }
2708 
2709     if (mmc->caps & MMC_CAP_SDIO_IRQ)
2710         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2711 
2712     mmc->caps |= MMC_CAP_CMD23;
2713     if (host->cqhci)
2714         mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2715     /* MMC core transfer sizes tunable parameters */
2716     mmc->max_segs = MAX_BD_NUM;
2717     if (host->dev_comp->support_64g)
2718         mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2719     else
2720         mmc->max_seg_size = BDMA_DESC_BUFLEN;
2721     mmc->max_blk_size = 2048;
2722     mmc->max_req_size = 512 * 1024;
2723     mmc->max_blk_count = mmc->max_req_size / 512;
2724     if (host->dev_comp->support_64g)
2725         host->dma_mask = DMA_BIT_MASK(36);
2726     else
2727         host->dma_mask = DMA_BIT_MASK(32);
2728     mmc_dev(mmc)->dma_mask = &host->dma_mask;
2729 
2730     host->timeout_clks = 3 * 1048576;
2731     host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2732                 2 * sizeof(struct mt_gpdma_desc),
2733                 &host->dma.gpd_addr, GFP_KERNEL);
2734     host->dma.bd = dma_alloc_coherent(&pdev->dev,
2735                 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2736                 &host->dma.bd_addr, GFP_KERNEL);
2737     if (!host->dma.gpd || !host->dma.bd) {
2738         ret = -ENOMEM;
2739         goto release_mem;
2740     }
2741     msdc_init_gpd_bd(host, &host->dma);
2742     INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2743     spin_lock_init(&host->lock);
2744 
2745     platform_set_drvdata(pdev, mmc);
2746     ret = msdc_ungate_clock(host);
2747     if (ret) {
2748         dev_err(&pdev->dev, "Cannot ungate clocks!\n");
2749         goto release_mem;
2750     }
2751     msdc_init_hw(host);
2752 
2753     if (mmc->caps2 & MMC_CAP2_CQE) {
2754         host->cq_host = devm_kzalloc(mmc->parent,
2755                          sizeof(*host->cq_host),
2756                          GFP_KERNEL);
2757         if (!host->cq_host) {
2758             ret = -ENOMEM;
2759             goto host_free;
2760         }
2761         host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2762         host->cq_host->mmio = host->base + 0x800;
2763         host->cq_host->ops = &msdc_cmdq_ops;
2764         ret = cqhci_init(host->cq_host, mmc, true);
2765         if (ret)
2766             goto host_free;
2767         mmc->max_segs = 128;
2768         /* cqhci 16bit length */
2769         /* 0 size, means 65536 so we don't have to -1 here */
2770         mmc->max_seg_size = 64 * 1024;
2771     }
2772 
2773     ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2774                    IRQF_TRIGGER_NONE, pdev->name, host);
2775     if (ret)
2776         goto release;
2777 
2778     pm_runtime_set_active(host->dev);
2779     pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2780     pm_runtime_use_autosuspend(host->dev);
2781     pm_runtime_enable(host->dev);
2782     ret = mmc_add_host(mmc);
2783 
2784     if (ret)
2785         goto end;
2786 
2787     return 0;
2788 end:
2789     pm_runtime_disable(host->dev);
2790 release:
2791     platform_set_drvdata(pdev, NULL);
2792     msdc_deinit_hw(host);
2793     msdc_gate_clock(host);
2794 release_mem:
2795     if (host->dma.gpd)
2796         dma_free_coherent(&pdev->dev,
2797             2 * sizeof(struct mt_gpdma_desc),
2798             host->dma.gpd, host->dma.gpd_addr);
2799     if (host->dma.bd)
2800         dma_free_coherent(&pdev->dev,
2801             MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2802             host->dma.bd, host->dma.bd_addr);
2803 host_free:
2804     mmc_free_host(mmc);
2805 
2806     return ret;
2807 }
2808 
2809 static int msdc_drv_remove(struct platform_device *pdev)
2810 {
2811     struct mmc_host *mmc;
2812     struct msdc_host *host;
2813 
2814     mmc = platform_get_drvdata(pdev);
2815     host = mmc_priv(mmc);
2816 
2817     pm_runtime_get_sync(host->dev);
2818 
2819     platform_set_drvdata(pdev, NULL);
2820     mmc_remove_host(mmc);
2821     msdc_deinit_hw(host);
2822     msdc_gate_clock(host);
2823 
2824     pm_runtime_disable(host->dev);
2825     pm_runtime_put_noidle(host->dev);
2826     dma_free_coherent(&pdev->dev,
2827             2 * sizeof(struct mt_gpdma_desc),
2828             host->dma.gpd, host->dma.gpd_addr);
2829     dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2830             host->dma.bd, host->dma.bd_addr);
2831 
2832     mmc_free_host(mmc);
2833 
2834     return 0;
2835 }
2836 
2837 static void msdc_save_reg(struct msdc_host *host)
2838 {
2839     u32 tune_reg = host->dev_comp->pad_tune_reg;
2840 
2841     host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2842     host->save_para.iocon = readl(host->base + MSDC_IOCON);
2843     host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2844     host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2845     host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2846     host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2847     host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2848     host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2849     host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2850     host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2851     host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2852     if (host->top_base) {
2853         host->save_para.emmc_top_control =
2854             readl(host->top_base + EMMC_TOP_CONTROL);
2855         host->save_para.emmc_top_cmd =
2856             readl(host->top_base + EMMC_TOP_CMD);
2857         host->save_para.emmc50_pad_ds_tune =
2858             readl(host->top_base + EMMC50_PAD_DS_TUNE);
2859     } else {
2860         host->save_para.pad_tune = readl(host->base + tune_reg);
2861     }
2862 }
2863 
2864 static void msdc_restore_reg(struct msdc_host *host)
2865 {
2866     struct mmc_host *mmc = mmc_from_priv(host);
2867     u32 tune_reg = host->dev_comp->pad_tune_reg;
2868 
2869     writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2870     writel(host->save_para.iocon, host->base + MSDC_IOCON);
2871     writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2872     writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2873     writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2874     writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2875     writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2876     writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2877     writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2878     writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2879     writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2880     if (host->top_base) {
2881         writel(host->save_para.emmc_top_control,
2882                host->top_base + EMMC_TOP_CONTROL);
2883         writel(host->save_para.emmc_top_cmd,
2884                host->top_base + EMMC_TOP_CMD);
2885         writel(host->save_para.emmc50_pad_ds_tune,
2886                host->top_base + EMMC50_PAD_DS_TUNE);
2887     } else {
2888         writel(host->save_para.pad_tune, host->base + tune_reg);
2889     }
2890 
2891     if (sdio_irq_claimed(mmc))
2892         __msdc_enable_sdio_irq(host, 1);
2893 }
2894 
2895 static int __maybe_unused msdc_runtime_suspend(struct device *dev)
2896 {
2897     struct mmc_host *mmc = dev_get_drvdata(dev);
2898     struct msdc_host *host = mmc_priv(mmc);
2899 
2900     msdc_save_reg(host);
2901 
2902     if (sdio_irq_claimed(mmc)) {
2903         if (host->pins_eint) {
2904             disable_irq(host->irq);
2905             pinctrl_select_state(host->pinctrl, host->pins_eint);
2906         }
2907 
2908         __msdc_enable_sdio_irq(host, 0);
2909     }
2910     msdc_gate_clock(host);
2911     return 0;
2912 }
2913 
2914 static int __maybe_unused msdc_runtime_resume(struct device *dev)
2915 {
2916     struct mmc_host *mmc = dev_get_drvdata(dev);
2917     struct msdc_host *host = mmc_priv(mmc);
2918     int ret;
2919 
2920     ret = msdc_ungate_clock(host);
2921     if (ret)
2922         return ret;
2923 
2924     msdc_restore_reg(host);
2925 
2926     if (sdio_irq_claimed(mmc) && host->pins_eint) {
2927         pinctrl_select_state(host->pinctrl, host->pins_uhs);
2928         enable_irq(host->irq);
2929     }
2930     return 0;
2931 }
2932 
2933 static int __maybe_unused msdc_suspend(struct device *dev)
2934 {
2935     struct mmc_host *mmc = dev_get_drvdata(dev);
2936     struct msdc_host *host = mmc_priv(mmc);
2937     int ret;
2938     u32 val;
2939 
2940     if (mmc->caps2 & MMC_CAP2_CQE) {
2941         ret = cqhci_suspend(mmc);
2942         if (ret)
2943             return ret;
2944         val = readl(host->base + MSDC_INT);
2945         writel(val, host->base + MSDC_INT);
2946     }
2947 
2948     /*
2949      * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will
2950      * not be marked as 1, pm_runtime_force_resume() will go out directly.
2951      */
2952     if (sdio_irq_claimed(mmc) && host->pins_eint)
2953         pm_runtime_get_noresume(dev);
2954 
2955     return pm_runtime_force_suspend(dev);
2956 }
2957 
2958 static int __maybe_unused msdc_resume(struct device *dev)
2959 {
2960     struct mmc_host *mmc = dev_get_drvdata(dev);
2961     struct msdc_host *host = mmc_priv(mmc);
2962 
2963     if (sdio_irq_claimed(mmc) && host->pins_eint)
2964         pm_runtime_put_noidle(dev);
2965 
2966     return pm_runtime_force_resume(dev);
2967 }
2968 
2969 static const struct dev_pm_ops msdc_dev_pm_ops = {
2970     SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
2971     SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
2972 };
2973 
2974 static struct platform_driver mt_msdc_driver = {
2975     .probe = msdc_drv_probe,
2976     .remove = msdc_drv_remove,
2977     .driver = {
2978         .name = "mtk-msdc",
2979         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2980         .of_match_table = msdc_of_ids,
2981         .pm = &msdc_dev_pm_ops,
2982     },
2983 };
2984 
2985 module_platform_driver(mt_msdc_driver);
2986 MODULE_LICENSE("GPL v2");
2987 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
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