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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
0004  * Author: Ludovic.barre@st.com for STMicroelectronics.
0005  */
0006 #include <linux/bitfield.h>
0007 #include <linux/delay.h>
0008 #include <linux/dma-mapping.h>
0009 #include <linux/iopoll.h>
0010 #include <linux/mmc/host.h>
0011 #include <linux/mmc/card.h>
0012 #include <linux/of_address.h>
0013 #include <linux/reset.h>
0014 #include <linux/scatterlist.h>
0015 #include "mmci.h"
0016 
0017 #define SDMMC_LLI_BUF_LEN   PAGE_SIZE
0018 #define SDMMC_IDMA_BURST    BIT(MMCI_STM32_IDMABNDT_SHIFT)
0019 
0020 #define DLYB_CR         0x0
0021 #define DLYB_CR_DEN     BIT(0)
0022 #define DLYB_CR_SEN     BIT(1)
0023 
0024 #define DLYB_CFGR       0x4
0025 #define DLYB_CFGR_SEL_MASK  GENMASK(3, 0)
0026 #define DLYB_CFGR_UNIT_MASK GENMASK(14, 8)
0027 #define DLYB_CFGR_LNG_MASK  GENMASK(27, 16)
0028 #define DLYB_CFGR_LNGF      BIT(31)
0029 
0030 #define DLYB_NB_DELAY       11
0031 #define DLYB_CFGR_SEL_MAX   (DLYB_NB_DELAY + 1)
0032 #define DLYB_CFGR_UNIT_MAX  127
0033 
0034 #define DLYB_LNG_TIMEOUT_US 1000
0035 #define SDMMC_VSWEND_TIMEOUT_US 10000
0036 
0037 struct sdmmc_lli_desc {
0038     u32 idmalar;
0039     u32 idmabase;
0040     u32 idmasize;
0041 };
0042 
0043 struct sdmmc_idma {
0044     dma_addr_t sg_dma;
0045     void *sg_cpu;
0046     dma_addr_t bounce_dma_addr;
0047     void *bounce_buf;
0048     bool use_bounce_buffer;
0049 };
0050 
0051 struct sdmmc_dlyb {
0052     void __iomem *base;
0053     u32 unit;
0054     u32 max;
0055 };
0056 
0057 static int sdmmc_idma_validate_data(struct mmci_host *host,
0058                     struct mmc_data *data)
0059 {
0060     struct sdmmc_idma *idma = host->dma_priv;
0061     struct device *dev = mmc_dev(host->mmc);
0062     struct scatterlist *sg;
0063     int i;
0064 
0065     /*
0066      * idma has constraints on idmabase & idmasize for each element
0067      * excepted the last element which has no constraint on idmasize
0068      */
0069     idma->use_bounce_buffer = false;
0070     for_each_sg(data->sg, sg, data->sg_len - 1, i) {
0071         if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
0072             !IS_ALIGNED(sg->length, SDMMC_IDMA_BURST)) {
0073             dev_dbg(mmc_dev(host->mmc),
0074                 "unaligned scatterlist: ofst:%x length:%d\n",
0075                 data->sg->offset, data->sg->length);
0076             goto use_bounce_buffer;
0077         }
0078     }
0079 
0080     if (!IS_ALIGNED(sg->offset, sizeof(u32))) {
0081         dev_dbg(mmc_dev(host->mmc),
0082             "unaligned last scatterlist: ofst:%x length:%d\n",
0083             data->sg->offset, data->sg->length);
0084         goto use_bounce_buffer;
0085     }
0086 
0087     return 0;
0088 
0089 use_bounce_buffer:
0090     if (!idma->bounce_buf) {
0091         idma->bounce_buf = dmam_alloc_coherent(dev,
0092                                host->mmc->max_req_size,
0093                                &idma->bounce_dma_addr,
0094                                GFP_KERNEL);
0095         if (!idma->bounce_buf) {
0096             dev_err(dev, "Unable to map allocate DMA bounce buffer.\n");
0097             return -ENOMEM;
0098         }
0099     }
0100 
0101     idma->use_bounce_buffer = true;
0102 
0103     return 0;
0104 }
0105 
0106 static int _sdmmc_idma_prep_data(struct mmci_host *host,
0107                  struct mmc_data *data)
0108 {
0109     struct sdmmc_idma *idma = host->dma_priv;
0110 
0111     if (idma->use_bounce_buffer) {
0112         if (data->flags & MMC_DATA_WRITE) {
0113             unsigned int xfer_bytes = data->blksz * data->blocks;
0114 
0115             sg_copy_to_buffer(data->sg, data->sg_len,
0116                       idma->bounce_buf, xfer_bytes);
0117             dma_wmb();
0118         }
0119     } else {
0120         int n_elem;
0121 
0122         n_elem = dma_map_sg(mmc_dev(host->mmc),
0123                     data->sg,
0124                     data->sg_len,
0125                     mmc_get_dma_dir(data));
0126 
0127         if (!n_elem) {
0128             dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
0129             return -EINVAL;
0130         }
0131     }
0132     return 0;
0133 }
0134 
0135 static int sdmmc_idma_prep_data(struct mmci_host *host,
0136                 struct mmc_data *data, bool next)
0137 {
0138     /* Check if job is already prepared. */
0139     if (!next && data->host_cookie == host->next_cookie)
0140         return 0;
0141 
0142     return _sdmmc_idma_prep_data(host, data);
0143 }
0144 
0145 static void sdmmc_idma_unprep_data(struct mmci_host *host,
0146                    struct mmc_data *data, int err)
0147 {
0148     struct sdmmc_idma *idma = host->dma_priv;
0149 
0150     if (idma->use_bounce_buffer) {
0151         if (data->flags & MMC_DATA_READ) {
0152             unsigned int xfer_bytes = data->blksz * data->blocks;
0153 
0154             sg_copy_from_buffer(data->sg, data->sg_len,
0155                         idma->bounce_buf, xfer_bytes);
0156         }
0157     } else {
0158         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
0159                  mmc_get_dma_dir(data));
0160     }
0161 }
0162 
0163 static int sdmmc_idma_setup(struct mmci_host *host)
0164 {
0165     struct sdmmc_idma *idma;
0166     struct device *dev = mmc_dev(host->mmc);
0167 
0168     idma = devm_kzalloc(dev, sizeof(*idma), GFP_KERNEL);
0169     if (!idma)
0170         return -ENOMEM;
0171 
0172     host->dma_priv = idma;
0173 
0174     if (host->variant->dma_lli) {
0175         idma->sg_cpu = dmam_alloc_coherent(dev, SDMMC_LLI_BUF_LEN,
0176                            &idma->sg_dma, GFP_KERNEL);
0177         if (!idma->sg_cpu) {
0178             dev_err(dev, "Failed to alloc IDMA descriptor\n");
0179             return -ENOMEM;
0180         }
0181         host->mmc->max_segs = SDMMC_LLI_BUF_LEN /
0182             sizeof(struct sdmmc_lli_desc);
0183         host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask;
0184 
0185         host->mmc->max_req_size = SZ_1M;
0186     } else {
0187         host->mmc->max_segs = 1;
0188         host->mmc->max_seg_size = host->mmc->max_req_size;
0189     }
0190 
0191     return dma_set_max_seg_size(dev, host->mmc->max_seg_size);
0192 }
0193 
0194 static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl)
0195 
0196 {
0197     struct sdmmc_idma *idma = host->dma_priv;
0198     struct sdmmc_lli_desc *desc = (struct sdmmc_lli_desc *)idma->sg_cpu;
0199     struct mmc_data *data = host->data;
0200     struct scatterlist *sg;
0201     int i;
0202 
0203     if (!host->variant->dma_lli || data->sg_len == 1 ||
0204         idma->use_bounce_buffer) {
0205         u32 dma_addr;
0206 
0207         if (idma->use_bounce_buffer)
0208             dma_addr = idma->bounce_dma_addr;
0209         else
0210             dma_addr = sg_dma_address(data->sg);
0211 
0212         writel_relaxed(dma_addr,
0213                    host->base + MMCI_STM32_IDMABASE0R);
0214         writel_relaxed(MMCI_STM32_IDMAEN,
0215                    host->base + MMCI_STM32_IDMACTRLR);
0216         return 0;
0217     }
0218 
0219     for_each_sg(data->sg, sg, data->sg_len, i) {
0220         desc[i].idmalar = (i + 1) * sizeof(struct sdmmc_lli_desc);
0221         desc[i].idmalar |= MMCI_STM32_ULA | MMCI_STM32_ULS
0222             | MMCI_STM32_ABR;
0223         desc[i].idmabase = sg_dma_address(sg);
0224         desc[i].idmasize = sg_dma_len(sg);
0225     }
0226 
0227     /* notice the end of link list */
0228     desc[data->sg_len - 1].idmalar &= ~MMCI_STM32_ULA;
0229 
0230     dma_wmb();
0231     writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
0232     writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
0233     writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
0234     writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
0235     writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN,
0236                host->base + MMCI_STM32_IDMACTRLR);
0237 
0238     return 0;
0239 }
0240 
0241 static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data)
0242 {
0243     writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
0244 
0245     if (!data->host_cookie)
0246         sdmmc_idma_unprep_data(host, data, 0);
0247 }
0248 
0249 static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
0250 {
0251     unsigned int clk = 0, ddr = 0;
0252 
0253     if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
0254         host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
0255         ddr = MCI_STM32_CLK_DDR;
0256 
0257     /*
0258      * cclk = mclk / (2 * clkdiv)
0259      * clkdiv 0 => bypass
0260      * in ddr mode bypass is not possible
0261      */
0262     if (desired) {
0263         if (desired >= host->mclk && !ddr) {
0264             host->cclk = host->mclk;
0265         } else {
0266             clk = DIV_ROUND_UP(host->mclk, 2 * desired);
0267             if (clk > MCI_STM32_CLK_CLKDIV_MSK)
0268                 clk = MCI_STM32_CLK_CLKDIV_MSK;
0269             host->cclk = host->mclk / (2 * clk);
0270         }
0271     } else {
0272         /*
0273          * while power-on phase the clock can't be define to 0,
0274          * Only power-off and power-cyc deactivate the clock.
0275          * if desired clock is 0, set max divider
0276          */
0277         clk = MCI_STM32_CLK_CLKDIV_MSK;
0278         host->cclk = host->mclk / (2 * clk);
0279     }
0280 
0281     /* Set actual clock for debug */
0282     if (host->mmc->ios.power_mode == MMC_POWER_ON)
0283         host->mmc->actual_clock = host->cclk;
0284     else
0285         host->mmc->actual_clock = 0;
0286 
0287     if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
0288         clk |= MCI_STM32_CLK_WIDEBUS_4;
0289     if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
0290         clk |= MCI_STM32_CLK_WIDEBUS_8;
0291 
0292     clk |= MCI_STM32_CLK_HWFCEN;
0293     clk |= host->clk_reg_add;
0294     clk |= ddr;
0295 
0296     /*
0297      * SDMMC_FBCK is selected when an external Delay Block is needed
0298      * with SDR104 or HS200.
0299      */
0300     if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) {
0301         clk |= MCI_STM32_CLK_BUSSPEED;
0302         if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 ||
0303             host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
0304             clk &= ~MCI_STM32_CLK_SEL_MSK;
0305             clk |= MCI_STM32_CLK_SELFBCK;
0306         }
0307     }
0308 
0309     mmci_write_clkreg(host, clk);
0310 }
0311 
0312 static void sdmmc_dlyb_input_ck(struct sdmmc_dlyb *dlyb)
0313 {
0314     if (!dlyb || !dlyb->base)
0315         return;
0316 
0317     /* Output clock = Input clock */
0318     writel_relaxed(0, dlyb->base + DLYB_CR);
0319 }
0320 
0321 static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr)
0322 {
0323     struct mmc_ios ios = host->mmc->ios;
0324     struct sdmmc_dlyb *dlyb = host->variant_priv;
0325 
0326     /* adds OF options */
0327     pwr = host->pwr_reg_add;
0328 
0329     sdmmc_dlyb_input_ck(dlyb);
0330 
0331     if (ios.power_mode == MMC_POWER_OFF) {
0332         /* Only a reset could power-off sdmmc */
0333         reset_control_assert(host->rst);
0334         udelay(2);
0335         reset_control_deassert(host->rst);
0336 
0337         /*
0338          * Set the SDMMC in Power-cycle state.
0339          * This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK
0340          * are driven low, to prevent the Card from being supplied
0341          * through the signal lines.
0342          */
0343         mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr);
0344     } else if (ios.power_mode == MMC_POWER_ON) {
0345         /*
0346          * After power-off (reset): the irq mask defined in probe
0347          * functionis lost
0348          * ault irq mask (probe) must be activated
0349          */
0350         writel(MCI_IRQENABLE | host->variant->start_err,
0351                host->base + MMCIMASK0);
0352 
0353         /* preserves voltage switch bits */
0354         pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN |
0355                     MCI_STM32_VSWITCH);
0356 
0357         /*
0358          * After a power-cycle state, we must set the SDMMC in
0359          * Power-off. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are
0360          * driven high. Then we can set the SDMMC to Power-on state
0361          */
0362         mmci_write_pwrreg(host, MCI_PWR_OFF | pwr);
0363         mdelay(1);
0364         mmci_write_pwrreg(host, MCI_PWR_ON | pwr);
0365     }
0366 }
0367 
0368 static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host)
0369 {
0370     u32 datactrl;
0371 
0372     datactrl = mmci_dctrl_blksz(host);
0373 
0374     if (host->mmc->card && mmc_card_sdio(host->mmc->card) &&
0375         host->data->blocks == 1)
0376         datactrl |= MCI_DPSM_STM32_MODE_SDIO;
0377     else if (host->data->stop && !host->mrq->sbc)
0378         datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP;
0379     else
0380         datactrl |= MCI_DPSM_STM32_MODE_BLOCK;
0381 
0382     return datactrl;
0383 }
0384 
0385 static bool sdmmc_busy_complete(struct mmci_host *host, u32 status, u32 err_msk)
0386 {
0387     void __iomem *base = host->base;
0388     u32 busy_d0, busy_d0end, mask, sdmmc_status;
0389 
0390     mask = readl_relaxed(base + MMCIMASK0);
0391     sdmmc_status = readl_relaxed(base + MMCISTATUS);
0392     busy_d0end = sdmmc_status & MCI_STM32_BUSYD0END;
0393     busy_d0 = sdmmc_status & MCI_STM32_BUSYD0;
0394 
0395     /* complete if there is an error or busy_d0end */
0396     if ((status & err_msk) || busy_d0end)
0397         goto complete;
0398 
0399     /*
0400      * On response the busy signaling is reflected in the BUSYD0 flag.
0401      * if busy_d0 is in-progress we must activate busyd0end interrupt
0402      * to wait this completion. Else this request has no busy step.
0403      */
0404     if (busy_d0) {
0405         if (!host->busy_status) {
0406             writel_relaxed(mask | host->variant->busy_detect_mask,
0407                        base + MMCIMASK0);
0408             host->busy_status = status &
0409                 (MCI_CMDSENT | MCI_CMDRESPEND);
0410         }
0411         return false;
0412     }
0413 
0414 complete:
0415     if (host->busy_status) {
0416         writel_relaxed(mask & ~host->variant->busy_detect_mask,
0417                    base + MMCIMASK0);
0418         host->busy_status = 0;
0419     }
0420 
0421     writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR);
0422 
0423     return true;
0424 }
0425 
0426 static void sdmmc_dlyb_set_cfgr(struct sdmmc_dlyb *dlyb,
0427                 int unit, int phase, bool sampler)
0428 {
0429     u32 cfgr;
0430 
0431     writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR);
0432 
0433     cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) |
0434            FIELD_PREP(DLYB_CFGR_SEL_MASK, phase);
0435     writel_relaxed(cfgr, dlyb->base + DLYB_CFGR);
0436 
0437     if (!sampler)
0438         writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
0439 }
0440 
0441 static int sdmmc_dlyb_lng_tuning(struct mmci_host *host)
0442 {
0443     struct sdmmc_dlyb *dlyb = host->variant_priv;
0444     u32 cfgr;
0445     int i, lng, ret;
0446 
0447     for (i = 0; i <= DLYB_CFGR_UNIT_MAX; i++) {
0448         sdmmc_dlyb_set_cfgr(dlyb, i, DLYB_CFGR_SEL_MAX, true);
0449 
0450         ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr,
0451                          (cfgr & DLYB_CFGR_LNGF),
0452                          1, DLYB_LNG_TIMEOUT_US);
0453         if (ret) {
0454             dev_warn(mmc_dev(host->mmc),
0455                  "delay line cfg timeout unit:%d cfgr:%d\n",
0456                  i, cfgr);
0457             continue;
0458         }
0459 
0460         lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr);
0461         if (lng < BIT(DLYB_NB_DELAY) && lng > 0)
0462             break;
0463     }
0464 
0465     if (i > DLYB_CFGR_UNIT_MAX)
0466         return -EINVAL;
0467 
0468     dlyb->unit = i;
0469     dlyb->max = __fls(lng);
0470 
0471     return 0;
0472 }
0473 
0474 static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode)
0475 {
0476     struct sdmmc_dlyb *dlyb = host->variant_priv;
0477     int cur_len = 0, max_len = 0, end_of_len = 0;
0478     int phase;
0479 
0480     for (phase = 0; phase <= dlyb->max; phase++) {
0481         sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
0482 
0483         if (mmc_send_tuning(host->mmc, opcode, NULL)) {
0484             cur_len = 0;
0485         } else {
0486             cur_len++;
0487             if (cur_len > max_len) {
0488                 max_len = cur_len;
0489                 end_of_len = phase;
0490             }
0491         }
0492     }
0493 
0494     if (!max_len) {
0495         dev_err(mmc_dev(host->mmc), "no tuning point found\n");
0496         return -EINVAL;
0497     }
0498 
0499     writel_relaxed(0, dlyb->base + DLYB_CR);
0500 
0501     phase = end_of_len - max_len / 2;
0502     sdmmc_dlyb_set_cfgr(dlyb, dlyb->unit, phase, false);
0503 
0504     dev_dbg(mmc_dev(host->mmc), "unit:%d max_dly:%d phase:%d\n",
0505         dlyb->unit, dlyb->max, phase);
0506 
0507     return 0;
0508 }
0509 
0510 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
0511 {
0512     struct mmci_host *host = mmc_priv(mmc);
0513     struct sdmmc_dlyb *dlyb = host->variant_priv;
0514 
0515     if (!dlyb || !dlyb->base)
0516         return -EINVAL;
0517 
0518     if (sdmmc_dlyb_lng_tuning(host))
0519         return -EINVAL;
0520 
0521     return sdmmc_dlyb_phase_tuning(host, opcode);
0522 }
0523 
0524 static void sdmmc_pre_sig_volt_vswitch(struct mmci_host *host)
0525 {
0526     /* clear the voltage switch completion flag */
0527     writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR);
0528     /* enable Voltage switch procedure */
0529     mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN);
0530 }
0531 
0532 static int sdmmc_post_sig_volt_switch(struct mmci_host *host,
0533                       struct mmc_ios *ios)
0534 {
0535     unsigned long flags;
0536     u32 status;
0537     int ret = 0;
0538 
0539     spin_lock_irqsave(&host->lock, flags);
0540     if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 &&
0541         host->pwr_reg & MCI_STM32_VSWITCHEN) {
0542         mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH);
0543         spin_unlock_irqrestore(&host->lock, flags);
0544 
0545         /* wait voltage switch completion while 10ms */
0546         ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS,
0547                          status,
0548                          (status & MCI_STM32_VSWEND),
0549                          10, SDMMC_VSWEND_TIMEOUT_US);
0550 
0551         writel_relaxed(MCI_STM32_VSWENDC | MCI_STM32_CKSTOPC,
0552                    host->base + MMCICLEAR);
0553         spin_lock_irqsave(&host->lock, flags);
0554         mmci_write_pwrreg(host, host->pwr_reg &
0555                   ~(MCI_STM32_VSWITCHEN | MCI_STM32_VSWITCH));
0556     }
0557     spin_unlock_irqrestore(&host->lock, flags);
0558 
0559     return ret;
0560 }
0561 
0562 static struct mmci_host_ops sdmmc_variant_ops = {
0563     .validate_data = sdmmc_idma_validate_data,
0564     .prep_data = sdmmc_idma_prep_data,
0565     .unprep_data = sdmmc_idma_unprep_data,
0566     .get_datactrl_cfg = sdmmc_get_dctrl_cfg,
0567     .dma_setup = sdmmc_idma_setup,
0568     .dma_start = sdmmc_idma_start,
0569     .dma_finalize = sdmmc_idma_finalize,
0570     .set_clkreg = mmci_sdmmc_set_clkreg,
0571     .set_pwrreg = mmci_sdmmc_set_pwrreg,
0572     .busy_complete = sdmmc_busy_complete,
0573     .pre_sig_volt_switch = sdmmc_pre_sig_volt_vswitch,
0574     .post_sig_volt_switch = sdmmc_post_sig_volt_switch,
0575 };
0576 
0577 void sdmmc_variant_init(struct mmci_host *host)
0578 {
0579     struct device_node *np = host->mmc->parent->of_node;
0580     void __iomem *base_dlyb;
0581     struct sdmmc_dlyb *dlyb;
0582 
0583     host->ops = &sdmmc_variant_ops;
0584     host->pwr_reg = readl_relaxed(host->base + MMCIPOWER);
0585 
0586     base_dlyb = devm_of_iomap(mmc_dev(host->mmc), np, 1, NULL);
0587     if (IS_ERR(base_dlyb))
0588         return;
0589 
0590     dlyb = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dlyb), GFP_KERNEL);
0591     if (!dlyb)
0592         return;
0593 
0594     dlyb->base = base_dlyb;
0595     host->variant_priv = dlyb;
0596     host->mmc_ops->execute_tuning = sdmmc_execute_tuning;
0597 }
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