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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
0004  *
0005  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
0006  */
0007 #define MMCIPOWER       0x000
0008 #define MCI_PWR_OFF     0x00
0009 #define MCI_PWR_UP      0x02
0010 #define MCI_PWR_ON      0x03
0011 #define MCI_OD          (1 << 6)
0012 #define MCI_ROD         (1 << 7)
0013 /*
0014  * The ST Micro version does not have ROD and reuse the voltage registers for
0015  * direction settings.
0016  */
0017 #define MCI_ST_DATA2DIREN   (1 << 2)
0018 #define MCI_ST_CMDDIREN     (1 << 3)
0019 #define MCI_ST_DATA0DIREN   (1 << 4)
0020 #define MCI_ST_DATA31DIREN  (1 << 5)
0021 #define MCI_ST_FBCLKEN      (1 << 7)
0022 #define MCI_ST_DATA74DIREN  (1 << 8)
0023 /*
0024  * The STM32 sdmmc does not have PWR_UP/OD/ROD
0025  * and uses the power register for
0026  */
0027 #define MCI_STM32_PWR_CYC   0x02
0028 #define MCI_STM32_VSWITCH   BIT(2)
0029 #define MCI_STM32_VSWITCHEN BIT(3)
0030 #define MCI_STM32_DIRPOL    BIT(4)
0031 
0032 #define MMCICLOCK       0x004
0033 #define MCI_CLK_ENABLE      (1 << 8)
0034 #define MCI_CLK_PWRSAVE     (1 << 9)
0035 #define MCI_CLK_BYPASS      (1 << 10)
0036 #define MCI_4BIT_BUS        (1 << 11)
0037 /*
0038  * 8bit wide buses, hardware flow contronl, negative edges and clock inversion
0039  * supported in ST Micro U300 and Ux500 versions
0040  */
0041 #define MCI_ST_8BIT_BUS     (1 << 12)
0042 #define MCI_ST_U300_HWFCEN  (1 << 13)
0043 #define MCI_ST_UX500_NEG_EDGE   (1 << 13)
0044 #define MCI_ST_UX500_HWFCEN (1 << 14)
0045 #define MCI_ST_UX500_CLK_INV    (1 << 15)
0046 /* Modified PL180 on Versatile Express platform */
0047 #define MCI_ARM_HWFCEN      (1 << 12)
0048 
0049 /* Modified on Qualcomm Integrations */
0050 #define MCI_QCOM_CLK_WIDEBUS_8  (BIT(10) | BIT(11))
0051 #define MCI_QCOM_CLK_FLOWENA    BIT(12)
0052 #define MCI_QCOM_CLK_INVERTOUT  BIT(13)
0053 
0054 /* select in latch data and command in */
0055 #define MCI_QCOM_CLK_SELECT_IN_FBCLK    BIT(15)
0056 #define MCI_QCOM_CLK_SELECT_IN_DDR_MODE (BIT(14) | BIT(15))
0057 
0058 /* Modified on STM32 sdmmc */
0059 #define MCI_STM32_CLK_CLKDIV_MSK    GENMASK(9, 0)
0060 #define MCI_STM32_CLK_WIDEBUS_4     BIT(14)
0061 #define MCI_STM32_CLK_WIDEBUS_8     BIT(15)
0062 #define MCI_STM32_CLK_NEGEDGE       BIT(16)
0063 #define MCI_STM32_CLK_HWFCEN        BIT(17)
0064 #define MCI_STM32_CLK_DDR       BIT(18)
0065 #define MCI_STM32_CLK_BUSSPEED      BIT(19)
0066 #define MCI_STM32_CLK_SEL_MSK       GENMASK(21, 20)
0067 #define MCI_STM32_CLK_SELCK     (0 << 20)
0068 #define MCI_STM32_CLK_SELCKIN       (1 << 20)
0069 #define MCI_STM32_CLK_SELFBCK       (2 << 20)
0070 
0071 #define MMCIARGUMENT        0x008
0072 
0073 /* The command register controls the Command Path State Machine (CPSM) */
0074 #define MMCICOMMAND     0x00c
0075 #define MCI_CPSM_RESPONSE   BIT(6)
0076 #define MCI_CPSM_LONGRSP    BIT(7)
0077 #define MCI_CPSM_INTERRUPT  BIT(8)
0078 #define MCI_CPSM_PENDING    BIT(9)
0079 #define MCI_CPSM_ENABLE     BIT(10)
0080 /* Command register flag extenstions in the ST Micro versions */
0081 #define MCI_CPSM_ST_SDIO_SUSP       BIT(11)
0082 #define MCI_CPSM_ST_ENCMD_COMPL     BIT(12)
0083 #define MCI_CPSM_ST_NIEN        BIT(13)
0084 #define MCI_CPSM_ST_CE_ATACMD       BIT(14)
0085 /* Command register flag extensions in the Qualcomm versions */
0086 #define MCI_CPSM_QCOM_PROGENA       BIT(11)
0087 #define MCI_CPSM_QCOM_DATCMD        BIT(12)
0088 #define MCI_CPSM_QCOM_MCIABORT      BIT(13)
0089 #define MCI_CPSM_QCOM_CCSENABLE     BIT(14)
0090 #define MCI_CPSM_QCOM_CCSDISABLE    BIT(15)
0091 #define MCI_CPSM_QCOM_AUTO_CMD19    BIT(16)
0092 #define MCI_CPSM_QCOM_AUTO_CMD21    BIT(21)
0093 /* Command register in STM32 sdmmc versions */
0094 #define MCI_CPSM_STM32_CMDTRANS     BIT(6)
0095 #define MCI_CPSM_STM32_CMDSTOP      BIT(7)
0096 #define MCI_CPSM_STM32_WAITRESP_MASK    GENMASK(9, 8)
0097 #define MCI_CPSM_STM32_NORSP        (0 << 8)
0098 #define MCI_CPSM_STM32_SRSP_CRC     (1 << 8)
0099 #define MCI_CPSM_STM32_SRSP     (2 << 8)
0100 #define MCI_CPSM_STM32_LRSP_CRC     (3 << 8)
0101 #define MCI_CPSM_STM32_ENABLE       BIT(12)
0102 
0103 #define MMCIRESPCMD     0x010
0104 #define MMCIRESPONSE0       0x014
0105 #define MMCIRESPONSE1       0x018
0106 #define MMCIRESPONSE2       0x01c
0107 #define MMCIRESPONSE3       0x020
0108 #define MMCIDATATIMER       0x024
0109 #define MMCIDATALENGTH      0x028
0110 
0111 /* The data control register controls the Data Path State Machine (DPSM) */
0112 #define MMCIDATACTRL        0x02c
0113 #define MCI_DPSM_ENABLE     BIT(0)
0114 #define MCI_DPSM_DIRECTION  BIT(1)
0115 #define MCI_DPSM_MODE       BIT(2)
0116 #define MCI_DPSM_DMAENABLE  BIT(3)
0117 #define MCI_DPSM_BLOCKSIZE  BIT(4)
0118 /* Control register extensions in the ST Micro U300 and Ux500 versions */
0119 #define MCI_DPSM_ST_RWSTART BIT(8)
0120 #define MCI_DPSM_ST_RWSTOP  BIT(9)
0121 #define MCI_DPSM_ST_RWMOD   BIT(10)
0122 #define MCI_DPSM_ST_SDIOEN  BIT(11)
0123 /* Control register extensions in the ST Micro Ux500 versions */
0124 #define MCI_DPSM_ST_DMAREQCTL   BIT(12)
0125 #define MCI_DPSM_ST_DBOOTMODEEN BIT(13)
0126 #define MCI_DPSM_ST_BUSYMODE    BIT(14)
0127 #define MCI_DPSM_ST_DDRMODE BIT(15)
0128 /* Control register extensions in the Qualcomm versions */
0129 #define MCI_DPSM_QCOM_DATA_PEND BIT(17)
0130 #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)
0131 /* Control register extensions in STM32 versions */
0132 #define MCI_DPSM_STM32_MODE_BLOCK   (0 << 2)
0133 #define MCI_DPSM_STM32_MODE_SDIO    (1 << 2)
0134 #define MCI_DPSM_STM32_MODE_STREAM  (2 << 2)
0135 #define MCI_DPSM_STM32_MODE_BLOCK_STOP  (3 << 2)
0136 
0137 #define MMCIDATACNT     0x030
0138 #define MMCISTATUS      0x034
0139 #define MCI_CMDCRCFAIL      (1 << 0)
0140 #define MCI_DATACRCFAIL     (1 << 1)
0141 #define MCI_CMDTIMEOUT      (1 << 2)
0142 #define MCI_DATATIMEOUT     (1 << 3)
0143 #define MCI_TXUNDERRUN      (1 << 4)
0144 #define MCI_RXOVERRUN       (1 << 5)
0145 #define MCI_CMDRESPEND      (1 << 6)
0146 #define MCI_CMDSENT     (1 << 7)
0147 #define MCI_DATAEND     (1 << 8)
0148 #define MCI_STARTBITERR     (1 << 9)
0149 #define MCI_DATABLOCKEND    (1 << 10)
0150 #define MCI_CMDACTIVE       (1 << 11)
0151 #define MCI_TXACTIVE        (1 << 12)
0152 #define MCI_RXACTIVE        (1 << 13)
0153 #define MCI_TXFIFOHALFEMPTY (1 << 14)
0154 #define MCI_RXFIFOHALFFULL  (1 << 15)
0155 #define MCI_TXFIFOFULL      (1 << 16)
0156 #define MCI_RXFIFOFULL      (1 << 17)
0157 #define MCI_TXFIFOEMPTY     (1 << 18)
0158 #define MCI_RXFIFOEMPTY     (1 << 19)
0159 #define MCI_TXDATAAVLBL     (1 << 20)
0160 #define MCI_RXDATAAVLBL     (1 << 21)
0161 /* Extended status bits for the ST Micro variants */
0162 #define MCI_ST_SDIOIT       (1 << 22)
0163 #define MCI_ST_CEATAEND     (1 << 23)
0164 #define MCI_ST_CARDBUSY     (1 << 24)
0165 /* Extended status bits for the STM32 variants */
0166 #define MCI_STM32_BUSYD0    BIT(20)
0167 #define MCI_STM32_BUSYD0END BIT(21)
0168 #define MCI_STM32_VSWEND    BIT(25)
0169 
0170 #define MMCICLEAR       0x038
0171 #define MCI_CMDCRCFAILCLR   (1 << 0)
0172 #define MCI_DATACRCFAILCLR  (1 << 1)
0173 #define MCI_CMDTIMEOUTCLR   (1 << 2)
0174 #define MCI_DATATIMEOUTCLR  (1 << 3)
0175 #define MCI_TXUNDERRUNCLR   (1 << 4)
0176 #define MCI_RXOVERRUNCLR    (1 << 5)
0177 #define MCI_CMDRESPENDCLR   (1 << 6)
0178 #define MCI_CMDSENTCLR      (1 << 7)
0179 #define MCI_DATAENDCLR      (1 << 8)
0180 #define MCI_STARTBITERRCLR  (1 << 9)
0181 #define MCI_DATABLOCKENDCLR (1 << 10)
0182 /* Extended status bits for the ST Micro variants */
0183 #define MCI_ST_SDIOITC      (1 << 22)
0184 #define MCI_ST_CEATAENDC    (1 << 23)
0185 #define MCI_ST_BUSYENDC     (1 << 24)
0186 /* Extended clear bits for the STM32 variants */
0187 #define MCI_STM32_VSWENDC   BIT(25)
0188 #define MCI_STM32_CKSTOPC   BIT(26)
0189 
0190 #define MMCIMASK0       0x03c
0191 #define MCI_CMDCRCFAILMASK  (1 << 0)
0192 #define MCI_DATACRCFAILMASK (1 << 1)
0193 #define MCI_CMDTIMEOUTMASK  (1 << 2)
0194 #define MCI_DATATIMEOUTMASK (1 << 3)
0195 #define MCI_TXUNDERRUNMASK  (1 << 4)
0196 #define MCI_RXOVERRUNMASK   (1 << 5)
0197 #define MCI_CMDRESPENDMASK  (1 << 6)
0198 #define MCI_CMDSENTMASK     (1 << 7)
0199 #define MCI_DATAENDMASK     (1 << 8)
0200 #define MCI_STARTBITERRMASK (1 << 9)
0201 #define MCI_DATABLOCKENDMASK    (1 << 10)
0202 #define MCI_CMDACTIVEMASK   (1 << 11)
0203 #define MCI_TXACTIVEMASK    (1 << 12)
0204 #define MCI_RXACTIVEMASK    (1 << 13)
0205 #define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
0206 #define MCI_RXFIFOHALFFULLMASK  (1 << 15)
0207 #define MCI_TXFIFOFULLMASK  (1 << 16)
0208 #define MCI_RXFIFOFULLMASK  (1 << 17)
0209 #define MCI_TXFIFOEMPTYMASK (1 << 18)
0210 #define MCI_RXFIFOEMPTYMASK (1 << 19)
0211 #define MCI_TXDATAAVLBLMASK (1 << 20)
0212 #define MCI_RXDATAAVLBLMASK (1 << 21)
0213 /* Extended status bits for the ST Micro variants */
0214 #define MCI_ST_SDIOITMASK   (1 << 22)
0215 #define MCI_ST_CEATAENDMASK (1 << 23)
0216 #define MCI_ST_BUSYENDMASK  (1 << 24)
0217 /* Extended status bits for the STM32 variants */
0218 #define MCI_STM32_BUSYD0ENDMASK BIT(21)
0219 
0220 #define MMCIMASK1       0x040
0221 #define MMCIFIFOCNT     0x048
0222 #define MMCIFIFO        0x080 /* to 0x0bc */
0223 
0224 /* STM32 sdmmc registers for IDMA (Internal DMA) */
0225 #define MMCI_STM32_IDMACTRLR    0x050
0226 #define MMCI_STM32_IDMAEN   BIT(0)
0227 #define MMCI_STM32_IDMALLIEN    BIT(1)
0228 
0229 #define MMCI_STM32_IDMABSIZER       0x054
0230 #define MMCI_STM32_IDMABNDT_SHIFT   5
0231 #define MMCI_STM32_IDMABNDT_MASK    GENMASK(12, 5)
0232 
0233 #define MMCI_STM32_IDMABASE0R   0x058
0234 
0235 #define MMCI_STM32_IDMALAR  0x64
0236 #define MMCI_STM32_IDMALA_MASK  GENMASK(13, 0)
0237 #define MMCI_STM32_ABR      BIT(29)
0238 #define MMCI_STM32_ULS      BIT(30)
0239 #define MMCI_STM32_ULA      BIT(31)
0240 
0241 #define MMCI_STM32_IDMABAR  0x68
0242 
0243 #define MCI_IRQENABLE   \
0244     (MCI_CMDCRCFAILMASK | MCI_DATACRCFAILMASK | MCI_CMDTIMEOUTMASK | \
0245     MCI_DATATIMEOUTMASK | MCI_TXUNDERRUNMASK | MCI_RXOVERRUNMASK |  \
0246     MCI_CMDRESPENDMASK | MCI_CMDSENTMASK)
0247 
0248 /* These interrupts are directed to IRQ1 when two IRQ lines are available */
0249 #define MCI_IRQ_PIO_MASK \
0250     (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
0251      MCI_TXFIFOHALFEMPTYMASK)
0252 
0253 #define MCI_IRQ_PIO_STM32_MASK \
0254     (MCI_RXFIFOHALFFULLMASK | MCI_TXFIFOHALFEMPTYMASK)
0255 
0256 #define NR_SG       128
0257 
0258 #define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
0259 
0260 struct clk;
0261 struct dma_chan;
0262 struct mmci_host;
0263 
0264 /**
0265  * struct variant_data - MMCI variant-specific quirks
0266  * @clkreg: default value for MCICLOCK register
0267  * @clkreg_enable: enable value for MMCICLOCK register
0268  * @clkreg_8bit_bus_enable: enable value for 8 bit bus
0269  * @clkreg_neg_edge_enable: enable value for inverted data/cmd output
0270  * @cmdreg_cpsm_enable: enable value for CPSM
0271  * @cmdreg_lrsp_crc: enable value for long response with crc
0272  * @cmdreg_srsp_crc: enable value for short response with crc
0273  * @cmdreg_srsp: enable value for short response without crc
0274  * @cmdreg_stop: enable value for stop and abort transmission
0275  * @datalength_bits: number of bits in the MMCIDATALENGTH register
0276  * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
0277  *        is asserted (likewise for RX)
0278  * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
0279  *        is asserted (likewise for RX)
0280  * @data_cmd_enable: enable value for data commands.
0281  * @st_sdio: enable ST specific SDIO logic
0282  * @st_clkdiv: true if using a ST-specific clock divider algorithm
0283  * @stm32_clkdiv: true if using a STM32-specific clock divider algorithm
0284  * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.
0285  * @datactrl_mask_sdio: SDIO enable mask in datactrl register
0286  * @datactrl_blocksz: block size in power of two
0287  * @datactrl_any_blocksz: true if block any block sizes are accepted by
0288  *        hardware, such as with some SDIO traffic that send
0289  *        odd packets.
0290  * @dma_power_of_2: DMA only works with blocks that are a power of 2.
0291  * @datactrl_first: true if data must be setup before send command
0292  * @datacnt_useless: true if you could not use datacnt register to read
0293  *           remaining data
0294  * @pwrreg_powerup: power up value for MMCIPOWER register
0295  * @f_max: maximum clk frequency supported by the controller.
0296  * @signal_direction: input/out direction of bus signals can be indicated
0297  * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock
0298  * @busy_detect: true if the variant supports busy detection on DAT0.
0299  * @busy_timeout: true if the variant starts data timer when the DPSM
0300  *        enter in Wait_R or Busy state.
0301  * @busy_dpsm_flag: bitmask enabling busy detection in the DPSM
0302  * @busy_detect_flag: bitmask identifying the bit in the MMCISTATUS register
0303  *            indicating that the card is busy
0304  * @busy_detect_mask: bitmask identifying the bit in the MMCIMASK0 to mask for
0305  *            getting busy end detection interrupts
0306  * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply
0307  * @explicit_mclk_control: enable explicit mclk control in driver.
0308  * @qcom_fifo: enables qcom specific fifo pio read logic.
0309  * @qcom_dml: enables qcom specific dma glue for dma transfers.
0310  * @reversed_irq_handling: handle data irq before cmd irq.
0311  * @mmcimask1: true if variant have a MMCIMASK1 register.
0312  * @irq_pio_mask: bitmask used to manage interrupt pio transfert in mmcimask
0313  *        register
0314  * @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS
0315  *         register.
0316  * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
0317  * @dma_lli: true if variant has dma link list feature.
0318  * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
0319  */
0320 struct variant_data {
0321     unsigned int        clkreg;
0322     unsigned int        clkreg_enable;
0323     unsigned int        clkreg_8bit_bus_enable;
0324     unsigned int        clkreg_neg_edge_enable;
0325     unsigned int        cmdreg_cpsm_enable;
0326     unsigned int        cmdreg_lrsp_crc;
0327     unsigned int        cmdreg_srsp_crc;
0328     unsigned int        cmdreg_srsp;
0329     unsigned int        cmdreg_stop;
0330     unsigned int        datalength_bits;
0331     unsigned int        fifosize;
0332     unsigned int        fifohalfsize;
0333     unsigned int        data_cmd_enable;
0334     unsigned int        datactrl_mask_ddrmode;
0335     unsigned int        datactrl_mask_sdio;
0336     unsigned int        datactrl_blocksz;
0337     u8          datactrl_any_blocksz:1;
0338     u8          dma_power_of_2:1;
0339     u8          datactrl_first:1;
0340     u8          datacnt_useless:1;
0341     u8          st_sdio:1;
0342     u8          st_clkdiv:1;
0343     u8          stm32_clkdiv:1;
0344     u32         pwrreg_powerup;
0345     u32         f_max;
0346     u8          signal_direction:1;
0347     u8          pwrreg_clkgate:1;
0348     u8          busy_detect:1;
0349     u8          busy_timeout:1;
0350     u32         busy_dpsm_flag;
0351     u32         busy_detect_flag;
0352     u32         busy_detect_mask;
0353     u8          pwrreg_nopower:1;
0354     u8          explicit_mclk_control:1;
0355     u8          qcom_fifo:1;
0356     u8          qcom_dml:1;
0357     u8          reversed_irq_handling:1;
0358     u8          mmcimask1:1;
0359     unsigned int        irq_pio_mask;
0360     u32         start_err;
0361     u32         opendrain;
0362     u8          dma_lli:1;
0363     u32         stm32_idmabsize_mask;
0364     void (*init)(struct mmci_host *host);
0365 };
0366 
0367 /* mmci variant callbacks */
0368 struct mmci_host_ops {
0369     int (*validate_data)(struct mmci_host *host, struct mmc_data *data);
0370     int (*prep_data)(struct mmci_host *host, struct mmc_data *data,
0371              bool next);
0372     void (*unprep_data)(struct mmci_host *host, struct mmc_data *data,
0373                 int err);
0374     u32 (*get_datactrl_cfg)(struct mmci_host *host);
0375     void (*get_next_data)(struct mmci_host *host, struct mmc_data *data);
0376     int (*dma_setup)(struct mmci_host *host);
0377     void (*dma_release)(struct mmci_host *host);
0378     int (*dma_start)(struct mmci_host *host, unsigned int *datactrl);
0379     void (*dma_finalize)(struct mmci_host *host, struct mmc_data *data);
0380     void (*dma_error)(struct mmci_host *host);
0381     void (*set_clkreg)(struct mmci_host *host, unsigned int desired);
0382     void (*set_pwrreg)(struct mmci_host *host, unsigned int pwr);
0383     bool (*busy_complete)(struct mmci_host *host, u32 status, u32 err_msk);
0384     void (*pre_sig_volt_switch)(struct mmci_host *host);
0385     int (*post_sig_volt_switch)(struct mmci_host *host, struct mmc_ios *ios);
0386 };
0387 
0388 struct mmci_host {
0389     phys_addr_t     phybase;
0390     void __iomem        *base;
0391     struct mmc_request  *mrq;
0392     struct mmc_command  *cmd;
0393     struct mmc_command  stop_abort;
0394     struct mmc_data     *data;
0395     struct mmc_host     *mmc;
0396     struct clk      *clk;
0397     u8          singleirq:1;
0398 
0399     struct reset_control    *rst;
0400 
0401     spinlock_t      lock;
0402 
0403     unsigned int        mclk;
0404     /* cached value of requested clk in set_ios */
0405     unsigned int        clock_cache;
0406     unsigned int        cclk;
0407     u32         pwr_reg;
0408     u32         pwr_reg_add;
0409     u32         clk_reg;
0410     u32         clk_reg_add;
0411     u32         datactrl_reg;
0412     u32         busy_status;
0413     u32         mask1_reg;
0414     u8          vqmmc_enabled:1;
0415     struct mmci_platform_data *plat;
0416     struct mmc_host_ops *mmc_ops;
0417     struct mmci_host_ops    *ops;
0418     struct variant_data *variant;
0419     void            *variant_priv;
0420     struct pinctrl      *pinctrl;
0421     struct pinctrl_state    *pins_opendrain;
0422 
0423     u8          hw_designer;
0424     u8          hw_revision:4;
0425 
0426     struct timer_list   timer;
0427     unsigned int        oldstat;
0428     u32         irq_action;
0429 
0430     /* pio stuff */
0431     struct sg_mapping_iter  sg_miter;
0432     unsigned int        size;
0433     int (*get_rx_fifocnt)(struct mmci_host *h, u32 status, int remain);
0434 
0435     u8          use_dma:1;
0436     u8          dma_in_progress:1;
0437     void            *dma_priv;
0438 
0439     s32         next_cookie;
0440 };
0441 
0442 #define dma_inprogress(host)    ((host)->dma_in_progress)
0443 
0444 void mmci_write_clkreg(struct mmci_host *host, u32 clk);
0445 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr);
0446 
0447 static inline u32 mmci_dctrl_blksz(struct mmci_host *host)
0448 {
0449     return (ffs(host->data->blksz) - 1) << 4;
0450 }
0451 
0452 #ifdef CONFIG_DMA_ENGINE
0453 int mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
0454             bool next);
0455 void mmci_dmae_unprep_data(struct mmci_host *host, struct mmc_data *data,
0456                int err);
0457 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data);
0458 int mmci_dmae_setup(struct mmci_host *host);
0459 void mmci_dmae_release(struct mmci_host *host);
0460 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl);
0461 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data);
0462 void mmci_dmae_error(struct mmci_host *host);
0463 #endif
0464 
0465 #ifdef CONFIG_MMC_QCOM_DML
0466 void qcom_variant_init(struct mmci_host *host);
0467 #else
0468 static inline void qcom_variant_init(struct mmci_host *host) {}
0469 #endif
0470 
0471 #ifdef CONFIG_MMC_STM32_SDMMC
0472 void sdmmc_variant_init(struct mmci_host *host);
0473 #else
0474 static inline void sdmmc_variant_init(struct mmci_host *host) {}
0475 #endif
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