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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * meson-mx-sdio.c - Meson6, Meson8 and Meson8b SDIO/MMC Host Controller
0004  *
0005  * Copyright (C) 2015 Endless Mobile, Inc.
0006  * Author: Carlo Caione <carlo@endlessm.com>
0007  * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
0008  */
0009 
0010 #include <linux/bitfield.h>
0011 #include <linux/clk.h>
0012 #include <linux/clk-provider.h>
0013 #include <linux/delay.h>
0014 #include <linux/device.h>
0015 #include <linux/dma-mapping.h>
0016 #include <linux/module.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/io.h>
0019 #include <linux/ioport.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/of_platform.h>
0022 #include <linux/timer.h>
0023 #include <linux/types.h>
0024 
0025 #include <linux/mmc/host.h>
0026 #include <linux/mmc/mmc.h>
0027 #include <linux/mmc/sdio.h>
0028 #include <linux/mmc/slot-gpio.h>
0029 
0030 #define MESON_MX_SDIO_ARGU                  0x00
0031 
0032 #define MESON_MX_SDIO_SEND                  0x04
0033     #define MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK       GENMASK(7, 0)
0034     #define MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK       GENMASK(15, 8)
0035     #define MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7        BIT(16)
0036     #define MESON_MX_SDIO_SEND_RESP_HAS_DATA        BIT(17)
0037     #define MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8     BIT(18)
0038     #define MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY      BIT(19)
0039     #define MESON_MX_SDIO_SEND_DATA             BIT(20)
0040     #define MESON_MX_SDIO_SEND_USE_INT_WINDOW       BIT(21)
0041     #define MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK    GENMASK(31, 24)
0042 
0043 #define MESON_MX_SDIO_CONF                  0x08
0044     #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT        0
0045     #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH        10
0046     #define MESON_MX_SDIO_CONF_CMD_DISABLE_CRC      BIT(10)
0047     #define MESON_MX_SDIO_CONF_CMD_OUT_AT_POSITIVE_EDGE BIT(11)
0048     #define MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK   GENMASK(17, 12)
0049     #define MESON_MX_SDIO_CONF_RESP_LATCH_AT_NEGATIVE_EDGE  BIT(18)
0050     #define MESON_MX_SDIO_CONF_DATA_LATCH_AT_NEGATIVE_EDGE  BIT(19)
0051     #define MESON_MX_SDIO_CONF_BUS_WIDTH            BIT(20)
0052     #define MESON_MX_SDIO_CONF_M_ENDIAN_MASK        GENMASK(22, 21)
0053     #define MESON_MX_SDIO_CONF_WRITE_NWR_MASK       GENMASK(28, 23)
0054     #define MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK GENMASK(31, 29)
0055 
0056 #define MESON_MX_SDIO_IRQS                  0x0c
0057     #define MESON_MX_SDIO_IRQS_STATUS_STATE_MACHINE_MASK    GENMASK(3, 0)
0058     #define MESON_MX_SDIO_IRQS_CMD_BUSY         BIT(4)
0059     #define MESON_MX_SDIO_IRQS_RESP_CRC7_OK         BIT(5)
0060     #define MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK       BIT(6)
0061     #define MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK      BIT(7)
0062     #define MESON_MX_SDIO_IRQS_IF_INT           BIT(8)
0063     #define MESON_MX_SDIO_IRQS_CMD_INT          BIT(9)
0064     #define MESON_MX_SDIO_IRQS_STATUS_INFO_MASK     GENMASK(15, 12)
0065     #define MESON_MX_SDIO_IRQS_TIMING_OUT_INT       BIT(16)
0066     #define MESON_MX_SDIO_IRQS_AMRISC_TIMING_OUT_INT_EN BIT(17)
0067     #define MESON_MX_SDIO_IRQS_ARC_TIMING_OUT_INT_EN    BIT(18)
0068     #define MESON_MX_SDIO_IRQS_TIMING_OUT_COUNT_MASK    GENMASK(31, 19)
0069 
0070 #define MESON_MX_SDIO_IRQC                  0x10
0071     #define MESON_MX_SDIO_IRQC_ARC_IF_INT_EN        BIT(3)
0072     #define MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN       BIT(4)
0073     #define MESON_MX_SDIO_IRQC_IF_CONFIG_MASK       GENMASK(7, 6)
0074     #define MESON_MX_SDIO_IRQC_FORCE_DATA_CLK       BIT(8)
0075     #define MESON_MX_SDIO_IRQC_FORCE_DATA_CMD       BIT(9)
0076     #define MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK      GENMASK(13, 10)
0077     #define MESON_MX_SDIO_IRQC_SOFT_RESET           BIT(15)
0078     #define MESON_MX_SDIO_IRQC_FORCE_HALT           BIT(30)
0079     #define MESON_MX_SDIO_IRQC_HALT_HOLE            BIT(31)
0080 
0081 #define MESON_MX_SDIO_MULT                  0x14
0082     #define MESON_MX_SDIO_MULT_PORT_SEL_MASK        GENMASK(1, 0)
0083     #define MESON_MX_SDIO_MULT_MEMORY_STICK_ENABLE      BIT(2)
0084     #define MESON_MX_SDIO_MULT_MEMORY_STICK_SCLK_ALWAYS BIT(3)
0085     #define MESON_MX_SDIO_MULT_STREAM_ENABLE        BIT(4)
0086     #define MESON_MX_SDIO_MULT_STREAM_8BITS_MODE        BIT(5)
0087     #define MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX      BIT(8)
0088     #define MESON_MX_SDIO_MULT_DAT0_DAT1_SWAPPED        BIT(10)
0089     #define MESON_MX_SDIO_MULT_DAT1_DAT0_SWAPPED        BIT(11)
0090     #define MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK     GENMASK(15, 12)
0091 
0092 #define MESON_MX_SDIO_ADDR                  0x18
0093 
0094 #define MESON_MX_SDIO_EXT                   0x1c
0095     #define MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK       GENMASK(29, 16)
0096 
0097 #define MESON_MX_SDIO_BOUNCE_REQ_SIZE               (128 * 1024)
0098 #define MESON_MX_SDIO_RESPONSE_CRC16_BITS           (16 - 1)
0099 #define MESON_MX_SDIO_MAX_SLOTS                 3
0100 
0101 struct meson_mx_mmc_host {
0102     struct device           *controller_dev;
0103 
0104     struct clk          *parent_clk;
0105     struct clk          *core_clk;
0106     struct clk_divider      cfg_div;
0107     struct clk          *cfg_div_clk;
0108     struct clk_fixed_factor     fixed_factor;
0109     struct clk          *fixed_factor_clk;
0110 
0111     void __iomem            *base;
0112     int             irq;
0113     spinlock_t          irq_lock;
0114 
0115     struct timer_list       cmd_timeout;
0116 
0117     unsigned int            slot_id;
0118     struct mmc_host         *mmc;
0119 
0120     struct mmc_request      *mrq;
0121     struct mmc_command      *cmd;
0122     int             error;
0123 };
0124 
0125 static void meson_mx_mmc_mask_bits(struct mmc_host *mmc, char reg, u32 mask,
0126                    u32 val)
0127 {
0128     struct meson_mx_mmc_host *host = mmc_priv(mmc);
0129     u32 regval;
0130 
0131     regval = readl(host->base + reg);
0132     regval &= ~mask;
0133     regval |= (val & mask);
0134 
0135     writel(regval, host->base + reg);
0136 }
0137 
0138 static void meson_mx_mmc_soft_reset(struct meson_mx_mmc_host *host)
0139 {
0140     writel(MESON_MX_SDIO_IRQC_SOFT_RESET, host->base + MESON_MX_SDIO_IRQC);
0141     udelay(2);
0142 }
0143 
0144 static struct mmc_command *meson_mx_mmc_get_next_cmd(struct mmc_command *cmd)
0145 {
0146     if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
0147         return cmd->mrq->cmd;
0148     else if (mmc_op_multi(cmd->opcode) &&
0149          (!cmd->mrq->sbc || cmd->error || cmd->data->error))
0150         return cmd->mrq->stop;
0151     else
0152         return NULL;
0153 }
0154 
0155 static void meson_mx_mmc_start_cmd(struct mmc_host *mmc,
0156                    struct mmc_command *cmd)
0157 {
0158     struct meson_mx_mmc_host *host = mmc_priv(mmc);
0159     unsigned int pack_size;
0160     unsigned long irqflags, timeout;
0161     u32 mult, send = 0, ext = 0;
0162 
0163     host->cmd = cmd;
0164 
0165     if (cmd->busy_timeout)
0166         timeout = msecs_to_jiffies(cmd->busy_timeout);
0167     else
0168         timeout = msecs_to_jiffies(1000);
0169 
0170     switch (mmc_resp_type(cmd)) {
0171     case MMC_RSP_R1:
0172     case MMC_RSP_R1B:
0173     case MMC_RSP_R3:
0174         /* 7 (CMD) + 32 (response) + 7 (CRC) -1 */
0175         send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 45);
0176         break;
0177     case MMC_RSP_R2:
0178         /* 7 (CMD) + 120 (response) + 7 (CRC) -1 */
0179         send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 133);
0180         send |= MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8;
0181         break;
0182     default:
0183         break;
0184     }
0185 
0186     if (!(cmd->flags & MMC_RSP_CRC))
0187         send |= MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7;
0188 
0189     if (cmd->flags & MMC_RSP_BUSY)
0190         send |= MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY;
0191 
0192     if (cmd->data) {
0193         send |= FIELD_PREP(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK,
0194                    (cmd->data->blocks - 1));
0195 
0196         pack_size = cmd->data->blksz * BITS_PER_BYTE;
0197         if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
0198             pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 4;
0199         else
0200             pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 1;
0201 
0202         ext |= FIELD_PREP(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK,
0203                   pack_size);
0204 
0205         if (cmd->data->flags & MMC_DATA_WRITE)
0206             send |= MESON_MX_SDIO_SEND_DATA;
0207         else
0208             send |= MESON_MX_SDIO_SEND_RESP_HAS_DATA;
0209 
0210         cmd->data->bytes_xfered = 0;
0211     }
0212 
0213     send |= FIELD_PREP(MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK,
0214                (0x40 | cmd->opcode));
0215 
0216     spin_lock_irqsave(&host->irq_lock, irqflags);
0217 
0218     mult = readl(host->base + MESON_MX_SDIO_MULT);
0219     mult &= ~MESON_MX_SDIO_MULT_PORT_SEL_MASK;
0220     mult |= FIELD_PREP(MESON_MX_SDIO_MULT_PORT_SEL_MASK, host->slot_id);
0221     mult |= BIT(31);
0222     writel(mult, host->base + MESON_MX_SDIO_MULT);
0223 
0224     /* enable the CMD done interrupt */
0225     meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQC,
0226                    MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN,
0227                    MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN);
0228 
0229     /* clear pending interrupts */
0230     meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQS,
0231                    MESON_MX_SDIO_IRQS_CMD_INT,
0232                    MESON_MX_SDIO_IRQS_CMD_INT);
0233 
0234     writel(cmd->arg, host->base + MESON_MX_SDIO_ARGU);
0235     writel(ext, host->base + MESON_MX_SDIO_EXT);
0236     writel(send, host->base + MESON_MX_SDIO_SEND);
0237 
0238     spin_unlock_irqrestore(&host->irq_lock, irqflags);
0239 
0240     mod_timer(&host->cmd_timeout, jiffies + timeout);
0241 }
0242 
0243 static void meson_mx_mmc_request_done(struct meson_mx_mmc_host *host)
0244 {
0245     struct mmc_request *mrq;
0246 
0247     mrq = host->mrq;
0248 
0249     if (host->cmd->error)
0250         meson_mx_mmc_soft_reset(host);
0251 
0252     host->mrq = NULL;
0253     host->cmd = NULL;
0254 
0255     mmc_request_done(host->mmc, mrq);
0256 }
0257 
0258 static void meson_mx_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0259 {
0260     struct meson_mx_mmc_host *host = mmc_priv(mmc);
0261     unsigned short vdd = ios->vdd;
0262     unsigned long clk_rate = ios->clock;
0263 
0264     switch (ios->bus_width) {
0265     case MMC_BUS_WIDTH_1:
0266         meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF,
0267                        MESON_MX_SDIO_CONF_BUS_WIDTH, 0);
0268         break;
0269 
0270     case MMC_BUS_WIDTH_4:
0271         meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF,
0272                        MESON_MX_SDIO_CONF_BUS_WIDTH,
0273                        MESON_MX_SDIO_CONF_BUS_WIDTH);
0274         break;
0275 
0276     case MMC_BUS_WIDTH_8:
0277     default:
0278         dev_err(mmc_dev(mmc), "unsupported bus width: %d\n",
0279             ios->bus_width);
0280         host->error = -EINVAL;
0281         return;
0282     }
0283 
0284     host->error = clk_set_rate(host->cfg_div_clk, ios->clock);
0285     if (host->error) {
0286         dev_warn(mmc_dev(mmc),
0287                 "failed to set MMC clock to %lu: %d\n",
0288                 clk_rate, host->error);
0289         return;
0290     }
0291 
0292     mmc->actual_clock = clk_get_rate(host->cfg_div_clk);
0293 
0294     switch (ios->power_mode) {
0295     case MMC_POWER_OFF:
0296         vdd = 0;
0297         fallthrough;
0298     case MMC_POWER_UP:
0299         if (!IS_ERR(mmc->supply.vmmc)) {
0300             host->error = mmc_regulator_set_ocr(mmc,
0301                                 mmc->supply.vmmc,
0302                                 vdd);
0303             if (host->error)
0304                 return;
0305         }
0306         break;
0307     }
0308 }
0309 
0310 static int meson_mx_mmc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq)
0311 {
0312     struct mmc_data *data = mrq->data;
0313     int dma_len;
0314     struct scatterlist *sg;
0315 
0316     if (!data)
0317         return 0;
0318 
0319     sg = data->sg;
0320     if (sg->offset & 3 || sg->length & 3) {
0321         dev_err(mmc_dev(mmc),
0322             "unaligned scatterlist: offset %x length %d\n",
0323             sg->offset, sg->length);
0324         return -EINVAL;
0325     }
0326 
0327     dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
0328                  mmc_get_dma_dir(data));
0329     if (dma_len <= 0) {
0330         dev_err(mmc_dev(mmc), "dma_map_sg failed\n");
0331         return -ENOMEM;
0332     }
0333 
0334     return 0;
0335 }
0336 
0337 static void meson_mx_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
0338 {
0339     struct meson_mx_mmc_host *host = mmc_priv(mmc);
0340     struct mmc_command *cmd = mrq->cmd;
0341 
0342     if (!host->error)
0343         host->error = meson_mx_mmc_map_dma(mmc, mrq);
0344 
0345     if (host->error) {
0346         cmd->error = host->error;
0347         mmc_request_done(mmc, mrq);
0348         return;
0349     }
0350 
0351     host->mrq = mrq;
0352 
0353     if (mrq->data)
0354         writel(sg_dma_address(mrq->data->sg),
0355                host->base + MESON_MX_SDIO_ADDR);
0356 
0357     if (mrq->sbc)
0358         meson_mx_mmc_start_cmd(mmc, mrq->sbc);
0359     else
0360         meson_mx_mmc_start_cmd(mmc, mrq->cmd);
0361 }
0362 
0363 static void meson_mx_mmc_read_response(struct mmc_host *mmc,
0364                        struct mmc_command *cmd)
0365 {
0366     struct meson_mx_mmc_host *host = mmc_priv(mmc);
0367     u32 mult;
0368     int i, resp[4];
0369 
0370     mult = readl(host->base + MESON_MX_SDIO_MULT);
0371     mult |= MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX;
0372     mult &= ~MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK;
0373     mult |= FIELD_PREP(MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK, 0);
0374     writel(mult, host->base + MESON_MX_SDIO_MULT);
0375 
0376     if (cmd->flags & MMC_RSP_136) {
0377         for (i = 0; i <= 3; i++)
0378             resp[3 - i] = readl(host->base + MESON_MX_SDIO_ARGU);
0379         cmd->resp[0] = (resp[0] << 8) | ((resp[1] >> 24) & 0xff);
0380         cmd->resp[1] = (resp[1] << 8) | ((resp[2] >> 24) & 0xff);
0381         cmd->resp[2] = (resp[2] << 8) | ((resp[3] >> 24) & 0xff);
0382         cmd->resp[3] = (resp[3] << 8);
0383     } else if (cmd->flags & MMC_RSP_PRESENT) {
0384         cmd->resp[0] = readl(host->base + MESON_MX_SDIO_ARGU);
0385     }
0386 }
0387 
0388 static irqreturn_t meson_mx_mmc_process_cmd_irq(struct meson_mx_mmc_host *host,
0389                         u32 irqs, u32 send)
0390 {
0391     struct mmc_command *cmd = host->cmd;
0392 
0393     /*
0394      * NOTE: even though it shouldn't happen we sometimes get command
0395      * interrupts twice (at least this is what it looks like). Ideally
0396      * we find out why this happens and warn here as soon as it occurs.
0397      */
0398     if (!cmd)
0399         return IRQ_HANDLED;
0400 
0401     cmd->error = 0;
0402     meson_mx_mmc_read_response(host->mmc, cmd);
0403 
0404     if (cmd->data) {
0405         if (!((irqs & MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK) ||
0406               (irqs & MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK)))
0407             cmd->error = -EILSEQ;
0408     } else {
0409         if (!((irqs & MESON_MX_SDIO_IRQS_RESP_CRC7_OK) ||
0410               (send & MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7)))
0411             cmd->error = -EILSEQ;
0412     }
0413 
0414     return IRQ_WAKE_THREAD;
0415 }
0416 
0417 static irqreturn_t meson_mx_mmc_irq(int irq, void *data)
0418 {
0419     struct meson_mx_mmc_host *host = (void *) data;
0420     u32 irqs, send;
0421     irqreturn_t ret;
0422 
0423     spin_lock(&host->irq_lock);
0424 
0425     irqs = readl(host->base + MESON_MX_SDIO_IRQS);
0426     send = readl(host->base + MESON_MX_SDIO_SEND);
0427 
0428     if (irqs & MESON_MX_SDIO_IRQS_CMD_INT)
0429         ret = meson_mx_mmc_process_cmd_irq(host, irqs, send);
0430     else
0431         ret = IRQ_HANDLED;
0432 
0433     /* finally ACK all pending interrupts */
0434     writel(irqs, host->base + MESON_MX_SDIO_IRQS);
0435 
0436     spin_unlock(&host->irq_lock);
0437 
0438     return ret;
0439 }
0440 
0441 static irqreturn_t meson_mx_mmc_irq_thread(int irq, void *irq_data)
0442 {
0443     struct meson_mx_mmc_host *host = (void *) irq_data;
0444     struct mmc_command *cmd = host->cmd, *next_cmd;
0445 
0446     if (WARN_ON(!cmd))
0447         return IRQ_HANDLED;
0448 
0449     del_timer_sync(&host->cmd_timeout);
0450 
0451     if (cmd->data) {
0452         dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg,
0453                 cmd->data->sg_len,
0454                 mmc_get_dma_dir(cmd->data));
0455 
0456         cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks;
0457     }
0458 
0459     next_cmd = meson_mx_mmc_get_next_cmd(cmd);
0460     if (next_cmd)
0461         meson_mx_mmc_start_cmd(host->mmc, next_cmd);
0462     else
0463         meson_mx_mmc_request_done(host);
0464 
0465     return IRQ_HANDLED;
0466 }
0467 
0468 static void meson_mx_mmc_timeout(struct timer_list *t)
0469 {
0470     struct meson_mx_mmc_host *host = from_timer(host, t, cmd_timeout);
0471     unsigned long irqflags;
0472     u32 irqc;
0473 
0474     spin_lock_irqsave(&host->irq_lock, irqflags);
0475 
0476     /* disable the CMD interrupt */
0477     irqc = readl(host->base + MESON_MX_SDIO_IRQC);
0478     irqc &= ~MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN;
0479     writel(irqc, host->base + MESON_MX_SDIO_IRQC);
0480 
0481     spin_unlock_irqrestore(&host->irq_lock, irqflags);
0482 
0483     /*
0484      * skip the timeout handling if the interrupt handler already processed
0485      * the command.
0486      */
0487     if (!host->cmd)
0488         return;
0489 
0490     dev_dbg(mmc_dev(host->mmc),
0491         "Timeout on CMD%u (IRQS = 0x%08x, ARGU = 0x%08x)\n",
0492         host->cmd->opcode, readl(host->base + MESON_MX_SDIO_IRQS),
0493         readl(host->base + MESON_MX_SDIO_ARGU));
0494 
0495     host->cmd->error = -ETIMEDOUT;
0496 
0497     meson_mx_mmc_request_done(host);
0498 }
0499 
0500 static struct mmc_host_ops meson_mx_mmc_ops = {
0501     .request        = meson_mx_mmc_request,
0502     .set_ios        = meson_mx_mmc_set_ios,
0503     .get_cd         = mmc_gpio_get_cd,
0504     .get_ro         = mmc_gpio_get_ro,
0505 };
0506 
0507 static struct platform_device *meson_mx_mmc_slot_pdev(struct device *parent)
0508 {
0509     struct device_node *slot_node;
0510     struct platform_device *pdev;
0511 
0512     /*
0513      * TODO: the MMC core framework currently does not support
0514      * controllers with multiple slots properly. So we only register
0515      * the first slot for now
0516      */
0517     slot_node = of_get_compatible_child(parent->of_node, "mmc-slot");
0518     if (!slot_node) {
0519         dev_warn(parent, "no 'mmc-slot' sub-node found\n");
0520         return ERR_PTR(-ENOENT);
0521     }
0522 
0523     pdev = of_platform_device_create(slot_node, NULL, parent);
0524     of_node_put(slot_node);
0525 
0526     return pdev;
0527 }
0528 
0529 static int meson_mx_mmc_add_host(struct meson_mx_mmc_host *host)
0530 {
0531     struct mmc_host *mmc = host->mmc;
0532     struct device *slot_dev = mmc_dev(mmc);
0533     int ret;
0534 
0535     if (of_property_read_u32(slot_dev->of_node, "reg", &host->slot_id)) {
0536         dev_err(slot_dev, "missing 'reg' property\n");
0537         return -EINVAL;
0538     }
0539 
0540     if (host->slot_id >= MESON_MX_SDIO_MAX_SLOTS) {
0541         dev_err(slot_dev, "invalid 'reg' property value %d\n",
0542             host->slot_id);
0543         return -EINVAL;
0544     }
0545 
0546     /* Get regulators and the supported OCR mask */
0547     ret = mmc_regulator_get_supply(mmc);
0548     if (ret)
0549         return ret;
0550 
0551     mmc->max_req_size = MESON_MX_SDIO_BOUNCE_REQ_SIZE;
0552     mmc->max_seg_size = mmc->max_req_size;
0553     mmc->max_blk_count =
0554         FIELD_GET(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK,
0555               0xffffffff);
0556     mmc->max_blk_size = FIELD_GET(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK,
0557                       0xffffffff);
0558     mmc->max_blk_size -= (4 * MESON_MX_SDIO_RESPONSE_CRC16_BITS);
0559     mmc->max_blk_size /= BITS_PER_BYTE;
0560 
0561     /* Get the min and max supported clock rates */
0562     mmc->f_min = clk_round_rate(host->cfg_div_clk, 1);
0563     mmc->f_max = clk_round_rate(host->cfg_div_clk,
0564                     clk_get_rate(host->parent_clk));
0565 
0566     mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY;
0567     mmc->ops = &meson_mx_mmc_ops;
0568 
0569     ret = mmc_of_parse(mmc);
0570     if (ret)
0571         return ret;
0572 
0573     ret = mmc_add_host(mmc);
0574     if (ret)
0575         return ret;
0576 
0577     return 0;
0578 }
0579 
0580 static int meson_mx_mmc_register_clks(struct meson_mx_mmc_host *host)
0581 {
0582     struct clk_init_data init;
0583     const char *clk_div_parent, *clk_fixed_factor_parent;
0584 
0585     clk_fixed_factor_parent = __clk_get_name(host->parent_clk);
0586     init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL,
0587                    "%s#fixed_factor",
0588                    dev_name(host->controller_dev));
0589     if (!init.name)
0590         return -ENOMEM;
0591 
0592     init.ops = &clk_fixed_factor_ops;
0593     init.flags = 0;
0594     init.parent_names = &clk_fixed_factor_parent;
0595     init.num_parents = 1;
0596     host->fixed_factor.div = 2;
0597     host->fixed_factor.mult = 1;
0598     host->fixed_factor.hw.init = &init;
0599 
0600     host->fixed_factor_clk = devm_clk_register(host->controller_dev,
0601                          &host->fixed_factor.hw);
0602     if (WARN_ON(IS_ERR(host->fixed_factor_clk)))
0603         return PTR_ERR(host->fixed_factor_clk);
0604 
0605     clk_div_parent = __clk_get_name(host->fixed_factor_clk);
0606     init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL,
0607                    "%s#div", dev_name(host->controller_dev));
0608     if (!init.name)
0609         return -ENOMEM;
0610 
0611     init.ops = &clk_divider_ops;
0612     init.flags = CLK_SET_RATE_PARENT;
0613     init.parent_names = &clk_div_parent;
0614     init.num_parents = 1;
0615     host->cfg_div.reg = host->base + MESON_MX_SDIO_CONF;
0616     host->cfg_div.shift = MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT;
0617     host->cfg_div.width = MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH;
0618     host->cfg_div.hw.init = &init;
0619     host->cfg_div.flags = CLK_DIVIDER_ALLOW_ZERO;
0620 
0621     host->cfg_div_clk = devm_clk_register(host->controller_dev,
0622                           &host->cfg_div.hw);
0623     if (WARN_ON(IS_ERR(host->cfg_div_clk)))
0624         return PTR_ERR(host->cfg_div_clk);
0625 
0626     return 0;
0627 }
0628 
0629 static int meson_mx_mmc_probe(struct platform_device *pdev)
0630 {
0631     struct platform_device *slot_pdev;
0632     struct mmc_host *mmc;
0633     struct meson_mx_mmc_host *host;
0634     int ret, irq;
0635     u32 conf;
0636 
0637     slot_pdev = meson_mx_mmc_slot_pdev(&pdev->dev);
0638     if (!slot_pdev)
0639         return -ENODEV;
0640     else if (IS_ERR(slot_pdev))
0641         return PTR_ERR(slot_pdev);
0642 
0643     mmc = mmc_alloc_host(sizeof(*host), &slot_pdev->dev);
0644     if (!mmc) {
0645         ret = -ENOMEM;
0646         goto error_unregister_slot_pdev;
0647     }
0648 
0649     host = mmc_priv(mmc);
0650     host->mmc = mmc;
0651     host->controller_dev = &pdev->dev;
0652 
0653     spin_lock_init(&host->irq_lock);
0654     timer_setup(&host->cmd_timeout, meson_mx_mmc_timeout, 0);
0655 
0656     platform_set_drvdata(pdev, host);
0657 
0658     host->base = devm_platform_ioremap_resource(pdev, 0);
0659     if (IS_ERR(host->base)) {
0660         ret = PTR_ERR(host->base);
0661         goto error_free_mmc;
0662     }
0663 
0664     irq = platform_get_irq(pdev, 0);
0665     if (irq < 0) {
0666         ret = irq;
0667         goto error_free_mmc;
0668     }
0669 
0670     ret = devm_request_threaded_irq(host->controller_dev, irq,
0671                     meson_mx_mmc_irq,
0672                     meson_mx_mmc_irq_thread, IRQF_ONESHOT,
0673                     NULL, host);
0674     if (ret)
0675         goto error_free_mmc;
0676 
0677     host->core_clk = devm_clk_get(host->controller_dev, "core");
0678     if (IS_ERR(host->core_clk)) {
0679         ret = PTR_ERR(host->core_clk);
0680         goto error_free_mmc;
0681     }
0682 
0683     host->parent_clk = devm_clk_get(host->controller_dev, "clkin");
0684     if (IS_ERR(host->parent_clk)) {
0685         ret = PTR_ERR(host->parent_clk);
0686         goto error_free_mmc;
0687     }
0688 
0689     ret = meson_mx_mmc_register_clks(host);
0690     if (ret)
0691         goto error_free_mmc;
0692 
0693     ret = clk_prepare_enable(host->core_clk);
0694     if (ret) {
0695         dev_err(host->controller_dev, "Failed to enable core clock\n");
0696         goto error_free_mmc;
0697     }
0698 
0699     ret = clk_prepare_enable(host->cfg_div_clk);
0700     if (ret) {
0701         dev_err(host->controller_dev, "Failed to enable MMC clock\n");
0702         goto error_disable_core_clk;
0703     }
0704 
0705     conf = 0;
0706     conf |= FIELD_PREP(MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK, 39);
0707     conf |= FIELD_PREP(MESON_MX_SDIO_CONF_M_ENDIAN_MASK, 0x3);
0708     conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_NWR_MASK, 0x2);
0709     conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK, 0x2);
0710     writel(conf, host->base + MESON_MX_SDIO_CONF);
0711 
0712     meson_mx_mmc_soft_reset(host);
0713 
0714     ret = meson_mx_mmc_add_host(host);
0715     if (ret)
0716         goto error_disable_clks;
0717 
0718     return 0;
0719 
0720 error_disable_clks:
0721     clk_disable_unprepare(host->cfg_div_clk);
0722 error_disable_core_clk:
0723     clk_disable_unprepare(host->core_clk);
0724 error_free_mmc:
0725     mmc_free_host(mmc);
0726 error_unregister_slot_pdev:
0727     of_platform_device_destroy(&slot_pdev->dev, NULL);
0728     return ret;
0729 }
0730 
0731 static int meson_mx_mmc_remove(struct platform_device *pdev)
0732 {
0733     struct meson_mx_mmc_host *host = platform_get_drvdata(pdev);
0734     struct device *slot_dev = mmc_dev(host->mmc);
0735 
0736     del_timer_sync(&host->cmd_timeout);
0737 
0738     mmc_remove_host(host->mmc);
0739 
0740     of_platform_device_destroy(slot_dev, NULL);
0741 
0742     clk_disable_unprepare(host->cfg_div_clk);
0743     clk_disable_unprepare(host->core_clk);
0744 
0745     mmc_free_host(host->mmc);
0746 
0747     return 0;
0748 }
0749 
0750 static const struct of_device_id meson_mx_mmc_of_match[] = {
0751     { .compatible = "amlogic,meson8-sdio", },
0752     { .compatible = "amlogic,meson8b-sdio", },
0753     { /* sentinel */ }
0754 };
0755 MODULE_DEVICE_TABLE(of, meson_mx_mmc_of_match);
0756 
0757 static struct platform_driver meson_mx_mmc_driver = {
0758     .probe   = meson_mx_mmc_probe,
0759     .remove  = meson_mx_mmc_remove,
0760     .driver  = {
0761         .name = "meson-mx-sdio",
0762         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0763         .of_match_table = of_match_ptr(meson_mx_mmc_of_match),
0764     },
0765 };
0766 
0767 module_platform_driver(meson_mx_mmc_driver);
0768 
0769 MODULE_DESCRIPTION("Meson6, Meson8 and Meson8b SDIO/MMC Host Driver");
0770 MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");
0771 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
0772 MODULE_LICENSE("GPL v2");
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