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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Amlogic Meson6/Meson8/Meson8b/Meson8m2 SDHC MMC host controller driver.
0004  *
0005  * Copyright (C) 2020 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/device.h>
0010 #include <linux/dma-mapping.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/iopoll.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/property.h>
0017 #include <linux/regmap.h>
0018 #include <linux/regulator/consumer.h>
0019 #include <linux/types.h>
0020 
0021 #include <linux/mmc/host.h>
0022 #include <linux/mmc/mmc.h>
0023 #include <linux/mmc/sdio.h>
0024 #include <linux/mmc/slot-gpio.h>
0025 
0026 #include "meson-mx-sdhc.h"
0027 
0028 #define MESON_SDHC_NUM_BULK_CLKS                4
0029 #define MESON_SDHC_MAX_BLK_SIZE                 512
0030 #define MESON_SDHC_NUM_TUNING_TRIES             10
0031 
0032 #define MESON_SDHC_WAIT_CMD_READY_SLEEP_US          1
0033 #define MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US            100000
0034 #define MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US            1
0035 #define MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US          200
0036 
0037 struct meson_mx_sdhc_data {
0038     void        (*init_hw)(struct mmc_host *mmc);
0039     void        (*set_pdma)(struct mmc_host *mmc);
0040     void        (*wait_before_send)(struct mmc_host *mmc);
0041     bool        hardware_flush_all_cmds;
0042 };
0043 
0044 struct meson_mx_sdhc_host {
0045     struct mmc_host         *mmc;
0046 
0047     struct mmc_request      *mrq;
0048     struct mmc_command      *cmd;
0049     int             error;
0050 
0051     struct regmap           *regmap;
0052 
0053     struct clk          *pclk;
0054     struct clk          *sd_clk;
0055     struct clk_bulk_data        bulk_clks[MESON_SDHC_NUM_BULK_CLKS];
0056     bool                bulk_clks_enabled;
0057 
0058     const struct meson_mx_sdhc_data *platform;
0059 };
0060 
0061 static const struct regmap_config meson_mx_sdhc_regmap_config = {
0062     .reg_bits = 8,
0063     .val_bits = 32,
0064     .reg_stride = 4,
0065     .max_register = MESON_SDHC_CLK2,
0066 };
0067 
0068 static void meson_mx_sdhc_hw_reset(struct mmc_host *mmc)
0069 {
0070     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0071 
0072     regmap_write(host->regmap, MESON_SDHC_SRST, MESON_SDHC_SRST_MAIN_CTRL |
0073              MESON_SDHC_SRST_RXFIFO | MESON_SDHC_SRST_TXFIFO |
0074              MESON_SDHC_SRST_DPHY_RX | MESON_SDHC_SRST_DPHY_TX |
0075              MESON_SDHC_SRST_DMA_IF);
0076     usleep_range(10, 100);
0077 
0078     regmap_write(host->regmap, MESON_SDHC_SRST, 0);
0079     usleep_range(10, 100);
0080 }
0081 
0082 static void meson_mx_sdhc_clear_fifo(struct mmc_host *mmc)
0083 {
0084     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0085     u32 stat;
0086 
0087     regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
0088     if (!FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat) &&
0089         !FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat))
0090         return;
0091 
0092     regmap_write(host->regmap, MESON_SDHC_SRST, MESON_SDHC_SRST_RXFIFO |
0093              MESON_SDHC_SRST_TXFIFO | MESON_SDHC_SRST_MAIN_CTRL);
0094     udelay(5);
0095 
0096     regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
0097     if (FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat) ||
0098         FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat))
0099         dev_warn(mmc_dev(host->mmc),
0100              "Failed to clear FIFOs, RX: %lu, TX: %lu\n",
0101              FIELD_GET(MESON_SDHC_STAT_RXFIFO_CNT, stat),
0102              FIELD_GET(MESON_SDHC_STAT_TXFIFO_CNT, stat));
0103 }
0104 
0105 static void meson_mx_sdhc_wait_cmd_ready(struct mmc_host *mmc)
0106 {
0107     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0108     u32 stat, esta;
0109     int ret;
0110 
0111     ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_STAT, stat,
0112                        !(stat & MESON_SDHC_STAT_CMD_BUSY),
0113                        MESON_SDHC_WAIT_CMD_READY_SLEEP_US,
0114                        MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US);
0115     if (ret) {
0116         dev_warn(mmc_dev(mmc),
0117              "Failed to poll for CMD_BUSY while processing CMD%d\n",
0118              host->cmd->opcode);
0119         meson_mx_sdhc_hw_reset(mmc);
0120     }
0121 
0122     ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_ESTA, esta,
0123                        !(esta & MESON_SDHC_ESTA_11_13),
0124                        MESON_SDHC_WAIT_CMD_READY_SLEEP_US,
0125                        MESON_SDHC_WAIT_CMD_READY_TIMEOUT_US);
0126     if (ret) {
0127         dev_warn(mmc_dev(mmc),
0128              "Failed to poll for ESTA[13:11] while processing CMD%d\n",
0129              host->cmd->opcode);
0130         meson_mx_sdhc_hw_reset(mmc);
0131     }
0132 }
0133 
0134 static void meson_mx_sdhc_start_cmd(struct mmc_host *mmc,
0135                     struct mmc_command *cmd)
0136 {
0137     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0138     bool manual_stop = false;
0139     u32 ictl, send;
0140     int pack_len;
0141 
0142     host->cmd = cmd;
0143 
0144     ictl = MESON_SDHC_ICTL_DATA_TIMEOUT | MESON_SDHC_ICTL_DATA_ERR_CRC |
0145            MESON_SDHC_ICTL_RXFIFO_FULL | MESON_SDHC_ICTL_TXFIFO_EMPTY |
0146            MESON_SDHC_ICTL_RESP_TIMEOUT | MESON_SDHC_ICTL_RESP_ERR_CRC;
0147 
0148     send = FIELD_PREP(MESON_SDHC_SEND_CMD_INDEX, cmd->opcode);
0149 
0150     if (cmd->data) {
0151         send |= MESON_SDHC_SEND_CMD_HAS_DATA;
0152         send |= FIELD_PREP(MESON_SDHC_SEND_TOTAL_PACK,
0153                    cmd->data->blocks - 1);
0154 
0155         if (cmd->data->blksz < MESON_SDHC_MAX_BLK_SIZE)
0156             pack_len = cmd->data->blksz;
0157         else
0158             pack_len = 0;
0159 
0160         if (cmd->data->flags & MMC_DATA_WRITE)
0161             send |= MESON_SDHC_SEND_DATA_DIR;
0162 
0163         /*
0164          * If command with no data, just wait response done
0165          * interrupt(int[0]), and if command with data transfer, just
0166          * wait dma done interrupt(int[11]), don't need care about
0167          * dat0 busy or not.
0168          */
0169         if (host->platform->hardware_flush_all_cmds ||
0170             cmd->data->flags & MMC_DATA_WRITE)
0171             /* hardware flush: */
0172             ictl |= MESON_SDHC_ICTL_DMA_DONE;
0173         else
0174             /* software flush: */
0175             ictl |= MESON_SDHC_ICTL_DATA_XFER_OK;
0176 
0177         /*
0178          * Mimic the logic from the vendor driver where (only)
0179          * SD_IO_RW_EXTENDED commands with more than one block set the
0180          * MESON_SDHC_MISC_MANUAL_STOP bit. This fixes the firmware
0181          * download in the brcmfmac driver for a BCM43362/1 card.
0182          * Without this sdio_memcpy_toio() (with a size of 219557
0183          * bytes) times out if MESON_SDHC_MISC_MANUAL_STOP is not set.
0184          */
0185         manual_stop = cmd->data->blocks > 1 &&
0186                   cmd->opcode == SD_IO_RW_EXTENDED;
0187     } else {
0188         pack_len = 0;
0189 
0190         ictl |= MESON_SDHC_ICTL_RESP_OK;
0191     }
0192 
0193     regmap_update_bits(host->regmap, MESON_SDHC_MISC,
0194                MESON_SDHC_MISC_MANUAL_STOP,
0195                manual_stop ? MESON_SDHC_MISC_MANUAL_STOP : 0);
0196 
0197     if (cmd->opcode == MMC_STOP_TRANSMISSION)
0198         send |= MESON_SDHC_SEND_DATA_STOP;
0199 
0200     if (cmd->flags & MMC_RSP_PRESENT)
0201         send |= MESON_SDHC_SEND_CMD_HAS_RESP;
0202 
0203     if (cmd->flags & MMC_RSP_136) {
0204         send |= MESON_SDHC_SEND_RESP_LEN;
0205         send |= MESON_SDHC_SEND_RESP_NO_CRC;
0206     }
0207 
0208     if (!(cmd->flags & MMC_RSP_CRC))
0209         send |= MESON_SDHC_SEND_RESP_NO_CRC;
0210 
0211     if (cmd->flags & MMC_RSP_BUSY)
0212         send |= MESON_SDHC_SEND_R1B;
0213 
0214     /* enable the new IRQs and mask all pending ones */
0215     regmap_write(host->regmap, MESON_SDHC_ICTL, ictl);
0216     regmap_write(host->regmap, MESON_SDHC_ISTA, MESON_SDHC_ISTA_ALL_IRQS);
0217 
0218     regmap_write(host->regmap, MESON_SDHC_ARGU, cmd->arg);
0219 
0220     regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
0221                MESON_SDHC_CTRL_PACK_LEN,
0222                FIELD_PREP(MESON_SDHC_CTRL_PACK_LEN, pack_len));
0223 
0224     if (cmd->data)
0225         regmap_write(host->regmap, MESON_SDHC_ADDR,
0226                  sg_dma_address(cmd->data->sg));
0227 
0228     meson_mx_sdhc_wait_cmd_ready(mmc);
0229 
0230     if (cmd->data)
0231         host->platform->set_pdma(mmc);
0232 
0233     if (host->platform->wait_before_send)
0234         host->platform->wait_before_send(mmc);
0235 
0236     regmap_write(host->regmap, MESON_SDHC_SEND, send);
0237 }
0238 
0239 static void meson_mx_sdhc_disable_clks(struct mmc_host *mmc)
0240 {
0241     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0242 
0243     if (!host->bulk_clks_enabled)
0244         return;
0245 
0246     clk_bulk_disable_unprepare(MESON_SDHC_NUM_BULK_CLKS, host->bulk_clks);
0247 
0248     host->bulk_clks_enabled = false;
0249 }
0250 
0251 static int meson_mx_sdhc_enable_clks(struct mmc_host *mmc)
0252 {
0253     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0254     int ret;
0255 
0256     if (host->bulk_clks_enabled)
0257         return 0;
0258 
0259     ret = clk_bulk_prepare_enable(MESON_SDHC_NUM_BULK_CLKS,
0260                       host->bulk_clks);
0261     if (ret)
0262         return ret;
0263 
0264     host->bulk_clks_enabled = true;
0265 
0266     return 0;
0267 }
0268 
0269 static int meson_mx_sdhc_set_clk(struct mmc_host *mmc, struct mmc_ios *ios)
0270 {
0271     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0272     u32 rx_clk_phase;
0273     int ret;
0274 
0275     meson_mx_sdhc_disable_clks(mmc);
0276 
0277     if (ios->clock) {
0278         ret = clk_set_rate(host->sd_clk, ios->clock);
0279         if (ret) {
0280             dev_warn(mmc_dev(mmc),
0281                  "Failed to set MMC clock to %uHz: %d\n",
0282                  ios->clock, host->error);
0283             return ret;
0284         }
0285 
0286         ret = meson_mx_sdhc_enable_clks(mmc);
0287         if (ret)
0288             return ret;
0289 
0290         mmc->actual_clock = clk_get_rate(host->sd_clk);
0291 
0292         /*
0293          * according to Amlogic the following latching points are
0294          * selected with empirical values, there is no (known) formula
0295          * to calculate these.
0296          */
0297         if (mmc->actual_clock > 100000000) {
0298             rx_clk_phase = 1;
0299         } else if (mmc->actual_clock > 45000000) {
0300             if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
0301                 rx_clk_phase = 15;
0302             else
0303                 rx_clk_phase = 11;
0304         } else if (mmc->actual_clock >= 25000000) {
0305             rx_clk_phase = 15;
0306         } else if (mmc->actual_clock > 5000000) {
0307             rx_clk_phase = 23;
0308         } else if (mmc->actual_clock > 1000000) {
0309             rx_clk_phase = 55;
0310         } else {
0311             rx_clk_phase = 1061;
0312         }
0313 
0314         regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
0315                    MESON_SDHC_CLK2_RX_CLK_PHASE,
0316                    FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
0317                           rx_clk_phase));
0318     } else {
0319         mmc->actual_clock = 0;
0320     }
0321 
0322     return 0;
0323 }
0324 
0325 static void meson_mx_sdhc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0326 {
0327     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0328     unsigned short vdd = ios->vdd;
0329 
0330     switch (ios->power_mode) {
0331     case MMC_POWER_OFF:
0332         vdd = 0;
0333         fallthrough;
0334 
0335     case MMC_POWER_UP:
0336         if (!IS_ERR(mmc->supply.vmmc)) {
0337             host->error = mmc_regulator_set_ocr(mmc,
0338                                 mmc->supply.vmmc,
0339                                 vdd);
0340             if (host->error)
0341                 return;
0342         }
0343 
0344         break;
0345 
0346     case MMC_POWER_ON:
0347         break;
0348     }
0349 
0350     host->error = meson_mx_sdhc_set_clk(mmc, ios);
0351     if (host->error)
0352         return;
0353 
0354     switch (ios->bus_width) {
0355     case MMC_BUS_WIDTH_1:
0356         regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
0357                    MESON_SDHC_CTRL_DAT_TYPE,
0358                    FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 0));
0359         break;
0360 
0361     case MMC_BUS_WIDTH_4:
0362         regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
0363                    MESON_SDHC_CTRL_DAT_TYPE,
0364                    FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 1));
0365         break;
0366 
0367     case MMC_BUS_WIDTH_8:
0368         regmap_update_bits(host->regmap, MESON_SDHC_CTRL,
0369                    MESON_SDHC_CTRL_DAT_TYPE,
0370                    FIELD_PREP(MESON_SDHC_CTRL_DAT_TYPE, 2));
0371         break;
0372 
0373     default:
0374         dev_err(mmc_dev(mmc), "unsupported bus width: %d\n",
0375             ios->bus_width);
0376         host->error = -EINVAL;
0377         return;
0378     }
0379 }
0380 
0381 static int meson_mx_sdhc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq)
0382 {
0383     struct mmc_data *data = mrq->data;
0384     int dma_len;
0385 
0386     if (!data)
0387         return 0;
0388 
0389     dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
0390                  mmc_get_dma_dir(data));
0391     if (dma_len <= 0) {
0392         dev_err(mmc_dev(mmc), "dma_map_sg failed\n");
0393         return -ENOMEM;
0394     }
0395 
0396     return 0;
0397 }
0398 
0399 static void meson_mx_sdhc_request(struct mmc_host *mmc, struct mmc_request *mrq)
0400 {
0401     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0402     struct mmc_command *cmd = mrq->cmd;
0403 
0404     if (!host->error)
0405         host->error = meson_mx_sdhc_map_dma(mmc, mrq);
0406 
0407     if (host->error) {
0408         cmd->error = host->error;
0409         mmc_request_done(mmc, mrq);
0410         return;
0411     }
0412 
0413     host->mrq = mrq;
0414 
0415     meson_mx_sdhc_start_cmd(mmc, mrq->cmd);
0416 }
0417 
0418 static int meson_mx_sdhc_card_busy(struct mmc_host *mmc)
0419 {
0420     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0421     u32 stat;
0422 
0423     regmap_read(host->regmap, MESON_SDHC_STAT, &stat);
0424     return FIELD_GET(MESON_SDHC_STAT_DAT3_0, stat) == 0;
0425 }
0426 
0427 static bool meson_mx_sdhc_tuning_point_matches(struct mmc_host *mmc,
0428                            u32 opcode)
0429 {
0430     unsigned int i, num_matches = 0;
0431     int ret;
0432 
0433     for (i = 0; i < MESON_SDHC_NUM_TUNING_TRIES; i++) {
0434         ret = mmc_send_tuning(mmc, opcode, NULL);
0435         if (!ret)
0436             num_matches++;
0437     }
0438 
0439     return num_matches == MESON_SDHC_NUM_TUNING_TRIES;
0440 }
0441 
0442 static int meson_mx_sdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
0443 {
0444     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0445     int div, start, len, best_start, best_len;
0446     int curr_phase, old_phase, new_phase;
0447     u32 val;
0448 
0449     len = 0;
0450     start = 0;
0451     best_len = 0;
0452 
0453     regmap_read(host->regmap, MESON_SDHC_CLK2, &val);
0454     old_phase = FIELD_GET(MESON_SDHC_CLK2_RX_CLK_PHASE, val);
0455 
0456     regmap_read(host->regmap, MESON_SDHC_CLKC, &val);
0457     div = FIELD_GET(MESON_SDHC_CLKC_CLK_DIV, val);
0458 
0459     for (curr_phase = 0; curr_phase <= div; curr_phase++) {
0460         regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
0461                    MESON_SDHC_CLK2_RX_CLK_PHASE,
0462                    FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
0463                           curr_phase));
0464 
0465         if (meson_mx_sdhc_tuning_point_matches(mmc, opcode)) {
0466             if (!len) {
0467                 start = curr_phase;
0468 
0469                 dev_dbg(mmc_dev(mmc),
0470                     "New RX phase window starts at %u\n",
0471                     start);
0472             }
0473 
0474             len++;
0475         } else {
0476             if (len > best_len) {
0477                 best_start = start;
0478                 best_len = len;
0479 
0480                 dev_dbg(mmc_dev(mmc),
0481                     "New best RX phase window: %u - %u\n",
0482                     best_start, best_start + best_len);
0483             }
0484 
0485             /* reset the current window */
0486             len = 0;
0487         }
0488     }
0489 
0490     if (len > best_len)
0491         /* the last window is the best (or possibly only) window */
0492         new_phase = start + (len / 2);
0493     else if (best_len)
0494         /* there was a better window than the last */
0495         new_phase = best_start + (best_len / 2);
0496     else
0497         /* no window was found at all, reset to the original phase */
0498         new_phase = old_phase;
0499 
0500     regmap_update_bits(host->regmap, MESON_SDHC_CLK2,
0501                MESON_SDHC_CLK2_RX_CLK_PHASE,
0502                FIELD_PREP(MESON_SDHC_CLK2_RX_CLK_PHASE,
0503                       new_phase));
0504 
0505     if (!len && !best_len)
0506         return -EIO;
0507 
0508     dev_dbg(mmc_dev(mmc), "Tuned RX clock phase to %u\n", new_phase);
0509 
0510     return 0;
0511 }
0512 
0513 static const struct mmc_host_ops meson_mx_sdhc_ops = {
0514     .card_hw_reset          = meson_mx_sdhc_hw_reset,
0515     .request            = meson_mx_sdhc_request,
0516     .set_ios            = meson_mx_sdhc_set_ios,
0517     .card_busy          = meson_mx_sdhc_card_busy,
0518     .execute_tuning         = meson_mx_sdhc_execute_tuning,
0519     .get_cd             = mmc_gpio_get_cd,
0520     .get_ro             = mmc_gpio_get_ro,
0521 };
0522 
0523 static void meson_mx_sdhc_request_done(struct meson_mx_sdhc_host *host)
0524 {
0525     struct mmc_request *mrq = host->mrq;
0526     struct mmc_host *mmc = host->mmc;
0527 
0528     /* disable interrupts and mask all pending ones */
0529     regmap_update_bits(host->regmap, MESON_SDHC_ICTL,
0530                MESON_SDHC_ICTL_ALL_IRQS, 0);
0531     regmap_update_bits(host->regmap, MESON_SDHC_ISTA,
0532                MESON_SDHC_ISTA_ALL_IRQS, MESON_SDHC_ISTA_ALL_IRQS);
0533 
0534     host->mrq = NULL;
0535     host->cmd = NULL;
0536 
0537     mmc_request_done(mmc, mrq);
0538 }
0539 
0540 static u32 meson_mx_sdhc_read_response(struct meson_mx_sdhc_host *host, u8 idx)
0541 {
0542     u32 val;
0543 
0544     regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
0545                MESON_SDHC_PDMA_DMA_MODE, 0);
0546 
0547     regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
0548                MESON_SDHC_PDMA_PIO_RDRESP,
0549                FIELD_PREP(MESON_SDHC_PDMA_PIO_RDRESP, idx));
0550 
0551     regmap_read(host->regmap, MESON_SDHC_ARGU, &val);
0552 
0553     return val;
0554 }
0555 
0556 static irqreturn_t meson_mx_sdhc_irq(int irq, void *data)
0557 {
0558     struct meson_mx_sdhc_host *host = data;
0559     struct mmc_command *cmd = host->cmd;
0560     u32 ictl, ista;
0561 
0562     regmap_read(host->regmap, MESON_SDHC_ICTL, &ictl);
0563     regmap_read(host->regmap, MESON_SDHC_ISTA, &ista);
0564 
0565     if (!(ictl & ista))
0566         return IRQ_NONE;
0567 
0568     if (ista & MESON_SDHC_ISTA_RXFIFO_FULL ||
0569         ista & MESON_SDHC_ISTA_TXFIFO_EMPTY)
0570         cmd->error = -EIO;
0571     else if (ista & MESON_SDHC_ISTA_RESP_ERR_CRC)
0572         cmd->error = -EILSEQ;
0573     else if (ista & MESON_SDHC_ISTA_RESP_TIMEOUT)
0574         cmd->error = -ETIMEDOUT;
0575 
0576     if (cmd->data) {
0577         if (ista & MESON_SDHC_ISTA_DATA_ERR_CRC)
0578             cmd->data->error = -EILSEQ;
0579         else if (ista & MESON_SDHC_ISTA_DATA_TIMEOUT)
0580             cmd->data->error = -ETIMEDOUT;
0581     }
0582 
0583     if (cmd->error || (cmd->data && cmd->data->error))
0584         dev_dbg(mmc_dev(host->mmc), "CMD%d error, ISTA: 0x%08x\n",
0585             cmd->opcode, ista);
0586 
0587     return IRQ_WAKE_THREAD;
0588 }
0589 
0590 static irqreturn_t meson_mx_sdhc_irq_thread(int irq, void *irq_data)
0591 {
0592     struct meson_mx_sdhc_host *host = irq_data;
0593     struct mmc_command *cmd;
0594     u32 val;
0595 
0596     cmd = host->cmd;
0597     if (WARN_ON(!cmd))
0598         return IRQ_HANDLED;
0599 
0600     if (cmd->data && !cmd->data->error) {
0601         if (!host->platform->hardware_flush_all_cmds &&
0602             cmd->data->flags & MMC_DATA_READ) {
0603             meson_mx_sdhc_wait_cmd_ready(host->mmc);
0604 
0605             /*
0606              * If MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH was
0607              * previously 0x1 then it has to be set to 0x3. If it
0608              * was 0x0 before then it has to be set to 0x2. Without
0609              * this reading SD cards sometimes transfers garbage,
0610              * which results in cards not being detected due to:
0611              *   unrecognised SCR structure version <random number>
0612              */
0613             val = FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
0614                      2);
0615             regmap_update_bits(host->regmap, MESON_SDHC_PDMA, val,
0616                        val);
0617         }
0618 
0619         dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg,
0620                  cmd->data->sg_len, mmc_get_dma_dir(cmd->data));
0621 
0622         cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks;
0623     }
0624 
0625     meson_mx_sdhc_wait_cmd_ready(host->mmc);
0626 
0627     if (cmd->flags & MMC_RSP_136) {
0628         cmd->resp[0] = meson_mx_sdhc_read_response(host, 4);
0629         cmd->resp[1] = meson_mx_sdhc_read_response(host, 3);
0630         cmd->resp[2] = meson_mx_sdhc_read_response(host, 2);
0631         cmd->resp[3] = meson_mx_sdhc_read_response(host, 1);
0632     } else {
0633         cmd->resp[0] = meson_mx_sdhc_read_response(host, 0);
0634     }
0635 
0636     if (cmd->error == -EIO || cmd->error == -ETIMEDOUT)
0637         meson_mx_sdhc_hw_reset(host->mmc);
0638     else if (cmd->data)
0639         /*
0640          * Clear the FIFOs after completing data transfers to prevent
0641          * corrupting data on write access. It's not clear why this is
0642          * needed (for reads and writes), but it mimics what the BSP
0643          * kernel did.
0644          */
0645         meson_mx_sdhc_clear_fifo(host->mmc);
0646 
0647     meson_mx_sdhc_request_done(host);
0648 
0649     return IRQ_HANDLED;
0650 }
0651 
0652 static void meson_mx_sdhc_init_hw_meson8(struct mmc_host *mmc)
0653 {
0654     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0655 
0656     regmap_write(host->regmap, MESON_SDHC_MISC,
0657              FIELD_PREP(MESON_SDHC_MISC_TXSTART_THRES, 7) |
0658              FIELD_PREP(MESON_SDHC_MISC_WCRC_ERR_PATT, 5) |
0659              FIELD_PREP(MESON_SDHC_MISC_WCRC_OK_PATT, 2));
0660 
0661     regmap_write(host->regmap, MESON_SDHC_ENHC,
0662              FIELD_PREP(MESON_SDHC_ENHC_RXFIFO_TH, 63) |
0663              MESON_SDHC_ENHC_MESON6_DMA_WR_RESP |
0664              FIELD_PREP(MESON_SDHC_ENHC_MESON6_RX_TIMEOUT, 255) |
0665              FIELD_PREP(MESON_SDHC_ENHC_SDIO_IRQ_PERIOD, 12));
0666 };
0667 
0668 static void meson_mx_sdhc_set_pdma_meson8(struct mmc_host *mmc)
0669 {
0670     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0671 
0672     if (host->cmd->data->flags & MMC_DATA_WRITE)
0673         regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
0674                    MESON_SDHC_PDMA_DMA_MODE |
0675                    MESON_SDHC_PDMA_RD_BURST |
0676                    MESON_SDHC_PDMA_TXFIFO_FILL,
0677                    MESON_SDHC_PDMA_DMA_MODE |
0678                    FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 31) |
0679                    MESON_SDHC_PDMA_TXFIFO_FILL);
0680     else
0681         regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
0682                    MESON_SDHC_PDMA_DMA_MODE |
0683                    MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
0684                    MESON_SDHC_PDMA_DMA_MODE |
0685                    FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_MANUAL_FLUSH,
0686                           1));
0687 
0688     if (host->cmd->data->flags & MMC_DATA_WRITE)
0689         regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
0690                    MESON_SDHC_PDMA_RD_BURST,
0691                    FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 15));
0692 }
0693 
0694 static void meson_mx_sdhc_wait_before_send_meson8(struct mmc_host *mmc)
0695 {
0696     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0697     u32 val;
0698     int ret;
0699 
0700     ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_ESTA, val,
0701                        val == 0,
0702                        MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US,
0703                        MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US);
0704     if (ret)
0705         dev_warn(mmc_dev(mmc),
0706              "Failed to wait for ESTA to clear: 0x%08x\n", val);
0707 
0708     if (host->cmd->data && host->cmd->data->flags & MMC_DATA_WRITE) {
0709         ret = regmap_read_poll_timeout(host->regmap, MESON_SDHC_STAT,
0710                     val, val & MESON_SDHC_STAT_TXFIFO_CNT,
0711                     MESON_SDHC_WAIT_BEFORE_SEND_SLEEP_US,
0712                     MESON_SDHC_WAIT_BEFORE_SEND_TIMEOUT_US);
0713         if (ret)
0714             dev_warn(mmc_dev(mmc),
0715                  "Failed to wait for TX FIFO to fill\n");
0716     }
0717 }
0718 
0719 static void meson_mx_sdhc_init_hw_meson8m2(struct mmc_host *mmc)
0720 {
0721     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0722 
0723     regmap_write(host->regmap, MESON_SDHC_MISC,
0724              FIELD_PREP(MESON_SDHC_MISC_TXSTART_THRES, 6) |
0725              FIELD_PREP(MESON_SDHC_MISC_WCRC_ERR_PATT, 5) |
0726              FIELD_PREP(MESON_SDHC_MISC_WCRC_OK_PATT, 2));
0727 
0728     regmap_write(host->regmap, MESON_SDHC_ENHC,
0729              FIELD_PREP(MESON_SDHC_ENHC_RXFIFO_TH, 64) |
0730              FIELD_PREP(MESON_SDHC_ENHC_MESON8M2_DEBUG, 1) |
0731              MESON_SDHC_ENHC_MESON8M2_WRRSP_MODE |
0732              FIELD_PREP(MESON_SDHC_ENHC_SDIO_IRQ_PERIOD, 12));
0733 }
0734 
0735 static void meson_mx_sdhc_set_pdma_meson8m2(struct mmc_host *mmc)
0736 {
0737     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0738 
0739     regmap_update_bits(host->regmap, MESON_SDHC_PDMA,
0740                MESON_SDHC_PDMA_DMA_MODE, MESON_SDHC_PDMA_DMA_MODE);
0741 }
0742 
0743 static void meson_mx_sdhc_init_hw(struct mmc_host *mmc)
0744 {
0745     struct meson_mx_sdhc_host *host = mmc_priv(mmc);
0746 
0747     meson_mx_sdhc_hw_reset(mmc);
0748 
0749     regmap_write(host->regmap, MESON_SDHC_CTRL,
0750              FIELD_PREP(MESON_SDHC_CTRL_RX_PERIOD, 0xf) |
0751              FIELD_PREP(MESON_SDHC_CTRL_RX_TIMEOUT, 0x7f) |
0752              FIELD_PREP(MESON_SDHC_CTRL_RX_ENDIAN, 0x7) |
0753              FIELD_PREP(MESON_SDHC_CTRL_TX_ENDIAN, 0x7));
0754 
0755     /*
0756      * start with a valid divider and enable the memory (un-setting
0757      * MESON_SDHC_CLKC_MEM_PWR_OFF).
0758      */
0759     regmap_write(host->regmap, MESON_SDHC_CLKC, MESON_SDHC_CLKC_CLK_DIV);
0760 
0761     regmap_write(host->regmap, MESON_SDHC_CLK2,
0762              FIELD_PREP(MESON_SDHC_CLK2_SD_CLK_PHASE, 1));
0763 
0764     regmap_write(host->regmap, MESON_SDHC_PDMA,
0765              MESON_SDHC_PDMA_DMA_URGENT |
0766              FIELD_PREP(MESON_SDHC_PDMA_WR_BURST, 7) |
0767              FIELD_PREP(MESON_SDHC_PDMA_TXFIFO_TH, 49) |
0768              FIELD_PREP(MESON_SDHC_PDMA_RD_BURST, 15) |
0769              FIELD_PREP(MESON_SDHC_PDMA_RXFIFO_TH, 7));
0770 
0771     /* some initialization bits depend on the SoC: */
0772     host->platform->init_hw(mmc);
0773 
0774     /* disable and mask all interrupts: */
0775     regmap_write(host->regmap, MESON_SDHC_ICTL, 0);
0776     regmap_write(host->regmap, MESON_SDHC_ISTA, MESON_SDHC_ISTA_ALL_IRQS);
0777 }
0778 
0779 static int meson_mx_sdhc_probe(struct platform_device *pdev)
0780 {
0781     struct device *dev = &pdev->dev;
0782     struct meson_mx_sdhc_host *host;
0783     struct mmc_host *mmc;
0784     void __iomem *base;
0785     int ret, irq;
0786 
0787     mmc = mmc_alloc_host(sizeof(*host), dev);
0788     if (!mmc)
0789         return -ENOMEM;
0790 
0791     ret = devm_add_action_or_reset(dev, (void(*)(void *))mmc_free_host,
0792                        mmc);
0793     if (ret) {
0794         dev_err(dev, "Failed to register mmc_free_host action\n");
0795         return ret;
0796     }
0797 
0798     host = mmc_priv(mmc);
0799     host->mmc = mmc;
0800 
0801     platform_set_drvdata(pdev, host);
0802 
0803     host->platform = device_get_match_data(dev);
0804     if (!host->platform)
0805         return -EINVAL;
0806 
0807     base = devm_platform_ioremap_resource(pdev, 0);
0808     if (IS_ERR(base))
0809         return PTR_ERR(base);
0810 
0811     host->regmap = devm_regmap_init_mmio(dev, base,
0812                          &meson_mx_sdhc_regmap_config);
0813     if (IS_ERR(host->regmap))
0814         return PTR_ERR(host->regmap);
0815 
0816     host->pclk = devm_clk_get(dev, "pclk");
0817     if (IS_ERR(host->pclk))
0818         return PTR_ERR(host->pclk);
0819 
0820     /* accessing any register requires the module clock to be enabled: */
0821     ret = clk_prepare_enable(host->pclk);
0822     if (ret) {
0823         dev_err(dev, "Failed to enable 'pclk' clock\n");
0824         return ret;
0825     }
0826 
0827     meson_mx_sdhc_init_hw(mmc);
0828 
0829     ret = meson_mx_sdhc_register_clkc(dev, base, host->bulk_clks);
0830     if (ret)
0831         goto err_disable_pclk;
0832 
0833     host->sd_clk = host->bulk_clks[1].clk;
0834 
0835     /* Get regulators and the supported OCR mask */
0836     ret = mmc_regulator_get_supply(mmc);
0837     if (ret)
0838         goto err_disable_pclk;
0839 
0840     mmc->max_req_size = SZ_128K;
0841     mmc->max_seg_size = mmc->max_req_size;
0842     mmc->max_blk_count = FIELD_GET(MESON_SDHC_SEND_TOTAL_PACK, ~0);
0843     mmc->max_blk_size = MESON_SDHC_MAX_BLK_SIZE;
0844     mmc->max_busy_timeout = 30 * MSEC_PER_SEC;
0845     mmc->f_min = clk_round_rate(host->sd_clk, 1);
0846     mmc->f_max = clk_round_rate(host->sd_clk, ULONG_MAX);
0847     mmc->max_current_180 = 300;
0848     mmc->max_current_330 = 300;
0849     mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_HW_RESET;
0850     mmc->ops = &meson_mx_sdhc_ops;
0851 
0852     ret = mmc_of_parse(mmc);
0853     if (ret)
0854         goto err_disable_pclk;
0855 
0856     irq = platform_get_irq(pdev, 0);
0857     if (irq < 0) {
0858         ret = irq;
0859         goto err_disable_pclk;
0860     }
0861 
0862     ret = devm_request_threaded_irq(dev, irq, meson_mx_sdhc_irq,
0863                     meson_mx_sdhc_irq_thread, IRQF_ONESHOT,
0864                     NULL, host);
0865     if (ret)
0866         goto err_disable_pclk;
0867 
0868     ret = mmc_add_host(mmc);
0869     if (ret)
0870         goto err_disable_pclk;
0871 
0872     return 0;
0873 
0874 err_disable_pclk:
0875     clk_disable_unprepare(host->pclk);
0876     return ret;
0877 }
0878 
0879 static int meson_mx_sdhc_remove(struct platform_device *pdev)
0880 {
0881     struct meson_mx_sdhc_host *host = platform_get_drvdata(pdev);
0882 
0883     mmc_remove_host(host->mmc);
0884 
0885     meson_mx_sdhc_disable_clks(host->mmc);
0886 
0887     clk_disable_unprepare(host->pclk);
0888 
0889     return 0;
0890 }
0891 
0892 static const struct meson_mx_sdhc_data meson_mx_sdhc_data_meson8 = {
0893     .init_hw            = meson_mx_sdhc_init_hw_meson8,
0894     .set_pdma           = meson_mx_sdhc_set_pdma_meson8,
0895     .wait_before_send       = meson_mx_sdhc_wait_before_send_meson8,
0896     .hardware_flush_all_cmds    = false,
0897 };
0898 
0899 static const struct meson_mx_sdhc_data meson_mx_sdhc_data_meson8m2 = {
0900     .init_hw            = meson_mx_sdhc_init_hw_meson8m2,
0901     .set_pdma           = meson_mx_sdhc_set_pdma_meson8m2,
0902     .hardware_flush_all_cmds    = true,
0903 };
0904 
0905 static const struct of_device_id meson_mx_sdhc_of_match[] = {
0906     {
0907         .compatible = "amlogic,meson8-sdhc",
0908         .data = &meson_mx_sdhc_data_meson8
0909     },
0910     {
0911         .compatible = "amlogic,meson8b-sdhc",
0912         .data = &meson_mx_sdhc_data_meson8
0913     },
0914     {
0915         .compatible = "amlogic,meson8m2-sdhc",
0916         .data = &meson_mx_sdhc_data_meson8m2
0917     },
0918     { /* sentinel */ }
0919 };
0920 MODULE_DEVICE_TABLE(of, meson_mx_sdhc_of_match);
0921 
0922 static struct platform_driver meson_mx_sdhc_driver = {
0923     .probe   = meson_mx_sdhc_probe,
0924     .remove  = meson_mx_sdhc_remove,
0925     .driver  = {
0926         .name = "meson-mx-sdhc",
0927         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0928         .of_match_table = of_match_ptr(meson_mx_sdhc_of_match),
0929     },
0930 };
0931 
0932 module_platform_driver(meson_mx_sdhc_driver);
0933 
0934 MODULE_DESCRIPTION("Meson6, Meson8, Meson8b and Meson8m2 SDHC Host Driver");
0935 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
0936 MODULE_LICENSE("GPL v2");
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