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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Amlogic SD/eMMC driver for the GX/S905 family SoCs
0004  *
0005  * Copyright (c) 2016 BayLibre, SAS.
0006  * Author: Kevin Hilman <khilman@baylibre.com>
0007  */
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/init.h>
0011 #include <linux/delay.h>
0012 #include <linux/device.h>
0013 #include <linux/iopoll.h>
0014 #include <linux/of_device.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/ioport.h>
0017 #include <linux/dma-mapping.h>
0018 #include <linux/mmc/host.h>
0019 #include <linux/mmc/mmc.h>
0020 #include <linux/mmc/sdio.h>
0021 #include <linux/mmc/slot-gpio.h>
0022 #include <linux/io.h>
0023 #include <linux/clk.h>
0024 #include <linux/clk-provider.h>
0025 #include <linux/regulator/consumer.h>
0026 #include <linux/reset.h>
0027 #include <linux/interrupt.h>
0028 #include <linux/bitfield.h>
0029 #include <linux/pinctrl/consumer.h>
0030 
0031 #define DRIVER_NAME "meson-gx-mmc"
0032 
0033 #define SD_EMMC_CLOCK 0x0
0034 #define   CLK_DIV_MASK GENMASK(5, 0)
0035 #define   CLK_SRC_MASK GENMASK(7, 6)
0036 #define   CLK_CORE_PHASE_MASK GENMASK(9, 8)
0037 #define   CLK_TX_PHASE_MASK GENMASK(11, 10)
0038 #define   CLK_RX_PHASE_MASK GENMASK(13, 12)
0039 #define   CLK_PHASE_0 0
0040 #define   CLK_PHASE_180 2
0041 #define   CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
0042 #define   CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
0043 #define   CLK_V2_ALWAYS_ON BIT(24)
0044 
0045 #define   CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
0046 #define   CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
0047 #define   CLK_V3_ALWAYS_ON BIT(28)
0048 
0049 #define   CLK_TX_DELAY_MASK(h)      (h->data->tx_delay_mask)
0050 #define   CLK_RX_DELAY_MASK(h)      (h->data->rx_delay_mask)
0051 #define   CLK_ALWAYS_ON(h)      (h->data->always_on)
0052 
0053 #define SD_EMMC_DELAY 0x4
0054 #define SD_EMMC_ADJUST 0x8
0055 #define   ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
0056 #define   ADJUST_DS_EN BIT(15)
0057 #define   ADJUST_ADJ_EN BIT(13)
0058 
0059 #define SD_EMMC_DELAY1 0x4
0060 #define SD_EMMC_DELAY2 0x8
0061 #define SD_EMMC_V3_ADJUST 0xc
0062 
0063 #define SD_EMMC_CALOUT 0x10
0064 #define SD_EMMC_START 0x40
0065 #define   START_DESC_INIT BIT(0)
0066 #define   START_DESC_BUSY BIT(1)
0067 #define   START_DESC_ADDR_MASK GENMASK(31, 2)
0068 
0069 #define SD_EMMC_CFG 0x44
0070 #define   CFG_BUS_WIDTH_MASK GENMASK(1, 0)
0071 #define   CFG_BUS_WIDTH_1 0x0
0072 #define   CFG_BUS_WIDTH_4 0x1
0073 #define   CFG_BUS_WIDTH_8 0x2
0074 #define   CFG_DDR BIT(2)
0075 #define   CFG_BLK_LEN_MASK GENMASK(7, 4)
0076 #define   CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
0077 #define   CFG_RC_CC_MASK GENMASK(15, 12)
0078 #define   CFG_STOP_CLOCK BIT(22)
0079 #define   CFG_CLK_ALWAYS_ON BIT(18)
0080 #define   CFG_CHK_DS BIT(20)
0081 #define   CFG_AUTO_CLK BIT(23)
0082 #define   CFG_ERR_ABORT BIT(27)
0083 
0084 #define SD_EMMC_STATUS 0x48
0085 #define   STATUS_BUSY BIT(31)
0086 #define   STATUS_DESC_BUSY BIT(30)
0087 #define   STATUS_DATI GENMASK(23, 16)
0088 
0089 #define SD_EMMC_IRQ_EN 0x4c
0090 #define   IRQ_RXD_ERR_MASK GENMASK(7, 0)
0091 #define   IRQ_TXD_ERR BIT(8)
0092 #define   IRQ_DESC_ERR BIT(9)
0093 #define   IRQ_RESP_ERR BIT(10)
0094 #define   IRQ_CRC_ERR \
0095     (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
0096 #define   IRQ_RESP_TIMEOUT BIT(11)
0097 #define   IRQ_DESC_TIMEOUT BIT(12)
0098 #define   IRQ_TIMEOUTS \
0099     (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
0100 #define   IRQ_END_OF_CHAIN BIT(13)
0101 #define   IRQ_RESP_STATUS BIT(14)
0102 #define   IRQ_SDIO BIT(15)
0103 #define   IRQ_EN_MASK \
0104     (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
0105      IRQ_SDIO)
0106 
0107 #define SD_EMMC_CMD_CFG 0x50
0108 #define SD_EMMC_CMD_ARG 0x54
0109 #define SD_EMMC_CMD_DAT 0x58
0110 #define SD_EMMC_CMD_RSP 0x5c
0111 #define SD_EMMC_CMD_RSP1 0x60
0112 #define SD_EMMC_CMD_RSP2 0x64
0113 #define SD_EMMC_CMD_RSP3 0x68
0114 
0115 #define SD_EMMC_RXD 0x94
0116 #define SD_EMMC_TXD 0x94
0117 #define SD_EMMC_LAST_REG SD_EMMC_TXD
0118 
0119 #define SD_EMMC_SRAM_DATA_BUF_LEN 1536
0120 #define SD_EMMC_SRAM_DATA_BUF_OFF 0x200
0121 
0122 #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
0123 #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
0124 #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
0125 #define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
0126 #define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
0127 #define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
0128 
0129 #define SD_EMMC_PRE_REQ_DONE BIT(0)
0130 #define SD_EMMC_DESC_CHAIN_MODE BIT(1)
0131 
0132 #define MUX_CLK_NUM_PARENTS 2
0133 
0134 struct meson_mmc_data {
0135     unsigned int tx_delay_mask;
0136     unsigned int rx_delay_mask;
0137     unsigned int always_on;
0138     unsigned int adjust;
0139 };
0140 
0141 struct sd_emmc_desc {
0142     u32 cmd_cfg;
0143     u32 cmd_arg;
0144     u32 cmd_data;
0145     u32 cmd_resp;
0146 };
0147 
0148 struct meson_host {
0149     struct  device      *dev;
0150     struct  meson_mmc_data *data;
0151     struct  mmc_host    *mmc;
0152     struct  mmc_command *cmd;
0153 
0154     void __iomem *regs;
0155     struct clk *core_clk;
0156     struct clk *mux_clk;
0157     struct clk *mmc_clk;
0158     unsigned long req_rate;
0159     bool ddr;
0160 
0161     bool dram_access_quirk;
0162 
0163     struct pinctrl *pinctrl;
0164     struct pinctrl_state *pins_clk_gate;
0165 
0166     unsigned int bounce_buf_size;
0167     void *bounce_buf;
0168     void __iomem *bounce_iomem_buf;
0169     dma_addr_t bounce_dma_addr;
0170     struct sd_emmc_desc *descs;
0171     dma_addr_t descs_dma_addr;
0172 
0173     int irq;
0174 
0175     bool vqmmc_enabled;
0176     bool needs_pre_post_req;
0177 
0178 };
0179 
0180 #define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
0181 #define CMD_CFG_BLOCK_MODE BIT(9)
0182 #define CMD_CFG_R1B BIT(10)
0183 #define CMD_CFG_END_OF_CHAIN BIT(11)
0184 #define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
0185 #define CMD_CFG_NO_RESP BIT(16)
0186 #define CMD_CFG_NO_CMD BIT(17)
0187 #define CMD_CFG_DATA_IO BIT(18)
0188 #define CMD_CFG_DATA_WR BIT(19)
0189 #define CMD_CFG_RESP_NOCRC BIT(20)
0190 #define CMD_CFG_RESP_128 BIT(21)
0191 #define CMD_CFG_RESP_NUM BIT(22)
0192 #define CMD_CFG_DATA_NUM BIT(23)
0193 #define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
0194 #define CMD_CFG_ERROR BIT(30)
0195 #define CMD_CFG_OWNER BIT(31)
0196 
0197 #define CMD_DATA_MASK GENMASK(31, 2)
0198 #define CMD_DATA_BIG_ENDIAN BIT(1)
0199 #define CMD_DATA_SRAM BIT(0)
0200 #define CMD_RESP_MASK GENMASK(31, 1)
0201 #define CMD_RESP_SRAM BIT(0)
0202 
0203 static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
0204 {
0205     unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
0206 
0207     if (!timeout)
0208         return SD_EMMC_CMD_TIMEOUT_DATA;
0209 
0210     timeout = roundup_pow_of_two(timeout);
0211 
0212     return min(timeout, 32768U); /* max. 2^15 ms */
0213 }
0214 
0215 static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
0216 {
0217     if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
0218         return cmd->mrq->cmd;
0219     else if (mmc_op_multi(cmd->opcode) &&
0220          (!cmd->mrq->sbc || cmd->error || cmd->data->error))
0221         return cmd->mrq->stop;
0222     else
0223         return NULL;
0224 }
0225 
0226 static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
0227                     struct mmc_request *mrq)
0228 {
0229     struct meson_host *host = mmc_priv(mmc);
0230     struct mmc_data *data = mrq->data;
0231     struct scatterlist *sg;
0232     int i;
0233 
0234     /*
0235      * When Controller DMA cannot directly access DDR memory, disable
0236      * support for Chain Mode to directly use the internal SRAM using
0237      * the bounce buffer mode.
0238      */
0239     if (host->dram_access_quirk)
0240         return;
0241 
0242     /* SD_IO_RW_EXTENDED (CMD53) can also use block mode under the hood */
0243     if (data->blocks > 1 || mrq->cmd->opcode == SD_IO_RW_EXTENDED) {
0244         /*
0245          * In block mode DMA descriptor format, "length" field indicates
0246          * number of blocks and there is no way to pass DMA size that
0247          * is not multiple of SDIO block size, making it impossible to
0248          * tie more than one memory buffer with single SDIO block.
0249          * Block mode sg buffer size should be aligned with SDIO block
0250          * size, otherwise chain mode could not be used.
0251          */
0252         for_each_sg(data->sg, sg, data->sg_len, i) {
0253             if (sg->length % data->blksz) {
0254                 dev_warn_once(mmc_dev(mmc),
0255                           "unaligned sg len %u blksize %u, disabling descriptor DMA for transfer\n",
0256                           sg->length, data->blksz);
0257                 return;
0258             }
0259         }
0260     }
0261 
0262     for_each_sg(data->sg, sg, data->sg_len, i) {
0263         /* check for 8 byte alignment */
0264         if (sg->offset % 8) {
0265             dev_warn_once(mmc_dev(mmc),
0266                       "unaligned sg offset %u, disabling descriptor DMA for transfer\n",
0267                       sg->offset);
0268             return;
0269         }
0270     }
0271 
0272     data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
0273 }
0274 
0275 static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
0276 {
0277     return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
0278 }
0279 
0280 static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
0281 {
0282     return data && data->flags & MMC_DATA_READ &&
0283            !meson_mmc_desc_chain_mode(data);
0284 }
0285 
0286 static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
0287 {
0288     struct mmc_data *data = mrq->data;
0289 
0290     if (!data)
0291         return;
0292 
0293     meson_mmc_get_transfer_mode(mmc, mrq);
0294     data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
0295 
0296     if (!meson_mmc_desc_chain_mode(data))
0297         return;
0298 
0299     data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
0300                                    mmc_get_dma_dir(data));
0301     if (!data->sg_count)
0302         dev_err(mmc_dev(mmc), "dma_map_sg failed");
0303 }
0304 
0305 static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
0306                    int err)
0307 {
0308     struct mmc_data *data = mrq->data;
0309 
0310     if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
0311         dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
0312                  mmc_get_dma_dir(data));
0313 }
0314 
0315 /*
0316  * Gating the clock on this controller is tricky.  It seems the mmc clock
0317  * is also used by the controller.  It may crash during some operation if the
0318  * clock is stopped.  The safest thing to do, whenever possible, is to keep
0319  * clock running at stop it at the pad using the pinmux.
0320  */
0321 static void meson_mmc_clk_gate(struct meson_host *host)
0322 {
0323     u32 cfg;
0324 
0325     if (host->pins_clk_gate) {
0326         pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
0327     } else {
0328         /*
0329          * If the pinmux is not provided - default to the classic and
0330          * unsafe method
0331          */
0332         cfg = readl(host->regs + SD_EMMC_CFG);
0333         cfg |= CFG_STOP_CLOCK;
0334         writel(cfg, host->regs + SD_EMMC_CFG);
0335     }
0336 }
0337 
0338 static void meson_mmc_clk_ungate(struct meson_host *host)
0339 {
0340     u32 cfg;
0341 
0342     if (host->pins_clk_gate)
0343         pinctrl_select_default_state(host->dev);
0344 
0345     /* Make sure the clock is not stopped in the controller */
0346     cfg = readl(host->regs + SD_EMMC_CFG);
0347     cfg &= ~CFG_STOP_CLOCK;
0348     writel(cfg, host->regs + SD_EMMC_CFG);
0349 }
0350 
0351 static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,
0352                  bool ddr)
0353 {
0354     struct mmc_host *mmc = host->mmc;
0355     int ret;
0356     u32 cfg;
0357 
0358     /* Same request - bail-out */
0359     if (host->ddr == ddr && host->req_rate == rate)
0360         return 0;
0361 
0362     /* stop clock */
0363     meson_mmc_clk_gate(host);
0364     host->req_rate = 0;
0365     mmc->actual_clock = 0;
0366 
0367     /* return with clock being stopped */
0368     if (!rate)
0369         return 0;
0370 
0371     /* Stop the clock during rate change to avoid glitches */
0372     cfg = readl(host->regs + SD_EMMC_CFG);
0373     cfg |= CFG_STOP_CLOCK;
0374     writel(cfg, host->regs + SD_EMMC_CFG);
0375 
0376     if (ddr) {
0377         /* DDR modes require higher module clock */
0378         rate <<= 1;
0379         cfg |= CFG_DDR;
0380     } else {
0381         cfg &= ~CFG_DDR;
0382     }
0383     writel(cfg, host->regs + SD_EMMC_CFG);
0384     host->ddr = ddr;
0385 
0386     ret = clk_set_rate(host->mmc_clk, rate);
0387     if (ret) {
0388         dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
0389             rate, ret);
0390         return ret;
0391     }
0392 
0393     host->req_rate = rate;
0394     mmc->actual_clock = clk_get_rate(host->mmc_clk);
0395 
0396     /* We should report the real output frequency of the controller */
0397     if (ddr) {
0398         host->req_rate >>= 1;
0399         mmc->actual_clock >>= 1;
0400     }
0401 
0402     dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
0403     if (rate != mmc->actual_clock)
0404         dev_dbg(host->dev, "requested rate was %lu\n", rate);
0405 
0406     /* (re)start clock */
0407     meson_mmc_clk_ungate(host);
0408 
0409     return 0;
0410 }
0411 
0412 /*
0413  * The SD/eMMC IP block has an internal mux and divider used for
0414  * generating the MMC clock.  Use the clock framework to create and
0415  * manage these clocks.
0416  */
0417 static int meson_mmc_clk_init(struct meson_host *host)
0418 {
0419     struct clk_init_data init;
0420     struct clk_mux *mux;
0421     struct clk_divider *div;
0422     char clk_name[32];
0423     int i, ret = 0;
0424     const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
0425     const char *clk_parent[1];
0426     u32 clk_reg;
0427 
0428     /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
0429     clk_reg = CLK_ALWAYS_ON(host);
0430     clk_reg |= CLK_DIV_MASK;
0431     clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
0432     clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
0433     clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
0434     writel(clk_reg, host->regs + SD_EMMC_CLOCK);
0435 
0436     /* get the mux parents */
0437     for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
0438         struct clk *clk;
0439         char name[16];
0440 
0441         snprintf(name, sizeof(name), "clkin%d", i);
0442         clk = devm_clk_get(host->dev, name);
0443         if (IS_ERR(clk))
0444             return dev_err_probe(host->dev, PTR_ERR(clk),
0445                          "Missing clock %s\n", name);
0446 
0447         mux_parent_names[i] = __clk_get_name(clk);
0448     }
0449 
0450     /* create the mux */
0451     mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
0452     if (!mux)
0453         return -ENOMEM;
0454 
0455     snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
0456     init.name = clk_name;
0457     init.ops = &clk_mux_ops;
0458     init.flags = 0;
0459     init.parent_names = mux_parent_names;
0460     init.num_parents = MUX_CLK_NUM_PARENTS;
0461 
0462     mux->reg = host->regs + SD_EMMC_CLOCK;
0463     mux->shift = __ffs(CLK_SRC_MASK);
0464     mux->mask = CLK_SRC_MASK >> mux->shift;
0465     mux->hw.init = &init;
0466 
0467     host->mux_clk = devm_clk_register(host->dev, &mux->hw);
0468     if (WARN_ON(IS_ERR(host->mux_clk)))
0469         return PTR_ERR(host->mux_clk);
0470 
0471     /* create the divider */
0472     div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
0473     if (!div)
0474         return -ENOMEM;
0475 
0476     snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
0477     init.name = clk_name;
0478     init.ops = &clk_divider_ops;
0479     init.flags = CLK_SET_RATE_PARENT;
0480     clk_parent[0] = __clk_get_name(host->mux_clk);
0481     init.parent_names = clk_parent;
0482     init.num_parents = 1;
0483 
0484     div->reg = host->regs + SD_EMMC_CLOCK;
0485     div->shift = __ffs(CLK_DIV_MASK);
0486     div->width = __builtin_popcountl(CLK_DIV_MASK);
0487     div->hw.init = &init;
0488     div->flags = CLK_DIVIDER_ONE_BASED;
0489 
0490     host->mmc_clk = devm_clk_register(host->dev, &div->hw);
0491     if (WARN_ON(IS_ERR(host->mmc_clk)))
0492         return PTR_ERR(host->mmc_clk);
0493 
0494     /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
0495     host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
0496     ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
0497     if (ret)
0498         return ret;
0499 
0500     return clk_prepare_enable(host->mmc_clk);
0501 }
0502 
0503 static void meson_mmc_disable_resampling(struct meson_host *host)
0504 {
0505     unsigned int val = readl(host->regs + host->data->adjust);
0506 
0507     val &= ~ADJUST_ADJ_EN;
0508     writel(val, host->regs + host->data->adjust);
0509 }
0510 
0511 static void meson_mmc_reset_resampling(struct meson_host *host)
0512 {
0513     unsigned int val;
0514 
0515     meson_mmc_disable_resampling(host);
0516 
0517     val = readl(host->regs + host->data->adjust);
0518     val &= ~ADJUST_ADJ_DELAY_MASK;
0519     writel(val, host->regs + host->data->adjust);
0520 }
0521 
0522 static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode)
0523 {
0524     struct meson_host *host = mmc_priv(mmc);
0525     unsigned int val, dly, max_dly, i;
0526     int ret;
0527 
0528     /* Resampling is done using the source clock */
0529     max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),
0530                    clk_get_rate(host->mmc_clk));
0531 
0532     val = readl(host->regs + host->data->adjust);
0533     val |= ADJUST_ADJ_EN;
0534     writel(val, host->regs + host->data->adjust);
0535 
0536     if (mmc_doing_retune(mmc))
0537         dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1;
0538     else
0539         dly = 0;
0540 
0541     for (i = 0; i < max_dly; i++) {
0542         val &= ~ADJUST_ADJ_DELAY_MASK;
0543         val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly);
0544         writel(val, host->regs + host->data->adjust);
0545 
0546         ret = mmc_send_tuning(mmc, opcode, NULL);
0547         if (!ret) {
0548             dev_dbg(mmc_dev(mmc), "resampling delay: %u\n",
0549                 (dly + i) % max_dly);
0550             return 0;
0551         }
0552     }
0553 
0554     meson_mmc_reset_resampling(host);
0555     return -EIO;
0556 }
0557 
0558 static int meson_mmc_prepare_ios_clock(struct meson_host *host,
0559                        struct mmc_ios *ios)
0560 {
0561     bool ddr;
0562 
0563     switch (ios->timing) {
0564     case MMC_TIMING_MMC_DDR52:
0565     case MMC_TIMING_UHS_DDR50:
0566         ddr = true;
0567         break;
0568 
0569     default:
0570         ddr = false;
0571         break;
0572     }
0573 
0574     return meson_mmc_clk_set(host, ios->clock, ddr);
0575 }
0576 
0577 static void meson_mmc_check_resampling(struct meson_host *host,
0578                        struct mmc_ios *ios)
0579 {
0580     switch (ios->timing) {
0581     case MMC_TIMING_LEGACY:
0582     case MMC_TIMING_MMC_HS:
0583     case MMC_TIMING_SD_HS:
0584     case MMC_TIMING_MMC_DDR52:
0585         meson_mmc_disable_resampling(host);
0586         break;
0587     }
0588 }
0589 
0590 static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0591 {
0592     struct meson_host *host = mmc_priv(mmc);
0593     u32 bus_width, val;
0594     int err;
0595 
0596     /*
0597      * GPIO regulator, only controls switching between 1v8 and
0598      * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
0599      */
0600     switch (ios->power_mode) {
0601     case MMC_POWER_OFF:
0602         if (!IS_ERR(mmc->supply.vmmc))
0603             mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
0604 
0605         if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
0606             regulator_disable(mmc->supply.vqmmc);
0607             host->vqmmc_enabled = false;
0608         }
0609 
0610         break;
0611 
0612     case MMC_POWER_UP:
0613         if (!IS_ERR(mmc->supply.vmmc))
0614             mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
0615 
0616         break;
0617 
0618     case MMC_POWER_ON:
0619         if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
0620             int ret = regulator_enable(mmc->supply.vqmmc);
0621 
0622             if (ret < 0)
0623                 dev_err(host->dev,
0624                     "failed to enable vqmmc regulator\n");
0625             else
0626                 host->vqmmc_enabled = true;
0627         }
0628 
0629         break;
0630     }
0631 
0632     /* Bus width */
0633     switch (ios->bus_width) {
0634     case MMC_BUS_WIDTH_1:
0635         bus_width = CFG_BUS_WIDTH_1;
0636         break;
0637     case MMC_BUS_WIDTH_4:
0638         bus_width = CFG_BUS_WIDTH_4;
0639         break;
0640     case MMC_BUS_WIDTH_8:
0641         bus_width = CFG_BUS_WIDTH_8;
0642         break;
0643     default:
0644         dev_err(host->dev, "Invalid ios->bus_width: %u.  Setting to 4.\n",
0645             ios->bus_width);
0646         bus_width = CFG_BUS_WIDTH_4;
0647     }
0648 
0649     val = readl(host->regs + SD_EMMC_CFG);
0650     val &= ~CFG_BUS_WIDTH_MASK;
0651     val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
0652     writel(val, host->regs + SD_EMMC_CFG);
0653 
0654     meson_mmc_check_resampling(host, ios);
0655     err = meson_mmc_prepare_ios_clock(host, ios);
0656     if (err)
0657         dev_err(host->dev, "Failed to set clock: %d\n,", err);
0658 
0659     dev_dbg(host->dev, "SD_EMMC_CFG:  0x%08x\n", val);
0660 }
0661 
0662 static void meson_mmc_request_done(struct mmc_host *mmc,
0663                    struct mmc_request *mrq)
0664 {
0665     struct meson_host *host = mmc_priv(mmc);
0666 
0667     host->cmd = NULL;
0668     if (host->needs_pre_post_req)
0669         meson_mmc_post_req(mmc, mrq, 0);
0670     mmc_request_done(host->mmc, mrq);
0671 }
0672 
0673 static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
0674 {
0675     struct meson_host *host = mmc_priv(mmc);
0676     u32 cfg, blksz_old;
0677 
0678     cfg = readl(host->regs + SD_EMMC_CFG);
0679     blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
0680 
0681     if (!is_power_of_2(blksz))
0682         dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
0683 
0684     blksz = ilog2(blksz);
0685 
0686     /* check if block-size matches, if not update */
0687     if (blksz == blksz_old)
0688         return;
0689 
0690     dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
0691         blksz_old, blksz);
0692 
0693     cfg &= ~CFG_BLK_LEN_MASK;
0694     cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
0695     writel(cfg, host->regs + SD_EMMC_CFG);
0696 }
0697 
0698 static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
0699 {
0700     if (cmd->flags & MMC_RSP_PRESENT) {
0701         if (cmd->flags & MMC_RSP_136)
0702             *cmd_cfg |= CMD_CFG_RESP_128;
0703         *cmd_cfg |= CMD_CFG_RESP_NUM;
0704 
0705         if (!(cmd->flags & MMC_RSP_CRC))
0706             *cmd_cfg |= CMD_CFG_RESP_NOCRC;
0707 
0708         if (cmd->flags & MMC_RSP_BUSY)
0709             *cmd_cfg |= CMD_CFG_R1B;
0710     } else {
0711         *cmd_cfg |= CMD_CFG_NO_RESP;
0712     }
0713 }
0714 
0715 static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
0716 {
0717     struct meson_host *host = mmc_priv(mmc);
0718     struct sd_emmc_desc *desc = host->descs;
0719     struct mmc_data *data = host->cmd->data;
0720     struct scatterlist *sg;
0721     u32 start;
0722     int i;
0723 
0724     if (data->flags & MMC_DATA_WRITE)
0725         cmd_cfg |= CMD_CFG_DATA_WR;
0726 
0727     if (data->blocks > 1) {
0728         cmd_cfg |= CMD_CFG_BLOCK_MODE;
0729         meson_mmc_set_blksz(mmc, data->blksz);
0730     }
0731 
0732     for_each_sg(data->sg, sg, data->sg_count, i) {
0733         unsigned int len = sg_dma_len(sg);
0734 
0735         if (data->blocks > 1)
0736             len /= data->blksz;
0737 
0738         desc[i].cmd_cfg = cmd_cfg;
0739         desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
0740         if (i > 0)
0741             desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
0742         desc[i].cmd_arg = host->cmd->arg;
0743         desc[i].cmd_resp = 0;
0744         desc[i].cmd_data = sg_dma_address(sg);
0745     }
0746     desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
0747 
0748     dma_wmb(); /* ensure descriptor is written before kicked */
0749     start = host->descs_dma_addr | START_DESC_BUSY;
0750     writel(start, host->regs + SD_EMMC_START);
0751 }
0752 
0753 /* local sg copy for dram_access_quirk */
0754 static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data,
0755                   size_t buflen, bool to_buffer)
0756 {
0757     unsigned int sg_flags = SG_MITER_ATOMIC;
0758     struct scatterlist *sgl = data->sg;
0759     unsigned int nents = data->sg_len;
0760     struct sg_mapping_iter miter;
0761     unsigned int offset = 0;
0762 
0763     if (to_buffer)
0764         sg_flags |= SG_MITER_FROM_SG;
0765     else
0766         sg_flags |= SG_MITER_TO_SG;
0767 
0768     sg_miter_start(&miter, sgl, nents, sg_flags);
0769 
0770     while ((offset < buflen) && sg_miter_next(&miter)) {
0771         unsigned int buf_offset = 0;
0772         unsigned int len, left;
0773         u32 *buf = miter.addr;
0774 
0775         len = min(miter.length, buflen - offset);
0776         left = len;
0777 
0778         if (to_buffer) {
0779             do {
0780                 writel(*buf++, host->bounce_iomem_buf + offset + buf_offset);
0781 
0782                 buf_offset += 4;
0783                 left -= 4;
0784             } while (left);
0785         } else {
0786             do {
0787                 *buf++ = readl(host->bounce_iomem_buf + offset + buf_offset);
0788 
0789                 buf_offset += 4;
0790                 left -= 4;
0791             } while (left);
0792         }
0793 
0794         offset += len;
0795     }
0796 
0797     sg_miter_stop(&miter);
0798 }
0799 
0800 static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
0801 {
0802     struct meson_host *host = mmc_priv(mmc);
0803     struct mmc_data *data = cmd->data;
0804     u32 cmd_cfg = 0, cmd_data = 0;
0805     unsigned int xfer_bytes = 0;
0806 
0807     /* Setup descriptors */
0808     dma_rmb();
0809 
0810     host->cmd = cmd;
0811 
0812     cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
0813     cmd_cfg |= CMD_CFG_OWNER;  /* owned by CPU */
0814     cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */
0815 
0816     meson_mmc_set_response_bits(cmd, &cmd_cfg);
0817 
0818     /* data? */
0819     if (data) {
0820         data->bytes_xfered = 0;
0821         cmd_cfg |= CMD_CFG_DATA_IO;
0822         cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
0823                       ilog2(meson_mmc_get_timeout_msecs(data)));
0824 
0825         if (meson_mmc_desc_chain_mode(data)) {
0826             meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
0827             return;
0828         }
0829 
0830         if (data->blocks > 1) {
0831             cmd_cfg |= CMD_CFG_BLOCK_MODE;
0832             cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
0833                           data->blocks);
0834             meson_mmc_set_blksz(mmc, data->blksz);
0835         } else {
0836             cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
0837         }
0838 
0839         xfer_bytes = data->blksz * data->blocks;
0840         if (data->flags & MMC_DATA_WRITE) {
0841             cmd_cfg |= CMD_CFG_DATA_WR;
0842             WARN_ON(xfer_bytes > host->bounce_buf_size);
0843             if (host->dram_access_quirk)
0844                 meson_mmc_copy_buffer(host, data, xfer_bytes, true);
0845             else
0846                 sg_copy_to_buffer(data->sg, data->sg_len,
0847                           host->bounce_buf, xfer_bytes);
0848             dma_wmb();
0849         }
0850 
0851         cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
0852     } else {
0853         cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
0854                       ilog2(SD_EMMC_CMD_TIMEOUT));
0855     }
0856 
0857     /* Last descriptor */
0858     cmd_cfg |= CMD_CFG_END_OF_CHAIN;
0859     writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
0860     writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
0861     writel(0, host->regs + SD_EMMC_CMD_RSP);
0862     wmb(); /* ensure descriptor is written before kicked */
0863     writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
0864 }
0865 
0866 static int meson_mmc_validate_dram_access(struct mmc_host *mmc, struct mmc_data *data)
0867 {
0868     struct scatterlist *sg;
0869     int i;
0870 
0871     /* Reject request if any element offset or size is not 32bit aligned */
0872     for_each_sg(data->sg, sg, data->sg_len, i) {
0873         if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
0874             !IS_ALIGNED(sg->length, sizeof(u32))) {
0875             dev_err(mmc_dev(mmc), "unaligned sg offset %u len %u\n",
0876                 data->sg->offset, data->sg->length);
0877             return -EINVAL;
0878         }
0879     }
0880 
0881     return 0;
0882 }
0883 
0884 static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
0885 {
0886     struct meson_host *host = mmc_priv(mmc);
0887     host->needs_pre_post_req = mrq->data &&
0888             !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
0889 
0890     /*
0891      * The memory at the end of the controller used as bounce buffer for
0892      * the dram_access_quirk only accepts 32bit read/write access,
0893      * check the aligment and length of the data before starting the request.
0894      */
0895     if (host->dram_access_quirk && mrq->data) {
0896         mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data);
0897         if (mrq->cmd->error) {
0898             mmc_request_done(mmc, mrq);
0899             return;
0900         }
0901     }
0902 
0903     if (host->needs_pre_post_req) {
0904         meson_mmc_get_transfer_mode(mmc, mrq);
0905         if (!meson_mmc_desc_chain_mode(mrq->data))
0906             host->needs_pre_post_req = false;
0907     }
0908 
0909     if (host->needs_pre_post_req)
0910         meson_mmc_pre_req(mmc, mrq);
0911 
0912     /* Stop execution */
0913     writel(0, host->regs + SD_EMMC_START);
0914 
0915     meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
0916 }
0917 
0918 static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
0919 {
0920     struct meson_host *host = mmc_priv(mmc);
0921 
0922     if (cmd->flags & MMC_RSP_136) {
0923         cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
0924         cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
0925         cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
0926         cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
0927     } else if (cmd->flags & MMC_RSP_PRESENT) {
0928         cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
0929     }
0930 }
0931 
0932 static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
0933 {
0934     struct meson_host *host = dev_id;
0935     struct mmc_command *cmd;
0936     struct mmc_data *data;
0937     u32 irq_en, status, raw_status;
0938     irqreturn_t ret = IRQ_NONE;
0939 
0940     irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
0941     raw_status = readl(host->regs + SD_EMMC_STATUS);
0942     status = raw_status & irq_en;
0943 
0944     if (!status) {
0945         dev_dbg(host->dev,
0946             "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n",
0947              irq_en, raw_status);
0948         return IRQ_NONE;
0949     }
0950 
0951     if (WARN_ON(!host) || WARN_ON(!host->cmd))
0952         return IRQ_NONE;
0953 
0954     /* ack all raised interrupts */
0955     writel(status, host->regs + SD_EMMC_STATUS);
0956 
0957     cmd = host->cmd;
0958     data = cmd->data;
0959     cmd->error = 0;
0960     if (status & IRQ_CRC_ERR) {
0961         dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
0962         cmd->error = -EILSEQ;
0963         ret = IRQ_WAKE_THREAD;
0964         goto out;
0965     }
0966 
0967     if (status & IRQ_TIMEOUTS) {
0968         dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
0969         cmd->error = -ETIMEDOUT;
0970         ret = IRQ_WAKE_THREAD;
0971         goto out;
0972     }
0973 
0974     meson_mmc_read_resp(host->mmc, cmd);
0975 
0976     if (status & IRQ_SDIO) {
0977         dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
0978         ret = IRQ_HANDLED;
0979     }
0980 
0981     if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
0982         if (data && !cmd->error)
0983             data->bytes_xfered = data->blksz * data->blocks;
0984         if (meson_mmc_bounce_buf_read(data) ||
0985             meson_mmc_get_next_command(cmd))
0986             ret = IRQ_WAKE_THREAD;
0987         else
0988             ret = IRQ_HANDLED;
0989     }
0990 
0991 out:
0992     if (cmd->error) {
0993         /* Stop desc in case of errors */
0994         u32 start = readl(host->regs + SD_EMMC_START);
0995 
0996         start &= ~START_DESC_BUSY;
0997         writel(start, host->regs + SD_EMMC_START);
0998     }
0999 
1000     if (ret == IRQ_HANDLED)
1001         meson_mmc_request_done(host->mmc, cmd->mrq);
1002 
1003     return ret;
1004 }
1005 
1006 static int meson_mmc_wait_desc_stop(struct meson_host *host)
1007 {
1008     u32 status;
1009 
1010     /*
1011      * It may sometimes take a while for it to actually halt. Here, we
1012      * are giving it 5ms to comply
1013      *
1014      * If we don't confirm the descriptor is stopped, it might raise new
1015      * IRQs after we have called mmc_request_done() which is bad.
1016      */
1017 
1018     return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,
1019                   !(status & (STATUS_BUSY | STATUS_DESC_BUSY)),
1020                   100, 5000);
1021 }
1022 
1023 static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
1024 {
1025     struct meson_host *host = dev_id;
1026     struct mmc_command *next_cmd, *cmd = host->cmd;
1027     struct mmc_data *data;
1028     unsigned int xfer_bytes;
1029 
1030     if (WARN_ON(!cmd))
1031         return IRQ_NONE;
1032 
1033     if (cmd->error) {
1034         meson_mmc_wait_desc_stop(host);
1035         meson_mmc_request_done(host->mmc, cmd->mrq);
1036 
1037         return IRQ_HANDLED;
1038     }
1039 
1040     data = cmd->data;
1041     if (meson_mmc_bounce_buf_read(data)) {
1042         xfer_bytes = data->blksz * data->blocks;
1043         WARN_ON(xfer_bytes > host->bounce_buf_size);
1044         if (host->dram_access_quirk)
1045             meson_mmc_copy_buffer(host, data, xfer_bytes, false);
1046         else
1047             sg_copy_from_buffer(data->sg, data->sg_len,
1048                         host->bounce_buf, xfer_bytes);
1049     }
1050 
1051     next_cmd = meson_mmc_get_next_command(cmd);
1052     if (next_cmd)
1053         meson_mmc_start_cmd(host->mmc, next_cmd);
1054     else
1055         meson_mmc_request_done(host->mmc, cmd->mrq);
1056 
1057     return IRQ_HANDLED;
1058 }
1059 
1060 /*
1061  * NOTE: we only need this until the GPIO/pinctrl driver can handle
1062  * interrupts.  For now, the MMC core will use this for polling.
1063  */
1064 static int meson_mmc_get_cd(struct mmc_host *mmc)
1065 {
1066     int status = mmc_gpio_get_cd(mmc);
1067 
1068     if (status == -ENOSYS)
1069         return 1; /* assume present */
1070 
1071     return status;
1072 }
1073 
1074 static void meson_mmc_cfg_init(struct meson_host *host)
1075 {
1076     u32 cfg = 0;
1077 
1078     cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
1079               ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
1080     cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
1081     cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
1082 
1083     /* abort chain on R/W errors */
1084     cfg |= CFG_ERR_ABORT;
1085 
1086     writel(cfg, host->regs + SD_EMMC_CFG);
1087 }
1088 
1089 static int meson_mmc_card_busy(struct mmc_host *mmc)
1090 {
1091     struct meson_host *host = mmc_priv(mmc);
1092     u32 regval;
1093 
1094     regval = readl(host->regs + SD_EMMC_STATUS);
1095 
1096     /* We are only interrested in lines 0 to 3, so mask the other ones */
1097     return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1098 }
1099 
1100 static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1101 {
1102     int ret;
1103 
1104     /* vqmmc regulator is available */
1105     if (!IS_ERR(mmc->supply.vqmmc)) {
1106         /*
1107          * The usual amlogic setup uses a GPIO to switch from one
1108          * regulator to the other. While the voltage ramp up is
1109          * pretty fast, care must be taken when switching from 3.3v
1110          * to 1.8v. Please make sure the regulator framework is aware
1111          * of your own regulator constraints
1112          */
1113         ret = mmc_regulator_set_vqmmc(mmc, ios);
1114         return ret < 0 ? ret : 0;
1115     }
1116 
1117     /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
1118     if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1119         return 0;
1120 
1121     return -EINVAL;
1122 }
1123 
1124 static const struct mmc_host_ops meson_mmc_ops = {
1125     .request    = meson_mmc_request,
1126     .set_ios    = meson_mmc_set_ios,
1127     .get_cd         = meson_mmc_get_cd,
1128     .pre_req    = meson_mmc_pre_req,
1129     .post_req   = meson_mmc_post_req,
1130     .execute_tuning = meson_mmc_resampling_tuning,
1131     .card_busy  = meson_mmc_card_busy,
1132     .start_signal_voltage_switch = meson_mmc_voltage_switch,
1133 };
1134 
1135 static int meson_mmc_probe(struct platform_device *pdev)
1136 {
1137     struct resource *res;
1138     struct meson_host *host;
1139     struct mmc_host *mmc;
1140     int ret;
1141 
1142     mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
1143     if (!mmc)
1144         return -ENOMEM;
1145     host = mmc_priv(mmc);
1146     host->mmc = mmc;
1147     host->dev = &pdev->dev;
1148     dev_set_drvdata(&pdev->dev, host);
1149 
1150     /* The G12A SDIO Controller needs an SRAM bounce buffer */
1151     host->dram_access_quirk = device_property_read_bool(&pdev->dev,
1152                     "amlogic,dram-access-quirk");
1153 
1154     /* Get regulators and the supported OCR mask */
1155     host->vqmmc_enabled = false;
1156     ret = mmc_regulator_get_supply(mmc);
1157     if (ret)
1158         goto free_host;
1159 
1160     ret = mmc_of_parse(mmc);
1161     if (ret) {
1162         if (ret != -EPROBE_DEFER)
1163             dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1164         goto free_host;
1165     }
1166 
1167     host->data = (struct meson_mmc_data *)
1168         of_device_get_match_data(&pdev->dev);
1169     if (!host->data) {
1170         ret = -EINVAL;
1171         goto free_host;
1172     }
1173 
1174     ret = device_reset_optional(&pdev->dev);
1175     if (ret) {
1176         dev_err_probe(&pdev->dev, ret, "device reset failed\n");
1177         goto free_host;
1178     }
1179 
1180     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1181     host->regs = devm_ioremap_resource(&pdev->dev, res);
1182     if (IS_ERR(host->regs)) {
1183         ret = PTR_ERR(host->regs);
1184         goto free_host;
1185     }
1186 
1187     host->irq = platform_get_irq(pdev, 0);
1188     if (host->irq <= 0) {
1189         ret = -EINVAL;
1190         goto free_host;
1191     }
1192 
1193     host->pinctrl = devm_pinctrl_get(&pdev->dev);
1194     if (IS_ERR(host->pinctrl)) {
1195         ret = PTR_ERR(host->pinctrl);
1196         goto free_host;
1197     }
1198 
1199     host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1200                            "clk-gate");
1201     if (IS_ERR(host->pins_clk_gate)) {
1202         dev_warn(&pdev->dev,
1203              "can't get clk-gate pinctrl, using clk_stop bit\n");
1204         host->pins_clk_gate = NULL;
1205     }
1206 
1207     host->core_clk = devm_clk_get(&pdev->dev, "core");
1208     if (IS_ERR(host->core_clk)) {
1209         ret = PTR_ERR(host->core_clk);
1210         goto free_host;
1211     }
1212 
1213     ret = clk_prepare_enable(host->core_clk);
1214     if (ret)
1215         goto free_host;
1216 
1217     ret = meson_mmc_clk_init(host);
1218     if (ret)
1219         goto err_core_clk;
1220 
1221     /* set config to sane default */
1222     meson_mmc_cfg_init(host);
1223 
1224     /* Stop execution */
1225     writel(0, host->regs + SD_EMMC_START);
1226 
1227     /* clear, ack and enable interrupts */
1228     writel(0, host->regs + SD_EMMC_IRQ_EN);
1229     writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1230            host->regs + SD_EMMC_STATUS);
1231     writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1232            host->regs + SD_EMMC_IRQ_EN);
1233 
1234     ret = request_threaded_irq(host->irq, meson_mmc_irq,
1235                    meson_mmc_irq_thread, IRQF_ONESHOT,
1236                    dev_name(&pdev->dev), host);
1237     if (ret)
1238         goto err_init_clk;
1239 
1240     mmc->caps |= MMC_CAP_CMD23;
1241     if (host->dram_access_quirk) {
1242         /* Limit segments to 1 due to low available sram memory */
1243         mmc->max_segs = 1;
1244         /* Limit to the available sram memory */
1245         mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN /
1246                      mmc->max_blk_size;
1247     } else {
1248         mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1249         mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
1250                 sizeof(struct sd_emmc_desc);
1251     }
1252     mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1253     mmc->max_seg_size = mmc->max_req_size;
1254 
1255     /*
1256      * At the moment, we don't know how to reliably enable HS400.
1257      * From the different datasheets, it is not even clear if this mode
1258      * is officially supported by any of the SoCs
1259      */
1260     mmc->caps2 &= ~MMC_CAP2_HS400;
1261 
1262     if (host->dram_access_quirk) {
1263         /*
1264          * The MMC Controller embeds 1,5KiB of internal SRAM
1265          * that can be used to be used as bounce buffer.
1266          * In the case of the G12A SDIO controller, use these
1267          * instead of the DDR memory
1268          */
1269         host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
1270         host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
1271         host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
1272     } else {
1273         /* data bounce buffer */
1274         host->bounce_buf_size = mmc->max_req_size;
1275         host->bounce_buf =
1276             dmam_alloc_coherent(host->dev, host->bounce_buf_size,
1277                         &host->bounce_dma_addr, GFP_KERNEL);
1278         if (host->bounce_buf == NULL) {
1279             dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1280             ret = -ENOMEM;
1281             goto err_free_irq;
1282         }
1283     }
1284 
1285     host->descs = dmam_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1286                       &host->descs_dma_addr, GFP_KERNEL);
1287     if (!host->descs) {
1288         dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1289         ret = -ENOMEM;
1290         goto err_free_irq;
1291     }
1292 
1293     mmc->ops = &meson_mmc_ops;
1294     mmc_add_host(mmc);
1295 
1296     return 0;
1297 
1298 err_free_irq:
1299     free_irq(host->irq, host);
1300 err_init_clk:
1301     clk_disable_unprepare(host->mmc_clk);
1302 err_core_clk:
1303     clk_disable_unprepare(host->core_clk);
1304 free_host:
1305     mmc_free_host(mmc);
1306     return ret;
1307 }
1308 
1309 static int meson_mmc_remove(struct platform_device *pdev)
1310 {
1311     struct meson_host *host = dev_get_drvdata(&pdev->dev);
1312 
1313     mmc_remove_host(host->mmc);
1314 
1315     /* disable interrupts */
1316     writel(0, host->regs + SD_EMMC_IRQ_EN);
1317     free_irq(host->irq, host);
1318 
1319     clk_disable_unprepare(host->mmc_clk);
1320     clk_disable_unprepare(host->core_clk);
1321 
1322     mmc_free_host(host->mmc);
1323     return 0;
1324 }
1325 
1326 static const struct meson_mmc_data meson_gx_data = {
1327     .tx_delay_mask  = CLK_V2_TX_DELAY_MASK,
1328     .rx_delay_mask  = CLK_V2_RX_DELAY_MASK,
1329     .always_on  = CLK_V2_ALWAYS_ON,
1330     .adjust     = SD_EMMC_ADJUST,
1331 };
1332 
1333 static const struct meson_mmc_data meson_axg_data = {
1334     .tx_delay_mask  = CLK_V3_TX_DELAY_MASK,
1335     .rx_delay_mask  = CLK_V3_RX_DELAY_MASK,
1336     .always_on  = CLK_V3_ALWAYS_ON,
1337     .adjust     = SD_EMMC_V3_ADJUST,
1338 };
1339 
1340 static const struct of_device_id meson_mmc_of_match[] = {
1341     { .compatible = "amlogic,meson-gx-mmc",     .data = &meson_gx_data },
1342     { .compatible = "amlogic,meson-gxbb-mmc",   .data = &meson_gx_data },
1343     { .compatible = "amlogic,meson-gxl-mmc",    .data = &meson_gx_data },
1344     { .compatible = "amlogic,meson-gxm-mmc",    .data = &meson_gx_data },
1345     { .compatible = "amlogic,meson-axg-mmc",    .data = &meson_axg_data },
1346     {}
1347 };
1348 MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
1349 
1350 static struct platform_driver meson_mmc_driver = {
1351     .probe      = meson_mmc_probe,
1352     .remove     = meson_mmc_remove,
1353     .driver     = {
1354         .name = DRIVER_NAME,
1355         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1356         .of_match_table = meson_mmc_of_match,
1357     },
1358 };
1359 
1360 module_platform_driver(meson_mmc_driver);
1361 
1362 MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");
1363 MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1364 MODULE_LICENSE("GPL v2");
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