mmc/host/dw_mmc.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Synopsys DesignWare Multimedia Card Interface driver
0004  *  (Based on NXP driver for lpc 31xx)
0005  *
0006  * Copyright (C) 2009 NXP Semiconductors
0007  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
0008  */
0009
0010 #ifndef _DW_MMC_H_
0011 #define _DW_MMC_H_
0012
0013 #include <linux/scatterlist.h>
0014 #include <linux/mmc/core.h>
0015 #include <linux/dmaengine.h>
0016 #include <linux/reset.h>
0017 #include <linux/fault-inject.h>
0018 #include <linux/hrtimer.h>
0019 #include <linux/interrupt.h>
0020
0021 enum dw_mci_state {
0022     STATE_IDLE = 0,
0023     STATE_SENDING_CMD,
0024     STATE_SENDING_DATA,
0025     STATE_DATA_BUSY,
0026     STATE_SENDING_STOP,
0027     STATE_DATA_ERROR,
0028     STATE_SENDING_CMD11,
0029     STATE_WAITING_CMD11_DONE,
0030 };
0031
0032 enum {
0033     EVENT_CMD_COMPLETE = 0,
0034     EVENT_XFER_COMPLETE,
0035     EVENT_DATA_COMPLETE,
0036     EVENT_DATA_ERROR,
0037 };
0038
0039 enum dw_mci_cookie {
0040     COOKIE_UNMAPPED,
0041     COOKIE_PRE_MAPPED,  /* mapped by pre_req() of dwmmc */
0042     COOKIE_MAPPED,      /* mapped by prepare_data() of dwmmc */
0043 };
0044
0045 struct mmc_data;
0046
0047 enum {
0048     TRANS_MODE_PIO = 0,
0049     TRANS_MODE_IDMAC,
0050     TRANS_MODE_EDMAC
0051 };
0052
0053 struct dw_mci_dma_slave {
0054     struct dma_chan *ch;
0055     enum dma_transfer_direction direction;
0056 };
0057
0058 /**
0059  * struct dw_mci - MMC controller state shared between all slots
0060  * @lock: Spinlock protecting the queue and associated data.
0061  * @irq_lock: Spinlock protecting the INTMASK setting.
0062  * @regs: Pointer to MMIO registers.
0063  * @fifo_reg: Pointer to MMIO registers for data FIFO
0064  * @sg: Scatterlist entry currently being processed by PIO code, if any.
0065  * @sg_miter: PIO mapping scatterlist iterator.
0066  * @mrq: The request currently being processed on @slot,
0067  *  or NULL if the controller is idle.
0068  * @cmd: The command currently being sent to the card, or NULL.
0069  * @data: The data currently being transferred, or NULL if no data
0070  *  transfer is in progress.
0071  * @stop_abort: The command currently prepared for stoping transfer.
0072  * @prev_blksz: The former transfer blksz record.
0073  * @timing: Record of current ios timing.
0074  * @use_dma: Which DMA channel is in use for the current transfer, zero
0075  *  denotes PIO mode.
0076  * @using_dma: Whether DMA is in use for the current transfer.
0077  * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
0078  * @sg_dma: Bus address of DMA buffer.
0079  * @sg_cpu: Virtual address of DMA buffer.
0080  * @dma_ops: Pointer to platform-specific DMA callbacks.
0081  * @cmd_status: Snapshot of SR taken upon completion of the current
0082  * @ring_size: Buffer size for idma descriptors.
0083  *  command. Only valid when EVENT_CMD_COMPLETE is pending.
0084  * @dms: structure of slave-dma private data.
0085  * @phy_regs: physical address of controller's register map
0086  * @data_status: Snapshot of SR taken upon completion of the current
0087  *  data transfer. Only valid when EVENT_DATA_COMPLETE or
0088  *  EVENT_DATA_ERROR is pending.
0089  * @stop_cmdr: Value to be loaded into CMDR when the stop command is
0090  *  to be sent.
0091  * @dir_status: Direction of current transfer.
0092  * @tasklet: Tasklet running the request state machine.
0093  * @pending_events: Bitmask of events flagged by the interrupt handler
0094  *  to be processed by the tasklet.
0095  * @completed_events: Bitmask of events which the state machine has
0096  *  processed.
0097  * @state: Tasklet state.
0098  * @queue: List of slots waiting for access to the controller.
0099  * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
0100  *  rate and timeout calculations.
0101  * @current_speed: Configured rate of the controller.
0102  * @minimum_speed: Stored minimum rate of the controller.
0103  * @fifoth_val: The value of FIFOTH register.
0104  * @verid: Denote Version ID.
0105  * @dev: Device associated with the MMC controller.
0106  * @pdata: Platform data associated with the MMC controller.
0107  * @drv_data: Driver specific data for identified variant of the controller
0108  * @priv: Implementation defined private data.
0109  * @biu_clk: Pointer to bus interface unit clock instance.
0110  * @ciu_clk: Pointer to card interface unit clock instance.
0111  * @slot: Slots sharing this MMC controller.
0112  * @fifo_depth: depth of FIFO.
0113  * @data_addr_override: override fifo reg offset with this value.
0114  * @wm_aligned: force fifo watermark equal with data length in PIO mode.
0115  *  Set as true if alignment is needed.
0116  * @data_shift: log2 of FIFO item size.
0117  * @part_buf_start: Start index in part_buf.
0118  * @part_buf_count: Bytes of partial data in part_buf.
0119  * @part_buf: Simple buffer for partial fifo reads/writes.
0120  * @push_data: Pointer to FIFO push function.
0121  * @pull_data: Pointer to FIFO pull function.
0122  * @quirks: Set of quirks that apply to specific versions of the IP.
0123  * @vqmmc_enabled: Status of vqmmc, should be true or false.
0124  * @irq_flags: The flags to be passed to request_irq.
0125  * @irq: The irq value to be passed to request_irq.
0126  * @sdio_id0: Number of slot0 in the SDIO interrupt registers.
0127  * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
0128  * @cto_timer: Timer for broken command transfer over scheme.
0129  * @dto_timer: Timer for broken data transfer over scheme.
0130  *
0131  * Locking
0132  * =======
0133  *
0134  * @lock is a softirq-safe spinlock protecting @queue as well as
0135  * @slot, @mrq and @state. These must always be updated
0136  * at the same time while holding @lock.
0137  * The @mrq field of struct dw_mci_slot is also protected by @lock,
0138  * and must always be written at the same time as the slot is added to
0139  * @queue.
0140  *
0141  * @irq_lock is an irq-safe spinlock protecting the INTMASK register
0142  * to allow the interrupt handler to modify it directly.  Held for only long
0143  * enough to read-modify-write INTMASK and no other locks are grabbed when
0144  * holding this one.
0145  *
0146  * @pending_events and @completed_events are accessed using atomic bit
0147  * operations, so they don't need any locking.
0148  *
0149  * None of the fields touched by the interrupt handler need any
0150  * locking. However, ordering is important: Before EVENT_DATA_ERROR or
0151  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
0152  * interrupts must be disabled and @data_status updated with a
0153  * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
0154  * CMDRDY interrupt must be disabled and @cmd_status updated with a
0155  * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
0156  * bytes_xfered field of @data must be written. This is ensured by
0157  * using barriers.
0158  */
0159 struct dw_mci {
0160     spinlock_t      lock;
0161     spinlock_t      irq_lock;
0162     void __iomem        *regs;
0163     void __iomem        *fifo_reg;
0164     u32         data_addr_override;
0165     bool            wm_aligned;
0166
0167     struct scatterlist  *sg;
0168     struct sg_mapping_iter  sg_miter;
0169
0170     struct mmc_request  *mrq;
0171     struct mmc_command  *cmd;
0172     struct mmc_data     *data;
0173     struct mmc_command  stop_abort;
0174     unsigned int        prev_blksz;
0175     unsigned char       timing;
0176
0177     /* DMA interface members*/
0178     int         use_dma;
0179     int         using_dma;
0180     int         dma_64bit_address;
0181
0182     dma_addr_t      sg_dma;
0183     void            *sg_cpu;
0184     const struct dw_mci_dma_ops *dma_ops;
0185     /* For idmac */
0186     unsigned int        ring_size;
0187
0188     /* For edmac */
0189     struct dw_mci_dma_slave *dms;
0190     /* Registers's physical base address */
0191     resource_size_t     phy_regs;
0192
0193     u32         cmd_status;
0194     u32         data_status;
0195     u32         stop_cmdr;
0196     u32         dir_status;
0197     struct tasklet_struct   tasklet;
0198     unsigned long       pending_events;
0199     unsigned long       completed_events;
0200     enum dw_mci_state   state;
0201     struct list_head    queue;
0202
0203     u32         bus_hz;
0204     u32         current_speed;
0205     u32         minimum_speed;
0206     u32         fifoth_val;
0207     u16         verid;
0208     struct device       *dev;
0209     struct dw_mci_board *pdata;
0210     const struct dw_mci_drv_data    *drv_data;
0211     void            *priv;
0212     struct clk      *biu_clk;
0213     struct clk      *ciu_clk;
0214     struct dw_mci_slot  *slot;
0215
0216     /* FIFO push and pull */
0217     int         fifo_depth;
0218     int         data_shift;
0219     u8          part_buf_start;
0220     u8          part_buf_count;
0221     union {
0222         u16     part_buf16;
0223         u32     part_buf32;
0224         u64     part_buf;
0225     };
0226     void (*push_data)(struct dw_mci *host, void *buf, int cnt);
0227     void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
0228
0229     u32         quirks;
0230     bool            vqmmc_enabled;
0231     unsigned long       irq_flags; /* IRQ flags */
0232     int         irq;
0233
0234     int         sdio_id0;
0235
0236     struct timer_list       cmd11_timer;
0237     struct timer_list       cto_timer;
0238     struct timer_list       dto_timer;
0239
0240 #ifdef CONFIG_FAULT_INJECTION
0241     struct fault_attr   fail_data_crc;
0242     struct hrtimer      fault_timer;
0243 #endif
0244 };
0245
0246 /* DMA ops for Internal/External DMAC interface */
0247 struct dw_mci_dma_ops {
0248     /* DMA Ops */
0249     int (*init)(struct dw_mci *host);
0250     int (*start)(struct dw_mci *host, unsigned int sg_len);
0251     void (*complete)(void *host);
0252     void (*stop)(struct dw_mci *host);
0253     void (*cleanup)(struct dw_mci *host);
0254     void (*exit)(struct dw_mci *host);
0255 };
0256
0257 struct dma_pdata;
0258
0259 /* Board platform data */
0260 struct dw_mci_board {
0261     unsigned int bus_hz; /* Clock speed at the cclk_in pad */
0262
0263     u32 caps;   /* Capabilities */
0264     u32 caps2;  /* More capabilities */
0265     u32 pm_caps;    /* PM capabilities */
0266     /*
0267      * Override fifo depth. If 0, autodetect it from the FIFOTH register,
0268      * but note that this may not be reliable after a bootloader has used
0269      * it.
0270      */
0271     unsigned int fifo_depth;
0272
0273     /* delay in mS before detecting cards after interrupt */
0274     u32 detect_delay_ms;
0275
0276     struct reset_control *rstc;
0277     struct dw_mci_dma_ops *dma_ops;
0278     struct dma_pdata *data;
0279 };
0280
0281 /* Support for longer data read timeout */
0282 #define DW_MMC_QUIRK_EXTENDED_TMOUT            BIT(0)
0283
0284 #define DW_MMC_240A     0x240a
0285 #define DW_MMC_280A     0x280a
0286
0287 #define SDMMC_CTRL      0x000
0288 #define SDMMC_PWREN     0x004
0289 #define SDMMC_CLKDIV        0x008
0290 #define SDMMC_CLKSRC        0x00c
0291 #define SDMMC_CLKENA        0x010
0292 #define SDMMC_TMOUT     0x014
0293 #define SDMMC_CTYPE     0x018
0294 #define SDMMC_BLKSIZ        0x01c
0295 #define SDMMC_BYTCNT        0x020
0296 #define SDMMC_INTMASK       0x024
0297 #define SDMMC_CMDARG        0x028
0298 #define SDMMC_CMD       0x02c
0299 #define SDMMC_RESP0     0x030
0300 #define SDMMC_RESP1     0x034
0301 #define SDMMC_RESP2     0x038
0302 #define SDMMC_RESP3     0x03c
0303 #define SDMMC_MINTSTS       0x040
0304 #define SDMMC_RINTSTS       0x044
0305 #define SDMMC_STATUS        0x048
0306 #define SDMMC_FIFOTH        0x04c
0307 #define SDMMC_CDETECT       0x050
0308 #define SDMMC_WRTPRT        0x054
0309 #define SDMMC_GPIO      0x058
0310 #define SDMMC_TCBCNT        0x05c
0311 #define SDMMC_TBBCNT        0x060
0312 #define SDMMC_DEBNCE        0x064
0313 #define SDMMC_USRID     0x068
0314 #define SDMMC_VERID     0x06c
0315 #define SDMMC_HCON      0x070
0316 #define SDMMC_UHS_REG       0x074
0317 #define SDMMC_RST_N     0x078
0318 #define SDMMC_BMOD      0x080
0319 #define SDMMC_PLDMND        0x084
0320 #define SDMMC_DBADDR        0x088
0321 #define SDMMC_IDSTS     0x08c
0322 #define SDMMC_IDINTEN       0x090
0323 #define SDMMC_DSCADDR       0x094
0324 #define SDMMC_BUFADDR       0x098
0325 #define SDMMC_CDTHRCTL      0x100
0326 #define SDMMC_UHS_REG_EXT   0x108
0327 #define SDMMC_DDR_REG       0x10c
0328 #define SDMMC_ENABLE_SHIFT  0x110
0329 #define SDMMC_DATA(x)       (x)
0330 /*
0331  * Registers to support idmac 64-bit address mode
0332  */
0333 #define SDMMC_DBADDRL       0x088
0334 #define SDMMC_DBADDRU       0x08c
0335 #define SDMMC_IDSTS64       0x090
0336 #define SDMMC_IDINTEN64     0x094
0337 #define SDMMC_DSCADDRL      0x098
0338 #define SDMMC_DSCADDRU      0x09c
0339 #define SDMMC_BUFADDRL      0x0A0
0340 #define SDMMC_BUFADDRU      0x0A4
0341
0342 /*
0343  * Data offset is difference according to Version
0344  * Lower than 2.40a : data register offest is 0x100
0345  */
0346 #define DATA_OFFSET     0x100
0347 #define DATA_240A_OFFSET    0x200
0348
0349 /* shift bit field */
0350 #define _SBF(f, v)      ((v) << (f))
0351
0352 /* Control register defines */
0353 #define SDMMC_CTRL_USE_IDMAC        BIT(25)
0354 #define SDMMC_CTRL_CEATA_INT_EN     BIT(11)
0355 #define SDMMC_CTRL_SEND_AS_CCSD     BIT(10)
0356 #define SDMMC_CTRL_SEND_CCSD        BIT(9)
0357 #define SDMMC_CTRL_ABRT_READ_DATA   BIT(8)
0358 #define SDMMC_CTRL_SEND_IRQ_RESP    BIT(7)
0359 #define SDMMC_CTRL_READ_WAIT        BIT(6)
0360 #define SDMMC_CTRL_DMA_ENABLE       BIT(5)
0361 #define SDMMC_CTRL_INT_ENABLE       BIT(4)
0362 #define SDMMC_CTRL_DMA_RESET        BIT(2)
0363 #define SDMMC_CTRL_FIFO_RESET       BIT(1)
0364 #define SDMMC_CTRL_RESET        BIT(0)
0365 /* Clock Enable register defines */
0366 #define SDMMC_CLKEN_LOW_PWR     BIT(16)
0367 #define SDMMC_CLKEN_ENABLE      BIT(0)
0368 /* time-out register defines */
0369 #define SDMMC_TMOUT_DATA(n)     _SBF(8, (n))
0370 #define SDMMC_TMOUT_DATA_MSK        0xFFFFFF00
0371 #define SDMMC_TMOUT_RESP(n)     ((n) & 0xFF)
0372 #define SDMMC_TMOUT_RESP_MSK        0xFF
0373 /* card-type register defines */
0374 #define SDMMC_CTYPE_8BIT        BIT(16)
0375 #define SDMMC_CTYPE_4BIT        BIT(0)
0376 #define SDMMC_CTYPE_1BIT        0
0377 /* Interrupt status & mask register defines */
0378 #define SDMMC_INT_SDIO(n)       BIT(16 + (n))
0379 #define SDMMC_INT_EBE           BIT(15)
0380 #define SDMMC_INT_ACD           BIT(14)
0381 #define SDMMC_INT_SBE           BIT(13)
0382 #define SDMMC_INT_HLE           BIT(12)
0383 #define SDMMC_INT_FRUN          BIT(11)
0384 #define SDMMC_INT_HTO           BIT(10)
0385 #define SDMMC_INT_VOLT_SWITCH       BIT(10) /* overloads bit 10! */
0386 #define SDMMC_INT_DRTO          BIT(9)
0387 #define SDMMC_INT_RTO           BIT(8)
0388 #define SDMMC_INT_DCRC          BIT(7)
0389 #define SDMMC_INT_RCRC          BIT(6)
0390 #define SDMMC_INT_RXDR          BIT(5)
0391 #define SDMMC_INT_TXDR          BIT(4)
0392 #define SDMMC_INT_DATA_OVER     BIT(3)
0393 #define SDMMC_INT_CMD_DONE      BIT(2)
0394 #define SDMMC_INT_RESP_ERR      BIT(1)
0395 #define SDMMC_INT_CD            BIT(0)
0396 #define SDMMC_INT_ERROR         0xbfc2
0397 /* Command register defines */
0398 #define SDMMC_CMD_START         BIT(31)
0399 #define SDMMC_CMD_USE_HOLD_REG  BIT(29)
0400 #define SDMMC_CMD_VOLT_SWITCH       BIT(28)
0401 #define SDMMC_CMD_CCS_EXP       BIT(23)
0402 #define SDMMC_CMD_CEATA_RD      BIT(22)
0403 #define SDMMC_CMD_UPD_CLK       BIT(21)
0404 #define SDMMC_CMD_INIT          BIT(15)
0405 #define SDMMC_CMD_STOP          BIT(14)
0406 #define SDMMC_CMD_PRV_DAT_WAIT      BIT(13)
0407 #define SDMMC_CMD_SEND_STOP     BIT(12)
0408 #define SDMMC_CMD_STRM_MODE     BIT(11)
0409 #define SDMMC_CMD_DAT_WR        BIT(10)
0410 #define SDMMC_CMD_DAT_EXP       BIT(9)
0411 #define SDMMC_CMD_RESP_CRC      BIT(8)
0412 #define SDMMC_CMD_RESP_LONG     BIT(7)
0413 #define SDMMC_CMD_RESP_EXP      BIT(6)
0414 #define SDMMC_CMD_INDX(n)       ((n) & 0x1F)
0415 /* Status register defines */
0416 #define SDMMC_GET_FCNT(x)       (((x)>>17) & 0x1FFF)
0417 #define SDMMC_STATUS_DMA_REQ        BIT(31)
0418 #define SDMMC_STATUS_BUSY       BIT(9)
0419 /* FIFOTH register defines */
0420 #define SDMMC_SET_FIFOTH(m, r, t)   (((m) & 0x7) << 28 | \
0421                      ((r) & 0xFFF) << 16 | \
0422                      ((t) & 0xFFF))
0423 /* HCON register defines */
0424 #define DMA_INTERFACE_IDMA      (0x0)
0425 #define DMA_INTERFACE_DWDMA     (0x1)
0426 #define DMA_INTERFACE_GDMA      (0x2)
0427 #define DMA_INTERFACE_NODMA     (0x3)
0428 #define SDMMC_GET_TRANS_MODE(x)     (((x)>>16) & 0x3)
0429 #define SDMMC_GET_SLOT_NUM(x)       ((((x)>>1) & 0x1F) + 1)
0430 #define SDMMC_GET_HDATA_WIDTH(x)    (((x)>>7) & 0x7)
0431 #define SDMMC_GET_ADDR_CONFIG(x)    (((x)>>27) & 0x1)
0432 /* Internal DMAC interrupt defines */
0433 #define SDMMC_IDMAC_INT_AI      BIT(9)
0434 #define SDMMC_IDMAC_INT_NI      BIT(8)
0435 #define SDMMC_IDMAC_INT_CES     BIT(5)
0436 #define SDMMC_IDMAC_INT_DU      BIT(4)
0437 #define SDMMC_IDMAC_INT_FBE     BIT(2)
0438 #define SDMMC_IDMAC_INT_RI      BIT(1)
0439 #define SDMMC_IDMAC_INT_TI      BIT(0)
0440 /* Internal DMAC bus mode bits */
0441 #define SDMMC_IDMAC_ENABLE      BIT(7)
0442 #define SDMMC_IDMAC_FB          BIT(1)
0443 #define SDMMC_IDMAC_SWRESET     BIT(0)
0444 /* H/W reset */
0445 #define SDMMC_RST_HWACTIVE      0x1
0446 /* Version ID register define */
0447 #define SDMMC_GET_VERID(x)      ((x) & 0xFFFF)
0448 /* Card read threshold */
0449 #define SDMMC_SET_THLD(v, x)        (((v) & 0xFFF) << 16 | (x))
0450 #define SDMMC_CARD_WR_THR_EN        BIT(2)
0451 #define SDMMC_CARD_RD_THR_EN        BIT(0)
0452 /* UHS-1 register defines */
0453 #define SDMMC_UHS_DDR           BIT(16)
0454 #define SDMMC_UHS_18V           BIT(0)
0455 /* DDR register defines */
0456 #define SDMMC_DDR_HS400         BIT(31)
0457 /* Enable shift register defines */
0458 #define SDMMC_ENABLE_PHASE      BIT(0)
0459 /* All ctrl reset bits */
0460 #define SDMMC_CTRL_ALL_RESET_FLAGS \
0461     (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
0462
0463 /* FIFO register access macros. These should not change the data endian-ness
0464  * as they are written to memory to be dealt with by the upper layers
0465  */
0466 #define mci_fifo_readw(__reg)   __raw_readw(__reg)
0467 #define mci_fifo_readl(__reg)   __raw_readl(__reg)
0468 #define mci_fifo_readq(__reg)   __raw_readq(__reg)
0469
0470 #define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
0471 #define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
0472 #define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
0473
0474 /* Register access macros */
0475 #define mci_readl(dev, reg)         \
0476     readl_relaxed((dev)->regs + SDMMC_##reg)
0477 #define mci_writel(dev, reg, value)         \
0478     writel_relaxed((value), (dev)->regs + SDMMC_##reg)
0479
0480 /* 16-bit FIFO access macros */
0481 #define mci_readw(dev, reg)         \
0482     readw_relaxed((dev)->regs + SDMMC_##reg)
0483 #define mci_writew(dev, reg, value)         \
0484     writew_relaxed((value), (dev)->regs + SDMMC_##reg)
0485
0486 /* 64-bit FIFO access macros */
0487 #ifdef readq
0488 #define mci_readq(dev, reg)         \
0489     readq_relaxed((dev)->regs + SDMMC_##reg)
0490 #define mci_writeq(dev, reg, value)         \
0491     writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
0492 #else
0493 /*
0494  * Dummy readq implementation for architectures that don't define it.
0495  *
0496  * We would assume that none of these architectures would configure
0497  * the IP block with a 64bit FIFO width, so this code will never be
0498  * executed on those machines. Defining these macros here keeps the
0499  * rest of the code free from ifdefs.
0500  */
0501 #define mci_readq(dev, reg)         \
0502     (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
0503 #define mci_writeq(dev, reg, value)         \
0504     (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
0505
0506 #define __raw_writeq(__value, __reg) \
0507     (*(volatile u64 __force *)(__reg) = (__value))
0508 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
0509 #endif
0510
0511 extern int dw_mci_probe(struct dw_mci *host);
0512 extern void dw_mci_remove(struct dw_mci *host);
0513 #ifdef CONFIG_PM
0514 extern int dw_mci_runtime_suspend(struct device *device);
0515 extern int dw_mci_runtime_resume(struct device *device);
0516 #endif
0517
0518 /**
0519  * struct dw_mci_slot - MMC slot state
0520  * @mmc: The mmc_host representing this slot.
0521  * @host: The MMC controller this slot is using.
0522  * @ctype: Card type for this slot.
0523  * @mrq: mmc_request currently being processed or waiting to be
0524  *  processed, or NULL when the slot is idle.
0525  * @queue_node: List node for placing this node in the @queue list of
0526  *  &struct dw_mci.
0527  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
0528  * @__clk_old: The last clock value that was requested from core.
0529  *  Keeping track of this helps us to avoid spamming the console.
0530  * @flags: Random state bits associated with the slot.
0531  * @id: Number of this slot.
0532  * @sdio_id: Number of this slot in the SDIO interrupt registers.
0533  */
0534 struct dw_mci_slot {
0535     struct mmc_host     *mmc;
0536     struct dw_mci       *host;
0537
0538     u32         ctype;
0539
0540     struct mmc_request  *mrq;
0541     struct list_head    queue_node;
0542
0543     unsigned int        clock;
0544     unsigned int        __clk_old;
0545
0546     unsigned long       flags;
0547 #define DW_MMC_CARD_PRESENT 0
0548 #define DW_MMC_CARD_NEED_INIT   1
0549 #define DW_MMC_CARD_NO_LOW_PWR  2
0550 #define DW_MMC_CARD_NO_USE_HOLD 3
0551 #define DW_MMC_CARD_NEEDS_POLL  4
0552     int         id;
0553     int         sdio_id;
0554 };
0555
0556 /**
0557  * dw_mci driver data - dw-mshc implementation specific driver data.
0558  * @caps: mmc subsystem specified capabilities of the controller(s).
0559  * @num_caps: number of capabilities specified by @caps.
0560  * @common_caps: mmc subsystem specified capabilities applicable to all of
0561  *  the controllers
0562  * @init: early implementation specific initialization.
0563  * @set_ios: handle bus specific extensions.
0564  * @parse_dt: parse implementation specific device tree properties.
0565  * @execute_tuning: implementation specific tuning procedure.
0566  * @set_data_timeout: implementation specific timeout.
0567  * @get_drto_clks: implementation specific cycle count for data read timeout.
0568  *
0569  * Provide controller implementation specific extensions. The usage of this
0570  * data structure is fully optional and usage of each member in this structure
0571  * is optional as well.
0572  */
0573 struct dw_mci_drv_data {
0574     unsigned long   *caps;
0575     u32     num_caps;
0576     u32     common_caps;
0577     int     (*init)(struct dw_mci *host);
0578     void        (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
0579     int     (*parse_dt)(struct dw_mci *host);
0580     int     (*execute_tuning)(struct dw_mci_slot *slot, u32 opcode);
0581     int     (*prepare_hs400_tuning)(struct dw_mci *host,
0582                         struct mmc_ios *ios);
0583     int     (*switch_voltage)(struct mmc_host *mmc,
0584                       struct mmc_ios *ios);
0585     void        (*set_data_timeout)(struct dw_mci *host,
0586                       unsigned int timeout_ns);
0587     u32     (*get_drto_clks)(struct dw_mci *host);
0588 };
0589 #endif /* _DW_MMC_H_ */