mmc/host/dw_mmc-rockchip.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
0004  */
0005
0006 #include <linux/module.h>
0007 #include <linux/platform_device.h>
0008 #include <linux/clk.h>
0009 #include <linux/mmc/host.h>
0010 #include <linux/of_address.h>
0011 #include <linux/mmc/slot-gpio.h>
0012 #include <linux/pm_runtime.h>
0013 #include <linux/slab.h>
0014
0015 #include "dw_mmc.h"
0016 #include "dw_mmc-pltfm.h"
0017
0018 #define RK3288_CLKGEN_DIV   2
0019
0020 static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 };
0021
0022 struct dw_mci_rockchip_priv_data {
0023     struct clk      *drv_clk;
0024     struct clk      *sample_clk;
0025     int         default_sample_phase;
0026     int         num_phases;
0027 };
0028
0029 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
0030 {
0031     struct dw_mci_rockchip_priv_data *priv = host->priv;
0032     int ret;
0033     unsigned int cclkin;
0034     u32 bus_hz;
0035
0036     if (ios->clock == 0)
0037         return;
0038
0039     /*
0040      * cclkin: source clock of mmc controller
0041      * bus_hz: card interface clock generated by CLKGEN
0042      * bus_hz = cclkin / RK3288_CLKGEN_DIV
0043      * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
0044      *
0045      * Note: div can only be 0 or 1, but div must be set to 1 for eMMC
0046      * DDR52 8-bit mode.
0047      */
0048     if (ios->bus_width == MMC_BUS_WIDTH_8 &&
0049         ios->timing == MMC_TIMING_MMC_DDR52)
0050         cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
0051     else
0052         cclkin = ios->clock * RK3288_CLKGEN_DIV;
0053
0054     ret = clk_set_rate(host->ciu_clk, cclkin);
0055     if (ret)
0056         dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret);
0057
0058     bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
0059     if (bus_hz != host->bus_hz) {
0060         host->bus_hz = bus_hz;
0061         /* force dw_mci_setup_bus() */
0062         host->current_speed = 0;
0063     }
0064
0065     /* Make sure we use phases which we can enumerate with */
0066     if (!IS_ERR(priv->sample_clk) && ios->timing <= MMC_TIMING_SD_HS)
0067         clk_set_phase(priv->sample_clk, priv->default_sample_phase);
0068
0069     /*
0070      * Set the drive phase offset based on speed mode to achieve hold times.
0071      *
0072      * NOTE: this is _not_ a value that is dynamically tuned and is also
0073      * _not_ a value that will vary from board to board.  It is a value
0074      * that could vary between different SoC models if they had massively
0075      * different output clock delays inside their dw_mmc IP block (delay_o),
0076      * but since it's OK to overshoot a little we don't need to do complex
0077      * calculations and can pick values that will just work for everyone.
0078      *
0079      * When picking values we'll stick with picking 0/90/180/270 since
0080      * those can be made very accurately on all known Rockchip SoCs.
0081      *
0082      * Note that these values match values from the DesignWare Databook
0083      * tables for the most part except for SDR12 and "ID mode".  For those
0084      * two modes the databook calculations assume a clock in of 50MHz.  As
0085      * seen above, we always use a clock in rate that is exactly the
0086      * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
0087      * back out before the controller sees it).
0088      *
0089      * From measurement of a single device, it appears that delay_o is
0090      * about .5 ns.  Since we try to leave a bit of margin, it's expected
0091      * that numbers here will be fine even with much larger delay_o
0092      * (the 1.4 ns assumed by the DesignWare Databook would result in the
0093      * same results, for instance).
0094      */
0095     if (!IS_ERR(priv->drv_clk)) {
0096         int phase;
0097
0098         /*
0099          * In almost all cases a 90 degree phase offset will provide
0100          * sufficient hold times across all valid input clock rates
0101          * assuming delay_o is not absurd for a given SoC.  We'll use
0102          * that as a default.
0103          */
0104         phase = 90;
0105
0106         switch (ios->timing) {
0107         case MMC_TIMING_MMC_DDR52:
0108             /*
0109              * Since clock in rate with MMC_DDR52 is doubled when
0110              * bus width is 8 we need to double the phase offset
0111              * to get the same timings.
0112              */
0113             if (ios->bus_width == MMC_BUS_WIDTH_8)
0114                 phase = 180;
0115             break;
0116         case MMC_TIMING_UHS_SDR104:
0117         case MMC_TIMING_MMC_HS200:
0118             /*
0119              * In the case of 150 MHz clock (typical max for
0120              * Rockchip SoCs), 90 degree offset will add a delay
0121              * of 1.67 ns.  That will meet min hold time of .8 ns
0122              * as long as clock output delay is < .87 ns.  On
0123              * SoCs measured this seems to be OK, but it doesn't
0124              * hurt to give margin here, so we use 180.
0125              */
0126             phase = 180;
0127             break;
0128         }
0129
0130         clk_set_phase(priv->drv_clk, phase);
0131     }
0132 }
0133
0134 #define TUNING_ITERATION_TO_PHASE(i, num_phases) \
0135         (DIV_ROUND_UP((i) * 360, num_phases))
0136
0137 static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
0138 {
0139     struct dw_mci *host = slot->host;
0140     struct dw_mci_rockchip_priv_data *priv = host->priv;
0141     struct mmc_host *mmc = slot->mmc;
0142     int ret = 0;
0143     int i;
0144     bool v, prev_v = 0, first_v;
0145     struct range_t {
0146         int start;
0147         int end; /* inclusive */
0148     };
0149     struct range_t *ranges;
0150     unsigned int range_count = 0;
0151     int longest_range_len = -1;
0152     int longest_range = -1;
0153     int middle_phase;
0154
0155     if (IS_ERR(priv->sample_clk)) {
0156         dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
0157         return -EIO;
0158     }
0159
0160     ranges = kmalloc_array(priv->num_phases / 2 + 1,
0161                    sizeof(*ranges), GFP_KERNEL);
0162     if (!ranges)
0163         return -ENOMEM;
0164
0165     /* Try each phase and extract good ranges */
0166     for (i = 0; i < priv->num_phases; ) {
0167         clk_set_phase(priv->sample_clk,
0168                   TUNING_ITERATION_TO_PHASE(i, priv->num_phases));
0169
0170         v = !mmc_send_tuning(mmc, opcode, NULL);
0171
0172         if (i == 0)
0173             first_v = v;
0174
0175         if ((!prev_v) && v) {
0176             range_count++;
0177             ranges[range_count-1].start = i;
0178         }
0179         if (v) {
0180             ranges[range_count-1].end = i;
0181             i++;
0182         } else if (i == priv->num_phases - 1) {
0183             /* No extra skipping rules if we're at the end */
0184             i++;
0185         } else {
0186             /*
0187              * No need to check too close to an invalid
0188              * one since testing bad phases is slow.  Skip
0189              * 20 degrees.
0190              */
0191             i += DIV_ROUND_UP(20 * priv->num_phases, 360);
0192
0193             /* Always test the last one */
0194             if (i >= priv->num_phases)
0195                 i = priv->num_phases - 1;
0196         }
0197
0198         prev_v = v;
0199     }
0200
0201     if (range_count == 0) {
0202         dev_warn(host->dev, "All phases bad!");
0203         ret = -EIO;
0204         goto free;
0205     }
0206
0207     /* wrap around case, merge the end points */
0208     if ((range_count > 1) && first_v && v) {
0209         ranges[0].start = ranges[range_count-1].start;
0210         range_count--;
0211     }
0212
0213     if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) {
0214         clk_set_phase(priv->sample_clk, priv->default_sample_phase);
0215         dev_info(host->dev, "All phases work, using default phase %d.",
0216              priv->default_sample_phase);
0217         goto free;
0218     }
0219
0220     /* Find the longest range */
0221     for (i = 0; i < range_count; i++) {
0222         int len = (ranges[i].end - ranges[i].start + 1);
0223
0224         if (len < 0)
0225             len += priv->num_phases;
0226
0227         if (longest_range_len < len) {
0228             longest_range_len = len;
0229             longest_range = i;
0230         }
0231
0232         dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
0233             TUNING_ITERATION_TO_PHASE(ranges[i].start,
0234                           priv->num_phases),
0235             TUNING_ITERATION_TO_PHASE(ranges[i].end,
0236                           priv->num_phases),
0237             len
0238         );
0239     }
0240
0241     dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
0242         TUNING_ITERATION_TO_PHASE(ranges[longest_range].start,
0243                       priv->num_phases),
0244         TUNING_ITERATION_TO_PHASE(ranges[longest_range].end,
0245                       priv->num_phases),
0246         longest_range_len
0247     );
0248
0249     middle_phase = ranges[longest_range].start + longest_range_len / 2;
0250     middle_phase %= priv->num_phases;
0251     dev_info(host->dev, "Successfully tuned phase to %d\n",
0252          TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases));
0253
0254     clk_set_phase(priv->sample_clk,
0255               TUNING_ITERATION_TO_PHASE(middle_phase,
0256                         priv->num_phases));
0257
0258 free:
0259     kfree(ranges);
0260     return ret;
0261 }
0262
0263 static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
0264 {
0265     struct device_node *np = host->dev->of_node;
0266     struct dw_mci_rockchip_priv_data *priv;
0267
0268     priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
0269     if (!priv)
0270         return -ENOMEM;
0271
0272     if (of_property_read_u32(np, "rockchip,desired-num-phases",
0273                     &priv->num_phases))
0274         priv->num_phases = 360;
0275
0276     if (of_property_read_u32(np, "rockchip,default-sample-phase",
0277                     &priv->default_sample_phase))
0278         priv->default_sample_phase = 0;
0279
0280     priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
0281     if (IS_ERR(priv->drv_clk))
0282         dev_dbg(host->dev, "ciu-drive not available\n");
0283
0284     priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
0285     if (IS_ERR(priv->sample_clk))
0286         dev_dbg(host->dev, "ciu-sample not available\n");
0287
0288     host->priv = priv;
0289
0290     return 0;
0291 }
0292
0293 static int dw_mci_rockchip_init(struct dw_mci *host)
0294 {
0295     int ret, i;
0296
0297     /* It is slot 8 on Rockchip SoCs */
0298     host->sdio_id0 = 8;
0299
0300     if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) {
0301         host->bus_hz /= RK3288_CLKGEN_DIV;
0302
0303         /* clock driver will fail if the clock is less than the lowest source clock
0304          * divided by the internal clock divider. Test for the lowest available
0305          * clock and set the minimum freq to clock / clock divider.
0306          */
0307
0308         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
0309             ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV);
0310             if (ret > 0) {
0311                 host->minimum_speed = ret / RK3288_CLKGEN_DIV;
0312                 break;
0313             }
0314         }
0315         if (ret < 0)
0316             dev_warn(host->dev, "no valid minimum freq: %d\n", ret);
0317     }
0318
0319     return 0;
0320 }
0321
0322 static const struct dw_mci_drv_data rk2928_drv_data = {
0323     .init           = dw_mci_rockchip_init,
0324 };
0325
0326 static const struct dw_mci_drv_data rk3288_drv_data = {
0327     .common_caps        = MMC_CAP_CMD23,
0328     .set_ios        = dw_mci_rk3288_set_ios,
0329     .execute_tuning     = dw_mci_rk3288_execute_tuning,
0330     .parse_dt       = dw_mci_rk3288_parse_dt,
0331     .init           = dw_mci_rockchip_init,
0332 };
0333
0334 static const struct of_device_id dw_mci_rockchip_match[] = {
0335     { .compatible = "rockchip,rk2928-dw-mshc",
0336         .data = &rk2928_drv_data },
0337     { .compatible = "rockchip,rk3288-dw-mshc",
0338         .data = &rk3288_drv_data },
0339     {},
0340 };
0341 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
0342
0343 static int dw_mci_rockchip_probe(struct platform_device *pdev)
0344 {
0345     const struct dw_mci_drv_data *drv_data;
0346     const struct of_device_id *match;
0347     int ret;
0348
0349     if (!pdev->dev.of_node)
0350         return -ENODEV;
0351
0352     match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
0353     drv_data = match->data;
0354
0355     pm_runtime_get_noresume(&pdev->dev);
0356     pm_runtime_set_active(&pdev->dev);
0357     pm_runtime_enable(&pdev->dev);
0358     pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
0359     pm_runtime_use_autosuspend(&pdev->dev);
0360
0361     ret = dw_mci_pltfm_register(pdev, drv_data);
0362     if (ret) {
0363         pm_runtime_disable(&pdev->dev);
0364         pm_runtime_set_suspended(&pdev->dev);
0365         pm_runtime_put_noidle(&pdev->dev);
0366         return ret;
0367     }
0368
0369     pm_runtime_put_autosuspend(&pdev->dev);
0370
0371     return 0;
0372 }
0373
0374 static int dw_mci_rockchip_remove(struct platform_device *pdev)
0375 {
0376     pm_runtime_get_sync(&pdev->dev);
0377     pm_runtime_disable(&pdev->dev);
0378     pm_runtime_put_noidle(&pdev->dev);
0379
0380     dw_mci_pltfm_remove(pdev);
0381
0382     return 0;
0383 }
0384
0385 static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
0386     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0387                 pm_runtime_force_resume)
0388     SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
0389                dw_mci_runtime_resume,
0390                NULL)
0391 };
0392
0393 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
0394     .probe      = dw_mci_rockchip_probe,
0395     .remove     = dw_mci_rockchip_remove,
0396     .driver     = {
0397         .name       = "dwmmc_rockchip",
0398         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0399         .of_match_table = dw_mci_rockchip_match,
0400         .pm     = &dw_mci_rockchip_dev_pm_ops,
0401     },
0402 };
0403
0404 module_platform_driver(dw_mci_rockchip_pltfm_driver);
0405
0406 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
0407 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
0408 MODULE_ALIAS("platform:dwmmc_rockchip");
0409 MODULE_LICENSE("GPL v2");