Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2013 Linaro Ltd.
0004  * Copyright (c) 2013 HiSilicon Limited.
0005  */
0006 
0007 #include <linux/bitops.h>
0008 #include <linux/bitfield.h>
0009 #include <linux/clk.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/mmc/host.h>
0012 #include <linux/module.h>
0013 #include <linux/of_address.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/regmap.h>
0017 #include <linux/regulator/consumer.h>
0018 
0019 #include "dw_mmc.h"
0020 #include "dw_mmc-pltfm.h"
0021 
0022 /*
0023  * hi6220 sd only support io voltage 1.8v and 3v
0024  * Also need config AO_SCTRL_SEL18 accordingly
0025  */
0026 #define AO_SCTRL_SEL18      BIT(10)
0027 #define AO_SCTRL_CTRL3      0x40C
0028 
0029 #define DWMMC_SDIO_ID 2
0030 
0031 #define SOC_SCTRL_SCPERCTRL5    (0x314)
0032 #define SDCARD_IO_SEL18         BIT(2)
0033 
0034 #define SDCARD_RD_THRESHOLD  (512)
0035 
0036 #define GENCLK_DIV (7)
0037 
0038 #define GPIO_CLK_ENABLE                   BIT(16)
0039 #define GPIO_CLK_DIV_MASK                 GENMASK(11, 8)
0040 #define GPIO_USE_SAMPLE_DLY_MASK          GENMASK(13, 13)
0041 #define UHS_REG_EXT_SAMPLE_PHASE_MASK     GENMASK(20, 16)
0042 #define UHS_REG_EXT_SAMPLE_DRVPHASE_MASK  GENMASK(25, 21)
0043 #define UHS_REG_EXT_SAMPLE_DLY_MASK       GENMASK(30, 26)
0044 
0045 #define TIMING_MODE     3
0046 #define TIMING_CFG_NUM 10
0047 
0048 #define NUM_PHASES (40)
0049 
0050 #define ENABLE_SHIFT_MIN_SMPL (4)
0051 #define ENABLE_SHIFT_MAX_SMPL (12)
0052 #define USE_DLY_MIN_SMPL (11)
0053 #define USE_DLY_MAX_SMPL (14)
0054 
0055 struct k3_priv {
0056     int ctrl_id;
0057     u32 cur_speed;
0058     struct regmap   *reg;
0059 };
0060 
0061 static unsigned long dw_mci_hi6220_caps[] = {
0062     MMC_CAP_CMD23,
0063     MMC_CAP_CMD23,
0064     0
0065 };
0066 
0067 struct hs_timing {
0068     u32 drv_phase;
0069     u32 smpl_dly;
0070     u32 smpl_phase_max;
0071     u32 smpl_phase_min;
0072 };
0073 
0074 static struct hs_timing hs_timing_cfg[TIMING_MODE][TIMING_CFG_NUM] = {
0075     { /* reserved */ },
0076     { /* SD */
0077         {7, 0, 15, 15,},  /* 0: LEGACY 400k */
0078         {6, 0,  4,  4,},  /* 1: MMC_HS */
0079         {6, 0,  3,  3,},  /* 2: SD_HS */
0080         {6, 0, 15, 15,},  /* 3: SDR12 */
0081         {6, 0,  2,  2,},  /* 4: SDR25 */
0082         {4, 0, 11,  0,},  /* 5: SDR50 */
0083         {6, 4, 15,  0,},  /* 6: SDR104 */
0084         {0},              /* 7: DDR50 */
0085         {0},              /* 8: DDR52 */
0086         {0},              /* 9: HS200 */
0087     },
0088     { /* SDIO */
0089         {7, 0, 15, 15,},  /* 0: LEGACY 400k */
0090         {0},              /* 1: MMC_HS */
0091         {6, 0, 15, 15,},  /* 2: SD_HS */
0092         {6, 0, 15, 15,},  /* 3: SDR12 */
0093         {6, 0,  0,  0,},  /* 4: SDR25 */
0094         {4, 0, 12,  0,},  /* 5: SDR50 */
0095         {5, 4, 15,  0,},  /* 6: SDR104 */
0096         {0},              /* 7: DDR50 */
0097         {0},              /* 8: DDR52 */
0098         {0},              /* 9: HS200 */
0099     }
0100 };
0101 
0102 static void dw_mci_k3_set_ios(struct dw_mci *host, struct mmc_ios *ios)
0103 {
0104     int ret;
0105 
0106     ret = clk_set_rate(host->ciu_clk, ios->clock);
0107     if (ret)
0108         dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
0109 
0110     host->bus_hz = clk_get_rate(host->ciu_clk);
0111 }
0112 
0113 static const struct dw_mci_drv_data k3_drv_data = {
0114     .set_ios        = dw_mci_k3_set_ios,
0115 };
0116 
0117 static int dw_mci_hi6220_parse_dt(struct dw_mci *host)
0118 {
0119     struct k3_priv *priv;
0120 
0121     priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
0122     if (!priv)
0123         return -ENOMEM;
0124 
0125     priv->reg = syscon_regmap_lookup_by_phandle(host->dev->of_node,
0126                      "hisilicon,peripheral-syscon");
0127     if (IS_ERR(priv->reg))
0128         priv->reg = NULL;
0129 
0130     priv->ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
0131     if (priv->ctrl_id < 0)
0132         priv->ctrl_id = 0;
0133 
0134     if (priv->ctrl_id >= TIMING_MODE)
0135         return -EINVAL;
0136 
0137     host->priv = priv;
0138     return 0;
0139 }
0140 
0141 static int dw_mci_hi6220_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
0142 {
0143     struct dw_mci_slot *slot = mmc_priv(mmc);
0144     struct k3_priv *priv;
0145     struct dw_mci *host;
0146     int min_uv, max_uv;
0147     int ret;
0148 
0149     host = slot->host;
0150     priv = host->priv;
0151 
0152     if (!priv || !priv->reg)
0153         return 0;
0154 
0155     if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
0156         ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
0157                      AO_SCTRL_SEL18, 0);
0158         min_uv = 3000000;
0159         max_uv = 3000000;
0160     } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
0161         ret = regmap_update_bits(priv->reg, AO_SCTRL_CTRL3,
0162                      AO_SCTRL_SEL18, AO_SCTRL_SEL18);
0163         min_uv = 1800000;
0164         max_uv = 1800000;
0165     } else {
0166         dev_dbg(host->dev, "voltage not supported\n");
0167         return -EINVAL;
0168     }
0169 
0170     if (ret) {
0171         dev_dbg(host->dev, "switch voltage failed\n");
0172         return ret;
0173     }
0174 
0175     if (IS_ERR_OR_NULL(mmc->supply.vqmmc))
0176         return 0;
0177 
0178     ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
0179     if (ret) {
0180         dev_dbg(host->dev, "Regulator set error %d: %d - %d\n",
0181                  ret, min_uv, max_uv);
0182         return ret;
0183     }
0184 
0185     return 0;
0186 }
0187 
0188 static void dw_mci_hi6220_set_ios(struct dw_mci *host, struct mmc_ios *ios)
0189 {
0190     int ret;
0191     unsigned int clock;
0192 
0193     clock = (ios->clock <= 25000000) ? 25000000 : ios->clock;
0194 
0195     ret = clk_set_rate(host->biu_clk, clock);
0196     if (ret)
0197         dev_warn(host->dev, "failed to set rate %uHz\n", clock);
0198 
0199     host->bus_hz = clk_get_rate(host->biu_clk);
0200 }
0201 
0202 static int dw_mci_hi6220_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
0203 {
0204     return 0;
0205 }
0206 
0207 static const struct dw_mci_drv_data hi6220_data = {
0208     .caps           = dw_mci_hi6220_caps,
0209     .num_caps       = ARRAY_SIZE(dw_mci_hi6220_caps),
0210     .switch_voltage     = dw_mci_hi6220_switch_voltage,
0211     .set_ios        = dw_mci_hi6220_set_ios,
0212     .parse_dt       = dw_mci_hi6220_parse_dt,
0213     .execute_tuning     = dw_mci_hi6220_execute_tuning,
0214 };
0215 
0216 static void dw_mci_hs_set_timing(struct dw_mci *host, int timing,
0217                      int smpl_phase)
0218 {
0219     u32 drv_phase;
0220     u32 smpl_dly;
0221     u32 use_smpl_dly = 0;
0222     u32 enable_shift = 0;
0223     u32 reg_value;
0224     int ctrl_id;
0225     struct k3_priv *priv;
0226 
0227     priv = host->priv;
0228     ctrl_id = priv->ctrl_id;
0229 
0230     drv_phase = hs_timing_cfg[ctrl_id][timing].drv_phase;
0231     smpl_dly   = hs_timing_cfg[ctrl_id][timing].smpl_dly;
0232     if (smpl_phase == -1)
0233         smpl_phase = (hs_timing_cfg[ctrl_id][timing].smpl_phase_max +
0234                  hs_timing_cfg[ctrl_id][timing].smpl_phase_min) / 2;
0235 
0236     switch (timing) {
0237     case MMC_TIMING_UHS_SDR104:
0238         if (smpl_phase >= USE_DLY_MIN_SMPL &&
0239                 smpl_phase <= USE_DLY_MAX_SMPL)
0240             use_smpl_dly = 1;
0241         fallthrough;
0242     case MMC_TIMING_UHS_SDR50:
0243         if (smpl_phase >= ENABLE_SHIFT_MIN_SMPL &&
0244                 smpl_phase <= ENABLE_SHIFT_MAX_SMPL)
0245             enable_shift = 1;
0246         break;
0247     }
0248 
0249     mci_writel(host, GPIO, 0x0);
0250     usleep_range(5, 10);
0251 
0252     reg_value = FIELD_PREP(UHS_REG_EXT_SAMPLE_PHASE_MASK, smpl_phase) |
0253             FIELD_PREP(UHS_REG_EXT_SAMPLE_DLY_MASK, smpl_dly) |
0254             FIELD_PREP(UHS_REG_EXT_SAMPLE_DRVPHASE_MASK, drv_phase);
0255     mci_writel(host, UHS_REG_EXT, reg_value);
0256 
0257     mci_writel(host, ENABLE_SHIFT, enable_shift);
0258 
0259     reg_value = FIELD_PREP(GPIO_CLK_DIV_MASK, GENCLK_DIV) |
0260                  FIELD_PREP(GPIO_USE_SAMPLE_DLY_MASK, use_smpl_dly);
0261     mci_writel(host, GPIO, (unsigned int)reg_value | GPIO_CLK_ENABLE);
0262 
0263     /* We should delay 1ms wait for timing setting finished. */
0264     usleep_range(1000, 2000);
0265 }
0266 
0267 static int dw_mci_hi3660_init(struct dw_mci *host)
0268 {
0269     mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(SDCARD_RD_THRESHOLD,
0270             SDMMC_CARD_RD_THR_EN));
0271 
0272     dw_mci_hs_set_timing(host, MMC_TIMING_LEGACY, -1);
0273     host->bus_hz /= (GENCLK_DIV + 1);
0274 
0275     return 0;
0276 }
0277 
0278 static int dw_mci_set_sel18(struct dw_mci *host, bool set)
0279 {
0280     int ret;
0281     unsigned int val;
0282     struct k3_priv *priv;
0283 
0284     priv = host->priv;
0285 
0286     val = set ? SDCARD_IO_SEL18 : 0;
0287     ret = regmap_update_bits(priv->reg, SOC_SCTRL_SCPERCTRL5,
0288                  SDCARD_IO_SEL18, val);
0289     if (ret) {
0290         dev_err(host->dev, "sel18 %u error\n", val);
0291         return ret;
0292     }
0293 
0294     return 0;
0295 }
0296 
0297 static void dw_mci_hi3660_set_ios(struct dw_mci *host, struct mmc_ios *ios)
0298 {
0299     int ret;
0300     unsigned long wanted;
0301     unsigned long actual;
0302     struct k3_priv *priv = host->priv;
0303 
0304     if (!ios->clock || ios->clock == priv->cur_speed)
0305         return;
0306 
0307     wanted = ios->clock * (GENCLK_DIV + 1);
0308     ret = clk_set_rate(host->ciu_clk, wanted);
0309     if (ret) {
0310         dev_err(host->dev, "failed to set rate %luHz\n", wanted);
0311         return;
0312     }
0313     actual = clk_get_rate(host->ciu_clk);
0314 
0315     dw_mci_hs_set_timing(host, ios->timing, -1);
0316     host->bus_hz = actual / (GENCLK_DIV + 1);
0317     host->current_speed = 0;
0318     priv->cur_speed = host->bus_hz;
0319 }
0320 
0321 static int dw_mci_get_best_clksmpl(unsigned int sample_flag)
0322 {
0323     int i;
0324     int interval;
0325     unsigned int v;
0326     unsigned int len;
0327     unsigned int range_start = 0;
0328     unsigned int range_length = 0;
0329     unsigned int middle_range = 0;
0330 
0331     if (!sample_flag)
0332         return -EIO;
0333 
0334     if (~sample_flag == 0)
0335         return 0;
0336 
0337     i = ffs(sample_flag) - 1;
0338 
0339     /*
0340     * A clock cycle is divided into 32 phases,
0341     * each of which is represented by a bit,
0342     * finding the optimal phase.
0343     */
0344     while (i < 32) {
0345         v = ror32(sample_flag, i);
0346         len = ffs(~v) - 1;
0347 
0348         if (len > range_length) {
0349             range_length = len;
0350             range_start = i;
0351         }
0352 
0353         interval = ffs(v >> len) - 1;
0354         if (interval < 0)
0355             break;
0356 
0357         i += len + interval;
0358     }
0359 
0360     middle_range = range_start + range_length / 2;
0361     if (middle_range >= 32)
0362         middle_range %= 32;
0363 
0364     return middle_range;
0365 }
0366 
0367 static int dw_mci_hi3660_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
0368 {
0369     int i = 0;
0370     struct dw_mci *host = slot->host;
0371     struct mmc_host *mmc = slot->mmc;
0372     int smpl_phase = 0;
0373     u32 tuning_sample_flag = 0;
0374     int best_clksmpl = 0;
0375 
0376     for (i = 0; i < NUM_PHASES; ++i, ++smpl_phase) {
0377         smpl_phase %= 32;
0378 
0379         mci_writel(host, TMOUT, ~0);
0380         dw_mci_hs_set_timing(host, mmc->ios.timing, smpl_phase);
0381 
0382         if (!mmc_send_tuning(mmc, opcode, NULL))
0383             tuning_sample_flag |= (1 << smpl_phase);
0384         else
0385             tuning_sample_flag &= ~(1 << smpl_phase);
0386     }
0387 
0388     best_clksmpl = dw_mci_get_best_clksmpl(tuning_sample_flag);
0389     if (best_clksmpl < 0) {
0390         dev_err(host->dev, "All phases bad!\n");
0391         return -EIO;
0392     }
0393 
0394     dw_mci_hs_set_timing(host, mmc->ios.timing, best_clksmpl);
0395 
0396     dev_info(host->dev, "tuning ok best_clksmpl %u tuning_sample_flag %x\n",
0397          best_clksmpl, tuning_sample_flag);
0398     return 0;
0399 }
0400 
0401 static int dw_mci_hi3660_switch_voltage(struct mmc_host *mmc,
0402                     struct mmc_ios *ios)
0403 {
0404     int ret = 0;
0405     struct dw_mci_slot *slot = mmc_priv(mmc);
0406     struct k3_priv *priv;
0407     struct dw_mci *host;
0408 
0409     host = slot->host;
0410     priv = host->priv;
0411 
0412     if (!priv || !priv->reg)
0413         return 0;
0414 
0415     if (priv->ctrl_id == DWMMC_SDIO_ID)
0416         return 0;
0417 
0418     if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
0419         ret = dw_mci_set_sel18(host, 0);
0420     else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
0421         ret = dw_mci_set_sel18(host, 1);
0422     if (ret)
0423         return ret;
0424 
0425     if (!IS_ERR(mmc->supply.vqmmc)) {
0426         ret = mmc_regulator_set_vqmmc(mmc, ios);
0427         if (ret < 0) {
0428             dev_err(host->dev, "Regulator set error %d\n", ret);
0429             return ret;
0430         }
0431     }
0432 
0433     return 0;
0434 }
0435 
0436 static const struct dw_mci_drv_data hi3660_data = {
0437     .init = dw_mci_hi3660_init,
0438     .set_ios = dw_mci_hi3660_set_ios,
0439     .parse_dt = dw_mci_hi6220_parse_dt,
0440     .execute_tuning = dw_mci_hi3660_execute_tuning,
0441     .switch_voltage  = dw_mci_hi3660_switch_voltage,
0442 };
0443 
0444 static const struct of_device_id dw_mci_k3_match[] = {
0445     { .compatible = "hisilicon,hi3660-dw-mshc", .data = &hi3660_data, },
0446     { .compatible = "hisilicon,hi4511-dw-mshc", .data = &k3_drv_data, },
0447     { .compatible = "hisilicon,hi6220-dw-mshc", .data = &hi6220_data, },
0448     {},
0449 };
0450 MODULE_DEVICE_TABLE(of, dw_mci_k3_match);
0451 
0452 static int dw_mci_k3_probe(struct platform_device *pdev)
0453 {
0454     const struct dw_mci_drv_data *drv_data;
0455     const struct of_device_id *match;
0456 
0457     match = of_match_node(dw_mci_k3_match, pdev->dev.of_node);
0458     drv_data = match->data;
0459 
0460     return dw_mci_pltfm_register(pdev, drv_data);
0461 }
0462 
0463 static const struct dev_pm_ops dw_mci_k3_dev_pm_ops = {
0464     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0465                 pm_runtime_force_resume)
0466     SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
0467                dw_mci_runtime_resume,
0468                NULL)
0469 };
0470 
0471 static struct platform_driver dw_mci_k3_pltfm_driver = {
0472     .probe      = dw_mci_k3_probe,
0473     .remove     = dw_mci_pltfm_remove,
0474     .driver     = {
0475         .name       = "dwmmc_k3",
0476         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0477         .of_match_table = dw_mci_k3_match,
0478         .pm     = &dw_mci_k3_dev_pm_ops,
0479     },
0480 };
0481 
0482 module_platform_driver(dw_mci_k3_pltfm_driver);
0483 
0484 MODULE_DESCRIPTION("K3 Specific DW-MSHC Driver Extension");
0485 MODULE_LICENSE("GPL v2");
0486 MODULE_ALIAS("platform:dwmmc_k3");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!