mmc/host/dw_mmc-exynos.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
0004  *
0005  * Copyright (C) 2012-2014 Samsung Electronics Co., Ltd.
0006  */
0007
0008 #ifndef _DW_MMC_EXYNOS_H_
0009 #define _DW_MMC_EXYNOS_H_
0010
0011 #define SDMMC_CLKSEL            0x09C
0012 #define SDMMC_CLKSEL64          0x0A8
0013
0014 /* Extended Register's Offset */
0015 #define SDMMC_HS400_DQS_EN      0x180
0016 #define SDMMC_HS400_ASYNC_FIFO_CTRL 0x184
0017 #define SDMMC_HS400_DLINE_CTRL      0x188
0018
0019 /* CLKSEL register defines */
0020 #define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
0021 #define SDMMC_CLKSEL_CCLK_DRIVE(x)  (((x) & 7) << 16)
0022 #define SDMMC_CLKSEL_CCLK_DIVIDER(x)    (((x) & 7) << 24)
0023 #define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
0024 #define SDMMC_CLKSEL_GET_DIV(x)     (((x) >> 24) & 0x7)
0025 #define SDMMC_CLKSEL_UP_SAMPLE(x, y)    (((x) & ~SDMMC_CLKSEL_CCLK_SAMPLE(7)) |\
0026                      SDMMC_CLKSEL_CCLK_SAMPLE(y))
0027 #define SDMMC_CLKSEL_TIMING(x, y, z)    (SDMMC_CLKSEL_CCLK_SAMPLE(x) |  \
0028                      SDMMC_CLKSEL_CCLK_DRIVE(y) |   \
0029                      SDMMC_CLKSEL_CCLK_DIVIDER(z))
0030 #define SDMMC_CLKSEL_TIMING_MASK    SDMMC_CLKSEL_TIMING(0x7, 0x7, 0x7)
0031 #define SDMMC_CLKSEL_WAKEUP_INT     BIT(11)
0032
0033 /* RCLK_EN register defines */
0034 #define DATA_STROBE_EN          BIT(0)
0035 #define AXI_NON_BLOCKING_WR BIT(7)
0036
0037 /* DLINE_CTRL register defines */
0038 #define DQS_CTRL_RD_DELAY(x, y)     (((x) & ~0x3FF) | ((y) & 0x3FF))
0039 #define DQS_CTRL_GET_RD_DELAY(x)    ((x) & 0x3FF)
0040
0041 /* Protector Register */
0042 #define SDMMC_EMMCP_BASE    0x1000
0043 #define SDMMC_MPSECURITY    (SDMMC_EMMCP_BASE + 0x0010)
0044 #define SDMMC_MPSBEGIN0     (SDMMC_EMMCP_BASE + 0x0200)
0045 #define SDMMC_MPSEND0       (SDMMC_EMMCP_BASE + 0x0204)
0046 #define SDMMC_MPSCTRL0      (SDMMC_EMMCP_BASE + 0x020C)
0047
0048 /* SMU control defines */
0049 #define SDMMC_MPSCTRL_SECURE_READ_BIT       BIT(7)
0050 #define SDMMC_MPSCTRL_SECURE_WRITE_BIT      BIT(6)
0051 #define SDMMC_MPSCTRL_NON_SECURE_READ_BIT   BIT(5)
0052 #define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT  BIT(4)
0053 #define SDMMC_MPSCTRL_USE_FUSE_KEY      BIT(3)
0054 #define SDMMC_MPSCTRL_ECB_MODE          BIT(2)
0055 #define SDMMC_MPSCTRL_ENCRYPTION        BIT(1)
0056 #define SDMMC_MPSCTRL_VALID         BIT(0)
0057
0058 /* Maximum number of Ending sector */
0059 #define SDMMC_ENDING_SEC_NR_MAX 0xFFFFFFFF
0060
0061 /* Fixed clock divider */
0062 #define EXYNOS4210_FIXED_CIU_CLK_DIV    2
0063 #define EXYNOS4412_FIXED_CIU_CLK_DIV    4
0064 #define HS400_FIXED_CIU_CLK_DIV     1
0065
0066 /* Minimal required clock frequency for cclkin, unit: HZ */
0067 #define EXYNOS_CCLKIN_MIN   50000000
0068
0069 #endif /* _DW_MMC_EXYNOS_H_ */