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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
0004  *
0005  * Copyright (C) 2012, Samsung Electronics Co., Ltd.
0006  */
0007 
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/clk.h>
0011 #include <linux/mmc/host.h>
0012 #include <linux/mmc/mmc.h>
0013 #include <linux/of.h>
0014 #include <linux/of_gpio.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/slab.h>
0017 
0018 #include "dw_mmc.h"
0019 #include "dw_mmc-pltfm.h"
0020 #include "dw_mmc-exynos.h"
0021 
0022 /* Variations in Exynos specific dw-mshc controller */
0023 enum dw_mci_exynos_type {
0024     DW_MCI_TYPE_EXYNOS4210,
0025     DW_MCI_TYPE_EXYNOS4412,
0026     DW_MCI_TYPE_EXYNOS5250,
0027     DW_MCI_TYPE_EXYNOS5420,
0028     DW_MCI_TYPE_EXYNOS5420_SMU,
0029     DW_MCI_TYPE_EXYNOS7,
0030     DW_MCI_TYPE_EXYNOS7_SMU,
0031     DW_MCI_TYPE_ARTPEC8,
0032 };
0033 
0034 /* Exynos implementation specific driver private data */
0035 struct dw_mci_exynos_priv_data {
0036     enum dw_mci_exynos_type     ctrl_type;
0037     u8              ciu_div;
0038     u32             sdr_timing;
0039     u32             ddr_timing;
0040     u32             hs400_timing;
0041     u32             tuned_sample;
0042     u32             cur_speed;
0043     u32             dqs_delay;
0044     u32             saved_dqs_en;
0045     u32             saved_strobe_ctrl;
0046 };
0047 
0048 static struct dw_mci_exynos_compatible {
0049     char                *compatible;
0050     enum dw_mci_exynos_type     ctrl_type;
0051 } exynos_compat[] = {
0052     {
0053         .compatible = "samsung,exynos4210-dw-mshc",
0054         .ctrl_type  = DW_MCI_TYPE_EXYNOS4210,
0055     }, {
0056         .compatible = "samsung,exynos4412-dw-mshc",
0057         .ctrl_type  = DW_MCI_TYPE_EXYNOS4412,
0058     }, {
0059         .compatible = "samsung,exynos5250-dw-mshc",
0060         .ctrl_type  = DW_MCI_TYPE_EXYNOS5250,
0061     }, {
0062         .compatible = "samsung,exynos5420-dw-mshc",
0063         .ctrl_type  = DW_MCI_TYPE_EXYNOS5420,
0064     }, {
0065         .compatible = "samsung,exynos5420-dw-mshc-smu",
0066         .ctrl_type  = DW_MCI_TYPE_EXYNOS5420_SMU,
0067     }, {
0068         .compatible = "samsung,exynos7-dw-mshc",
0069         .ctrl_type  = DW_MCI_TYPE_EXYNOS7,
0070     }, {
0071         .compatible = "samsung,exynos7-dw-mshc-smu",
0072         .ctrl_type  = DW_MCI_TYPE_EXYNOS7_SMU,
0073     }, {
0074         .compatible = "axis,artpec8-dw-mshc",
0075         .ctrl_type  = DW_MCI_TYPE_ARTPEC8,
0076     },
0077 };
0078 
0079 static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
0080 {
0081     struct dw_mci_exynos_priv_data *priv = host->priv;
0082 
0083     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
0084         return EXYNOS4412_FIXED_CIU_CLK_DIV;
0085     else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
0086         return EXYNOS4210_FIXED_CIU_CLK_DIV;
0087     else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
0088             priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
0089             priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
0090         return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
0091     else
0092         return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
0093 }
0094 
0095 static void dw_mci_exynos_config_smu(struct dw_mci *host)
0096 {
0097     struct dw_mci_exynos_priv_data *priv = host->priv;
0098 
0099     /*
0100      * If Exynos is provided the Security management,
0101      * set for non-ecryption mode at this time.
0102      */
0103     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
0104         priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
0105         mci_writel(host, MPSBEGIN0, 0);
0106         mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
0107         mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
0108                SDMMC_MPSCTRL_NON_SECURE_READ_BIT |
0109                SDMMC_MPSCTRL_VALID |
0110                SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
0111     }
0112 }
0113 
0114 static int dw_mci_exynos_priv_init(struct dw_mci *host)
0115 {
0116     struct dw_mci_exynos_priv_data *priv = host->priv;
0117 
0118     dw_mci_exynos_config_smu(host);
0119 
0120     if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) {
0121         priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
0122         priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN);
0123         priv->saved_dqs_en |= AXI_NON_BLOCKING_WR;
0124         mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en);
0125         if (!priv->dqs_delay)
0126             priv->dqs_delay =
0127                 DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
0128     }
0129 
0130     if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) {
0131         /* Quirk needed for the ARTPEC-8 SoC */
0132         host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT;
0133     }
0134 
0135     host->bus_hz /= (priv->ciu_div + 1);
0136 
0137     return 0;
0138 }
0139 
0140 static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
0141 {
0142     struct dw_mci_exynos_priv_data *priv = host->priv;
0143     u32 clksel;
0144 
0145     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
0146         priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
0147         priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
0148         clksel = mci_readl(host, CLKSEL64);
0149     else
0150         clksel = mci_readl(host, CLKSEL);
0151 
0152     clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;
0153 
0154     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
0155         priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
0156         priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
0157         mci_writel(host, CLKSEL64, clksel);
0158     else
0159         mci_writel(host, CLKSEL, clksel);
0160 
0161     /*
0162      * Exynos4412 and Exynos5250 extends the use of CMD register with the
0163      * use of bit 29 (which is reserved on standard MSHC controllers) for
0164      * optionally bypassing the HOLD register for command and data. The
0165      * HOLD register should be bypassed in case there is no phase shift
0166      * applied on CMD/DATA that is sent to the card.
0167      */
0168     if (!SDMMC_CLKSEL_GET_DRV_WD3(clksel) && host->slot)
0169         set_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags);
0170 }
0171 
0172 #ifdef CONFIG_PM
0173 static int dw_mci_exynos_runtime_resume(struct device *dev)
0174 {
0175     struct dw_mci *host = dev_get_drvdata(dev);
0176     int ret;
0177 
0178     ret = dw_mci_runtime_resume(dev);
0179     if (ret)
0180         return ret;
0181 
0182     dw_mci_exynos_config_smu(host);
0183 
0184     return ret;
0185 }
0186 #endif /* CONFIG_PM */
0187 
0188 #ifdef CONFIG_PM_SLEEP
0189 /**
0190  * dw_mci_exynos_suspend_noirq - Exynos-specific suspend code
0191  * @dev: Device to suspend (this device)
0192  *
0193  * This ensures that device will be in runtime active state in
0194  * dw_mci_exynos_resume_noirq after calling pm_runtime_force_resume()
0195  */
0196 static int dw_mci_exynos_suspend_noirq(struct device *dev)
0197 {
0198     pm_runtime_get_noresume(dev);
0199     return pm_runtime_force_suspend(dev);
0200 }
0201 
0202 /**
0203  * dw_mci_exynos_resume_noirq - Exynos-specific resume code
0204  * @dev: Device to resume (this device)
0205  *
0206  * On exynos5420 there is a silicon errata that will sometimes leave the
0207  * WAKEUP_INT bit in the CLKSEL register asserted.  This bit is 1 to indicate
0208  * that it fired and we can clear it by writing a 1 back.  Clear it to prevent
0209  * interrupts from going off constantly.
0210  *
0211  * We run this code on all exynos variants because it doesn't hurt.
0212  */
0213 static int dw_mci_exynos_resume_noirq(struct device *dev)
0214 {
0215     struct dw_mci *host = dev_get_drvdata(dev);
0216     struct dw_mci_exynos_priv_data *priv = host->priv;
0217     u32 clksel;
0218     int ret;
0219 
0220     ret = pm_runtime_force_resume(dev);
0221     if (ret)
0222         return ret;
0223 
0224     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
0225         priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
0226         priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
0227         clksel = mci_readl(host, CLKSEL64);
0228     else
0229         clksel = mci_readl(host, CLKSEL);
0230 
0231     if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
0232         if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
0233             priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
0234             priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
0235             mci_writel(host, CLKSEL64, clksel);
0236         else
0237             mci_writel(host, CLKSEL, clksel);
0238     }
0239 
0240     pm_runtime_put(dev);
0241 
0242     return 0;
0243 }
0244 #endif /* CONFIG_PM_SLEEP */
0245 
0246 static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
0247 {
0248     struct dw_mci_exynos_priv_data *priv = host->priv;
0249     u32 dqs, strobe;
0250 
0251     /*
0252      * Not supported to configure register
0253      * related to HS400
0254      */
0255     if ((priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420) ||
0256         (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)) {
0257         if (timing == MMC_TIMING_MMC_HS400)
0258             dev_warn(host->dev,
0259                  "cannot configure HS400, unsupported chipset\n");
0260         return;
0261     }
0262 
0263     dqs = priv->saved_dqs_en;
0264     strobe = priv->saved_strobe_ctrl;
0265 
0266     if (timing == MMC_TIMING_MMC_HS400) {
0267         dqs |= DATA_STROBE_EN;
0268         strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
0269     } else if (timing == MMC_TIMING_UHS_SDR104) {
0270         dqs &= 0xffffff00;
0271     } else {
0272         dqs &= ~DATA_STROBE_EN;
0273     }
0274 
0275     mci_writel(host, HS400_DQS_EN, dqs);
0276     mci_writel(host, HS400_DLINE_CTRL, strobe);
0277 }
0278 
0279 static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted)
0280 {
0281     struct dw_mci_exynos_priv_data *priv = host->priv;
0282     unsigned long actual;
0283     u8 div;
0284     int ret;
0285     /*
0286      * Don't care if wanted clock is zero or
0287      * ciu clock is unavailable
0288      */
0289     if (!wanted || IS_ERR(host->ciu_clk))
0290         return;
0291 
0292     /* Guaranteed minimum frequency for cclkin */
0293     if (wanted < EXYNOS_CCLKIN_MIN)
0294         wanted = EXYNOS_CCLKIN_MIN;
0295 
0296     if (wanted == priv->cur_speed)
0297         return;
0298 
0299     div = dw_mci_exynos_get_ciu_div(host);
0300     ret = clk_set_rate(host->ciu_clk, wanted * div);
0301     if (ret)
0302         dev_warn(host->dev,
0303             "failed to set clk-rate %u error: %d\n",
0304             wanted * div, ret);
0305     actual = clk_get_rate(host->ciu_clk);
0306     host->bus_hz = actual / div;
0307     priv->cur_speed = wanted;
0308     host->current_speed = 0;
0309 }
0310 
0311 static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
0312 {
0313     struct dw_mci_exynos_priv_data *priv = host->priv;
0314     unsigned int wanted = ios->clock;
0315     u32 timing = ios->timing, clksel;
0316 
0317     switch (timing) {
0318     case MMC_TIMING_MMC_HS400:
0319         /* Update tuned sample timing */
0320         clksel = SDMMC_CLKSEL_UP_SAMPLE(
0321                 priv->hs400_timing, priv->tuned_sample);
0322         wanted <<= 1;
0323         break;
0324     case MMC_TIMING_MMC_DDR52:
0325         clksel = priv->ddr_timing;
0326         /* Should be double rate for DDR mode */
0327         if (ios->bus_width == MMC_BUS_WIDTH_8)
0328             wanted <<= 1;
0329         break;
0330     case MMC_TIMING_UHS_SDR104:
0331     case MMC_TIMING_UHS_SDR50:
0332         clksel = (priv->sdr_timing & 0xfff8ffff) |
0333             (priv->ciu_div << 16);
0334         break;
0335     case MMC_TIMING_UHS_DDR50:
0336         clksel = (priv->ddr_timing & 0xfff8ffff) |
0337             (priv->ciu_div << 16);
0338         break;
0339     default:
0340         clksel = priv->sdr_timing;
0341     }
0342 
0343     /* Set clock timing for the requested speed mode*/
0344     dw_mci_exynos_set_clksel_timing(host, clksel);
0345 
0346     /* Configure setting for HS400 */
0347     dw_mci_exynos_config_hs400(host, timing);
0348 
0349     /* Configure clock rate */
0350     dw_mci_exynos_adjust_clock(host, wanted);
0351 }
0352 
0353 static int dw_mci_exynos_parse_dt(struct dw_mci *host)
0354 {
0355     struct dw_mci_exynos_priv_data *priv;
0356     struct device_node *np = host->dev->of_node;
0357     u32 timing[2];
0358     u32 div = 0;
0359     int idx;
0360     int ret;
0361 
0362     priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
0363     if (!priv)
0364         return -ENOMEM;
0365 
0366     for (idx = 0; idx < ARRAY_SIZE(exynos_compat); idx++) {
0367         if (of_device_is_compatible(np, exynos_compat[idx].compatible))
0368             priv->ctrl_type = exynos_compat[idx].ctrl_type;
0369     }
0370 
0371     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
0372         priv->ciu_div = EXYNOS4412_FIXED_CIU_CLK_DIV - 1;
0373     else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
0374         priv->ciu_div = EXYNOS4210_FIXED_CIU_CLK_DIV - 1;
0375     else {
0376         of_property_read_u32(np, "samsung,dw-mshc-ciu-div", &div);
0377         priv->ciu_div = div;
0378     }
0379 
0380     ret = of_property_read_u32_array(np,
0381             "samsung,dw-mshc-sdr-timing", timing, 2);
0382     if (ret)
0383         return ret;
0384 
0385     priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
0386 
0387     ret = of_property_read_u32_array(np,
0388             "samsung,dw-mshc-ddr-timing", timing, 2);
0389     if (ret)
0390         return ret;
0391 
0392     priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
0393 
0394     ret = of_property_read_u32_array(np,
0395             "samsung,dw-mshc-hs400-timing", timing, 2);
0396     if (!ret && of_property_read_u32(np,
0397                 "samsung,read-strobe-delay", &priv->dqs_delay))
0398         dev_dbg(host->dev,
0399             "read-strobe-delay is not found, assuming usage of default value\n");
0400 
0401     priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1],
0402                         HS400_FIXED_CIU_CLK_DIV);
0403     host->priv = priv;
0404     return 0;
0405 }
0406 
0407 static inline u8 dw_mci_exynos_get_clksmpl(struct dw_mci *host)
0408 {
0409     struct dw_mci_exynos_priv_data *priv = host->priv;
0410 
0411     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
0412         priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
0413         priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
0414         return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
0415     else
0416         return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL));
0417 }
0418 
0419 static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
0420 {
0421     u32 clksel;
0422     struct dw_mci_exynos_priv_data *priv = host->priv;
0423 
0424     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
0425         priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
0426         priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
0427         clksel = mci_readl(host, CLKSEL64);
0428     else
0429         clksel = mci_readl(host, CLKSEL);
0430     clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
0431     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
0432         priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
0433         priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
0434         mci_writel(host, CLKSEL64, clksel);
0435     else
0436         mci_writel(host, CLKSEL, clksel);
0437 }
0438 
0439 static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
0440 {
0441     struct dw_mci_exynos_priv_data *priv = host->priv;
0442     u32 clksel;
0443     u8 sample;
0444 
0445     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
0446         priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
0447         priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
0448         clksel = mci_readl(host, CLKSEL64);
0449     else
0450         clksel = mci_readl(host, CLKSEL);
0451 
0452     sample = (clksel + 1) & 0x7;
0453     clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
0454 
0455     if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
0456         priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
0457         priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
0458         mci_writel(host, CLKSEL64, clksel);
0459     else
0460         mci_writel(host, CLKSEL, clksel);
0461 
0462     return sample;
0463 }
0464 
0465 static s8 dw_mci_exynos_get_best_clksmpl(u8 candidates)
0466 {
0467     const u8 iter = 8;
0468     u8 __c;
0469     s8 i, loc = -1;
0470 
0471     for (i = 0; i < iter; i++) {
0472         __c = ror8(candidates, i);
0473         if ((__c & 0xc7) == 0xc7) {
0474             loc = i;
0475             goto out;
0476         }
0477     }
0478 
0479     for (i = 0; i < iter; i++) {
0480         __c = ror8(candidates, i);
0481         if ((__c & 0x83) == 0x83) {
0482             loc = i;
0483             goto out;
0484         }
0485     }
0486 
0487     /*
0488      * If there is no cadiates value, then it needs to return -EIO.
0489      * If there are candidates values and don't find bset clk sample value,
0490      * then use a first candidates clock sample value.
0491      */
0492     for (i = 0; i < iter; i++) {
0493         __c = ror8(candidates, i);
0494         if ((__c & 0x1) == 0x1) {
0495             loc = i;
0496             goto out;
0497         }
0498     }
0499 out:
0500     return loc;
0501 }
0502 
0503 static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
0504 {
0505     struct dw_mci *host = slot->host;
0506     struct dw_mci_exynos_priv_data *priv = host->priv;
0507     struct mmc_host *mmc = slot->mmc;
0508     u8 start_smpl, smpl, candidates = 0;
0509     s8 found;
0510     int ret = 0;
0511 
0512     start_smpl = dw_mci_exynos_get_clksmpl(host);
0513 
0514     do {
0515         mci_writel(host, TMOUT, ~0);
0516         smpl = dw_mci_exynos_move_next_clksmpl(host);
0517 
0518         if (!mmc_send_tuning(mmc, opcode, NULL))
0519             candidates |= (1 << smpl);
0520 
0521     } while (start_smpl != smpl);
0522 
0523     found = dw_mci_exynos_get_best_clksmpl(candidates);
0524     if (found >= 0) {
0525         dw_mci_exynos_set_clksmpl(host, found);
0526         priv->tuned_sample = found;
0527     } else {
0528         ret = -EIO;
0529         dev_warn(&mmc->class_dev,
0530             "There is no candidates value about clksmpl!\n");
0531     }
0532 
0533     return ret;
0534 }
0535 
0536 static int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
0537                     struct mmc_ios *ios)
0538 {
0539     struct dw_mci_exynos_priv_data *priv = host->priv;
0540 
0541     dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing);
0542     dw_mci_exynos_adjust_clock(host, (ios->clock) << 1);
0543 
0544     return 0;
0545 }
0546 
0547 static void dw_mci_exynos_set_data_timeout(struct dw_mci *host,
0548                        unsigned int timeout_ns)
0549 {
0550     u32 clk_div, tmout;
0551     u64 tmp;
0552     unsigned int tmp2;
0553 
0554     clk_div = (mci_readl(host, CLKDIV) & 0xFF) * 2;
0555     if (clk_div == 0)
0556         clk_div = 1;
0557 
0558     tmp = DIV_ROUND_UP_ULL((u64)timeout_ns * host->bus_hz, NSEC_PER_SEC);
0559     tmp = DIV_ROUND_UP_ULL(tmp, clk_div);
0560 
0561     /* TMOUT[7:0] (RESPONSE_TIMEOUT) */
0562     tmout = 0xFF; /* Set maximum */
0563 
0564     /*
0565      * Extended HW timer (max = 0x6FFFFF2):
0566      * ((TMOUT[10:8] - 1) * 0xFFFFFF + TMOUT[31:11] * 8)
0567      */
0568     if (!tmp || tmp > 0x6FFFFF2)
0569         tmout |= (0xFFFFFF << 8);
0570     else {
0571         /* TMOUT[10:8] */
0572         tmp2 = (((unsigned int)tmp / 0xFFFFFF) + 1) & 0x7;
0573         tmout |= tmp2 << 8;
0574 
0575         /* TMOUT[31:11] */
0576         tmp = tmp - ((tmp2 - 1) * 0xFFFFFF);
0577         tmout |= (tmp & 0xFFFFF8) << 8;
0578     }
0579 
0580     mci_writel(host, TMOUT, tmout);
0581     dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: %#08x",
0582         timeout_ns, tmout >> 8);
0583 }
0584 
0585 static u32 dw_mci_exynos_get_drto_clks(struct dw_mci *host)
0586 {
0587     u32 drto_clks;
0588 
0589     drto_clks = mci_readl(host, TMOUT) >> 8;
0590 
0591     return (((drto_clks & 0x7) - 1) * 0xFFFFFF) + ((drto_clks & 0xFFFFF8));
0592 }
0593 
0594 /* Common capabilities of Exynos4/Exynos5 SoC */
0595 static unsigned long exynos_dwmmc_caps[4] = {
0596     MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA,
0597     0,
0598     0,
0599     0,
0600 };
0601 
0602 static const struct dw_mci_drv_data exynos_drv_data = {
0603     .caps           = exynos_dwmmc_caps,
0604     .num_caps       = ARRAY_SIZE(exynos_dwmmc_caps),
0605     .common_caps        = MMC_CAP_CMD23,
0606     .init           = dw_mci_exynos_priv_init,
0607     .set_ios        = dw_mci_exynos_set_ios,
0608     .parse_dt       = dw_mci_exynos_parse_dt,
0609     .execute_tuning     = dw_mci_exynos_execute_tuning,
0610     .prepare_hs400_tuning   = dw_mci_exynos_prepare_hs400_tuning,
0611 };
0612 
0613 static const struct dw_mci_drv_data artpec_drv_data = {
0614     .common_caps        = MMC_CAP_CMD23,
0615     .init           = dw_mci_exynos_priv_init,
0616     .set_ios        = dw_mci_exynos_set_ios,
0617     .parse_dt       = dw_mci_exynos_parse_dt,
0618     .execute_tuning     = dw_mci_exynos_execute_tuning,
0619     .set_data_timeout       = dw_mci_exynos_set_data_timeout,
0620     .get_drto_clks      = dw_mci_exynos_get_drto_clks,
0621 };
0622 
0623 static const struct of_device_id dw_mci_exynos_match[] = {
0624     { .compatible = "samsung,exynos4412-dw-mshc",
0625             .data = &exynos_drv_data, },
0626     { .compatible = "samsung,exynos5250-dw-mshc",
0627             .data = &exynos_drv_data, },
0628     { .compatible = "samsung,exynos5420-dw-mshc",
0629             .data = &exynos_drv_data, },
0630     { .compatible = "samsung,exynos5420-dw-mshc-smu",
0631             .data = &exynos_drv_data, },
0632     { .compatible = "samsung,exynos7-dw-mshc",
0633             .data = &exynos_drv_data, },
0634     { .compatible = "samsung,exynos7-dw-mshc-smu",
0635             .data = &exynos_drv_data, },
0636     { .compatible = "axis,artpec8-dw-mshc",
0637             .data = &artpec_drv_data, },
0638     {},
0639 };
0640 MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);
0641 
0642 static int dw_mci_exynos_probe(struct platform_device *pdev)
0643 {
0644     const struct dw_mci_drv_data *drv_data;
0645     const struct of_device_id *match;
0646     int ret;
0647 
0648     match = of_match_node(dw_mci_exynos_match, pdev->dev.of_node);
0649     drv_data = match->data;
0650 
0651     pm_runtime_get_noresume(&pdev->dev);
0652     pm_runtime_set_active(&pdev->dev);
0653     pm_runtime_enable(&pdev->dev);
0654 
0655     ret = dw_mci_pltfm_register(pdev, drv_data);
0656     if (ret) {
0657         pm_runtime_disable(&pdev->dev);
0658         pm_runtime_set_suspended(&pdev->dev);
0659         pm_runtime_put_noidle(&pdev->dev);
0660 
0661         return ret;
0662     }
0663 
0664     return 0;
0665 }
0666 
0667 static int dw_mci_exynos_remove(struct platform_device *pdev)
0668 {
0669     pm_runtime_disable(&pdev->dev);
0670     pm_runtime_set_suspended(&pdev->dev);
0671     pm_runtime_put_noidle(&pdev->dev);
0672 
0673     dw_mci_pltfm_remove(pdev);
0674 
0675     return 0;
0676 }
0677 
0678 static const struct dev_pm_ops dw_mci_exynos_pmops = {
0679     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dw_mci_exynos_suspend_noirq,
0680                       dw_mci_exynos_resume_noirq)
0681     SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
0682                dw_mci_exynos_runtime_resume,
0683                NULL)
0684 };
0685 
0686 static struct platform_driver dw_mci_exynos_pltfm_driver = {
0687     .probe      = dw_mci_exynos_probe,
0688     .remove     = dw_mci_exynos_remove,
0689     .driver     = {
0690         .name       = "dwmmc_exynos",
0691         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0692         .of_match_table = dw_mci_exynos_match,
0693         .pm     = &dw_mci_exynos_pmops,
0694     },
0695 };
0696 
0697 module_platform_driver(dw_mci_exynos_pltfm_driver);
0698 
0699 MODULE_DESCRIPTION("Samsung Specific DW-MSHC Driver Extension");
0700 MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com");
0701 MODULE_LICENSE("GPL v2");
0702 MODULE_ALIAS("platform:dwmmc_exynos");
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