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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver
0004  *
0005  * Copyright (C) 2006 Texas Instruments.
0006  *       Original author: Purushotam Kumar
0007  * Copyright (C) 2009 David Brownell
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/ioport.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/clk.h>
0014 #include <linux/err.h>
0015 #include <linux/cpufreq.h>
0016 #include <linux/mmc/host.h>
0017 #include <linux/io.h>
0018 #include <linux/irq.h>
0019 #include <linux/delay.h>
0020 #include <linux/dmaengine.h>
0021 #include <linux/dma-mapping.h>
0022 #include <linux/mmc/mmc.h>
0023 #include <linux/of.h>
0024 #include <linux/of_device.h>
0025 #include <linux/mmc/slot-gpio.h>
0026 #include <linux/interrupt.h>
0027 
0028 #include <linux/platform_data/mmc-davinci.h>
0029 
0030 /*
0031  * Register Definitions
0032  */
0033 #define DAVINCI_MMCCTL       0x00 /* Control Register                  */
0034 #define DAVINCI_MMCCLK       0x04 /* Memory Clock Control Register     */
0035 #define DAVINCI_MMCST0       0x08 /* Status Register 0                 */
0036 #define DAVINCI_MMCST1       0x0C /* Status Register 1                 */
0037 #define DAVINCI_MMCIM        0x10 /* Interrupt Mask Register           */
0038 #define DAVINCI_MMCTOR       0x14 /* Response Time-Out Register        */
0039 #define DAVINCI_MMCTOD       0x18 /* Data Read Time-Out Register       */
0040 #define DAVINCI_MMCBLEN      0x1C /* Block Length Register             */
0041 #define DAVINCI_MMCNBLK      0x20 /* Number of Blocks Register         */
0042 #define DAVINCI_MMCNBLC      0x24 /* Number of Blocks Counter Register */
0043 #define DAVINCI_MMCDRR       0x28 /* Data Receive Register             */
0044 #define DAVINCI_MMCDXR       0x2C /* Data Transmit Register            */
0045 #define DAVINCI_MMCCMD       0x30 /* Command Register                  */
0046 #define DAVINCI_MMCARGHL     0x34 /* Argument Register                 */
0047 #define DAVINCI_MMCRSP01     0x38 /* Response Register 0 and 1         */
0048 #define DAVINCI_MMCRSP23     0x3C /* Response Register 0 and 1         */
0049 #define DAVINCI_MMCRSP45     0x40 /* Response Register 0 and 1         */
0050 #define DAVINCI_MMCRSP67     0x44 /* Response Register 0 and 1         */
0051 #define DAVINCI_MMCDRSP      0x48 /* Data Response Register            */
0052 #define DAVINCI_MMCETOK      0x4C
0053 #define DAVINCI_MMCCIDX      0x50 /* Command Index Register            */
0054 #define DAVINCI_MMCCKC       0x54
0055 #define DAVINCI_MMCTORC      0x58
0056 #define DAVINCI_MMCTODC      0x5C
0057 #define DAVINCI_MMCBLNC      0x60
0058 #define DAVINCI_SDIOCTL      0x64
0059 #define DAVINCI_SDIOST0      0x68
0060 #define DAVINCI_SDIOIEN      0x6C
0061 #define DAVINCI_SDIOIST      0x70
0062 #define DAVINCI_MMCFIFOCTL   0x74 /* FIFO Control Register             */
0063 
0064 /* DAVINCI_MMCCTL definitions */
0065 #define MMCCTL_DATRST         (1 << 0)
0066 #define MMCCTL_CMDRST         (1 << 1)
0067 #define MMCCTL_WIDTH_8_BIT    (1 << 8)
0068 #define MMCCTL_WIDTH_4_BIT    (1 << 2)
0069 #define MMCCTL_DATEG_DISABLED (0 << 6)
0070 #define MMCCTL_DATEG_RISING   (1 << 6)
0071 #define MMCCTL_DATEG_FALLING  (2 << 6)
0072 #define MMCCTL_DATEG_BOTH     (3 << 6)
0073 #define MMCCTL_PERMDR_LE      (0 << 9)
0074 #define MMCCTL_PERMDR_BE      (1 << 9)
0075 #define MMCCTL_PERMDX_LE      (0 << 10)
0076 #define MMCCTL_PERMDX_BE      (1 << 10)
0077 
0078 /* DAVINCI_MMCCLK definitions */
0079 #define MMCCLK_CLKEN          (1 << 8)
0080 #define MMCCLK_CLKRT_MASK     (0xFF << 0)
0081 
0082 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
0083 #define MMCST0_DATDNE         BIT(0)    /* data done */
0084 #define MMCST0_BSYDNE         BIT(1)    /* busy done */
0085 #define MMCST0_RSPDNE         BIT(2)    /* command done */
0086 #define MMCST0_TOUTRD         BIT(3)    /* data read timeout */
0087 #define MMCST0_TOUTRS         BIT(4)    /* command response timeout */
0088 #define MMCST0_CRCWR          BIT(5)    /* data write CRC error */
0089 #define MMCST0_CRCRD          BIT(6)    /* data read CRC error */
0090 #define MMCST0_CRCRS          BIT(7)    /* command response CRC error */
0091 #define MMCST0_DXRDY          BIT(9)    /* data transmit ready (fifo empty) */
0092 #define MMCST0_DRRDY          BIT(10)   /* data receive ready (data in fifo)*/
0093 #define MMCST0_DATED          BIT(11)   /* DAT3 edge detect */
0094 #define MMCST0_TRNDNE         BIT(12)   /* transfer done */
0095 
0096 /* DAVINCI_MMCST1 definitions */
0097 #define MMCST1_BUSY           (1 << 0)
0098 
0099 /* DAVINCI_MMCCMD definitions */
0100 #define MMCCMD_CMD_MASK       (0x3F << 0)
0101 #define MMCCMD_PPLEN          (1 << 7)
0102 #define MMCCMD_BSYEXP         (1 << 8)
0103 #define MMCCMD_RSPFMT_MASK    (3 << 9)
0104 #define MMCCMD_RSPFMT_NONE    (0 << 9)
0105 #define MMCCMD_RSPFMT_R1456   (1 << 9)
0106 #define MMCCMD_RSPFMT_R2      (2 << 9)
0107 #define MMCCMD_RSPFMT_R3      (3 << 9)
0108 #define MMCCMD_DTRW           (1 << 11)
0109 #define MMCCMD_STRMTP         (1 << 12)
0110 #define MMCCMD_WDATX          (1 << 13)
0111 #define MMCCMD_INITCK         (1 << 14)
0112 #define MMCCMD_DCLR           (1 << 15)
0113 #define MMCCMD_DMATRIG        (1 << 16)
0114 
0115 /* DAVINCI_MMCFIFOCTL definitions */
0116 #define MMCFIFOCTL_FIFORST    (1 << 0)
0117 #define MMCFIFOCTL_FIFODIR_WR (1 << 1)
0118 #define MMCFIFOCTL_FIFODIR_RD (0 << 1)
0119 #define MMCFIFOCTL_FIFOLEV    (1 << 2) /* 0 = 128 bits, 1 = 256 bits */
0120 #define MMCFIFOCTL_ACCWD_4    (0 << 3) /* access width of 4 bytes    */
0121 #define MMCFIFOCTL_ACCWD_3    (1 << 3) /* access width of 3 bytes    */
0122 #define MMCFIFOCTL_ACCWD_2    (2 << 3) /* access width of 2 bytes    */
0123 #define MMCFIFOCTL_ACCWD_1    (3 << 3) /* access width of 1 byte     */
0124 
0125 /* DAVINCI_SDIOST0 definitions */
0126 #define SDIOST0_DAT1_HI       BIT(0)
0127 
0128 /* DAVINCI_SDIOIEN definitions */
0129 #define SDIOIEN_IOINTEN       BIT(0)
0130 
0131 /* DAVINCI_SDIOIST definitions */
0132 #define SDIOIST_IOINT         BIT(0)
0133 
0134 /* MMCSD Init clock in Hz in opendrain mode */
0135 #define MMCSD_INIT_CLOCK        200000
0136 
0137 /*
0138  * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units,
0139  * and we handle up to MAX_NR_SG segments.  MMC_BLOCK_BOUNCE kicks in only
0140  * for drivers with max_segs == 1, making the segments bigger (64KB)
0141  * than the page or two that's otherwise typical. nr_sg (passed from
0142  * platform data) == 16 gives at least the same throughput boost, using
0143  * EDMA transfer linkage instead of spending CPU time copying pages.
0144  */
0145 #define MAX_CCNT    ((1 << 16) - 1)
0146 
0147 #define MAX_NR_SG   16
0148 
0149 static unsigned rw_threshold = 32;
0150 module_param(rw_threshold, uint, S_IRUGO);
0151 MODULE_PARM_DESC(rw_threshold,
0152         "Read/Write threshold. Default = 32");
0153 
0154 static unsigned poll_threshold = 128;
0155 module_param(poll_threshold, uint, S_IRUGO);
0156 MODULE_PARM_DESC(poll_threshold,
0157          "Polling transaction size threshold. Default = 128");
0158 
0159 static unsigned poll_loopcount = 32;
0160 module_param(poll_loopcount, uint, S_IRUGO);
0161 MODULE_PARM_DESC(poll_loopcount,
0162          "Maximum polling loop count. Default = 32");
0163 
0164 static unsigned use_dma = 1;
0165 module_param(use_dma, uint, 0);
0166 MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1");
0167 
0168 struct mmc_davinci_host {
0169     struct mmc_command *cmd;
0170     struct mmc_data *data;
0171     struct mmc_host *mmc;
0172     struct clk *clk;
0173     unsigned int mmc_input_clk;
0174     void __iomem *base;
0175     struct resource *mem_res;
0176     int mmc_irq, sdio_irq;
0177     unsigned char bus_mode;
0178 
0179 #define DAVINCI_MMC_DATADIR_NONE    0
0180 #define DAVINCI_MMC_DATADIR_READ    1
0181 #define DAVINCI_MMC_DATADIR_WRITE   2
0182     unsigned char data_dir;
0183 
0184     /* buffer is used during PIO of one scatterlist segment, and
0185      * is updated along with buffer_bytes_left.  bytes_left applies
0186      * to all N blocks of the PIO transfer.
0187      */
0188     u8 *buffer;
0189     u32 buffer_bytes_left;
0190     u32 bytes_left;
0191 
0192     struct dma_chan *dma_tx;
0193     struct dma_chan *dma_rx;
0194     bool use_dma;
0195     bool do_dma;
0196     bool sdio_int;
0197     bool active_request;
0198 
0199     /* For PIO we walk scatterlists one segment at a time. */
0200     unsigned int        sg_len;
0201     struct scatterlist *sg;
0202 
0203     /* Version of the MMC/SD controller */
0204     u8 version;
0205     /* for ns in one cycle calculation */
0206     unsigned ns_in_one_cycle;
0207     /* Number of sg segments */
0208     u8 nr_sg;
0209 #ifdef CONFIG_CPU_FREQ
0210     struct notifier_block   freq_transition;
0211 #endif
0212 };
0213 
0214 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id);
0215 
0216 /* PIO only */
0217 static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host)
0218 {
0219     host->buffer_bytes_left = sg_dma_len(host->sg);
0220     host->buffer = sg_virt(host->sg);
0221     if (host->buffer_bytes_left > host->bytes_left)
0222         host->buffer_bytes_left = host->bytes_left;
0223 }
0224 
0225 static void davinci_fifo_data_trans(struct mmc_davinci_host *host,
0226                     unsigned int n)
0227 {
0228     u8 *p;
0229     unsigned int i;
0230 
0231     if (host->buffer_bytes_left == 0) {
0232         host->sg = sg_next(host->data->sg);
0233         mmc_davinci_sg_to_buf(host);
0234     }
0235 
0236     p = host->buffer;
0237     if (n > host->buffer_bytes_left)
0238         n = host->buffer_bytes_left;
0239     host->buffer_bytes_left -= n;
0240     host->bytes_left -= n;
0241 
0242     /* NOTE:  we never transfer more than rw_threshold bytes
0243      * to/from the fifo here; there's no I/O overlap.
0244      * This also assumes that access width( i.e. ACCWD) is 4 bytes
0245      */
0246     if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
0247         for (i = 0; i < (n >> 2); i++) {
0248             writel(*((u32 *)p), host->base + DAVINCI_MMCDXR);
0249             p = p + 4;
0250         }
0251         if (n & 3) {
0252             iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3));
0253             p = p + (n & 3);
0254         }
0255     } else {
0256         for (i = 0; i < (n >> 2); i++) {
0257             *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR);
0258             p  = p + 4;
0259         }
0260         if (n & 3) {
0261             ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3));
0262             p = p + (n & 3);
0263         }
0264     }
0265     host->buffer = p;
0266 }
0267 
0268 static void mmc_davinci_start_command(struct mmc_davinci_host *host,
0269         struct mmc_command *cmd)
0270 {
0271     u32 cmd_reg = 0;
0272     u32 im_val;
0273 
0274     dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n",
0275         cmd->opcode, cmd->arg,
0276         ({ char *s;
0277         switch (mmc_resp_type(cmd)) {
0278         case MMC_RSP_R1:
0279             s = ", R1/R5/R6/R7 response";
0280             break;
0281         case MMC_RSP_R1B:
0282             s = ", R1b response";
0283             break;
0284         case MMC_RSP_R2:
0285             s = ", R2 response";
0286             break;
0287         case MMC_RSP_R3:
0288             s = ", R3/R4 response";
0289             break;
0290         default:
0291             s = ", (R? response)";
0292             break;
0293         } s; }));
0294     host->cmd = cmd;
0295 
0296     switch (mmc_resp_type(cmd)) {
0297     case MMC_RSP_R1B:
0298         /* There's some spec confusion about when R1B is
0299          * allowed, but if the card doesn't issue a BUSY
0300          * then it's harmless for us to allow it.
0301          */
0302         cmd_reg |= MMCCMD_BSYEXP;
0303         fallthrough;
0304     case MMC_RSP_R1:        /* 48 bits, CRC */
0305         cmd_reg |= MMCCMD_RSPFMT_R1456;
0306         break;
0307     case MMC_RSP_R2:        /* 136 bits, CRC */
0308         cmd_reg |= MMCCMD_RSPFMT_R2;
0309         break;
0310     case MMC_RSP_R3:        /* 48 bits, no CRC */
0311         cmd_reg |= MMCCMD_RSPFMT_R3;
0312         break;
0313     default:
0314         cmd_reg |= MMCCMD_RSPFMT_NONE;
0315         dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n",
0316             mmc_resp_type(cmd));
0317         break;
0318     }
0319 
0320     /* Set command index */
0321     cmd_reg |= cmd->opcode;
0322 
0323     /* Enable EDMA transfer triggers */
0324     if (host->do_dma)
0325         cmd_reg |= MMCCMD_DMATRIG;
0326 
0327     if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL &&
0328             host->data_dir == DAVINCI_MMC_DATADIR_READ)
0329         cmd_reg |= MMCCMD_DMATRIG;
0330 
0331     /* Setting whether command involves data transfer or not */
0332     if (cmd->data)
0333         cmd_reg |= MMCCMD_WDATX;
0334 
0335     /* Setting whether data read or write */
0336     if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
0337         cmd_reg |= MMCCMD_DTRW;
0338 
0339     if (host->bus_mode == MMC_BUSMODE_PUSHPULL)
0340         cmd_reg |= MMCCMD_PPLEN;
0341 
0342     /* set Command timeout */
0343     writel(0x1FFF, host->base + DAVINCI_MMCTOR);
0344 
0345     /* Enable interrupt (calculate here, defer until FIFO is stuffed). */
0346     im_val =  MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS;
0347     if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
0348         im_val |= MMCST0_DATDNE | MMCST0_CRCWR;
0349 
0350         if (!host->do_dma)
0351             im_val |= MMCST0_DXRDY;
0352     } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) {
0353         im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD;
0354 
0355         if (!host->do_dma)
0356             im_val |= MMCST0_DRRDY;
0357     }
0358 
0359     /*
0360      * Before non-DMA WRITE commands the controller needs priming:
0361      * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size
0362      */
0363     if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE))
0364         davinci_fifo_data_trans(host, rw_threshold);
0365 
0366     writel(cmd->arg, host->base + DAVINCI_MMCARGHL);
0367     writel(cmd_reg,  host->base + DAVINCI_MMCCMD);
0368 
0369     host->active_request = true;
0370 
0371     if (!host->do_dma && host->bytes_left <= poll_threshold) {
0372         u32 count = poll_loopcount;
0373 
0374         while (host->active_request && count--) {
0375             mmc_davinci_irq(0, host);
0376             cpu_relax();
0377         }
0378     }
0379 
0380     if (host->active_request)
0381         writel(im_val, host->base + DAVINCI_MMCIM);
0382 }
0383 
0384 /*----------------------------------------------------------------------*/
0385 
0386 /* DMA infrastructure */
0387 
0388 static void davinci_abort_dma(struct mmc_davinci_host *host)
0389 {
0390     struct dma_chan *sync_dev;
0391 
0392     if (host->data_dir == DAVINCI_MMC_DATADIR_READ)
0393         sync_dev = host->dma_rx;
0394     else
0395         sync_dev = host->dma_tx;
0396 
0397     dmaengine_terminate_all(sync_dev);
0398 }
0399 
0400 static int mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
0401         struct mmc_data *data)
0402 {
0403     struct dma_chan *chan;
0404     struct dma_async_tx_descriptor *desc;
0405     int ret = 0;
0406 
0407     if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
0408         struct dma_slave_config dma_tx_conf = {
0409             .direction = DMA_MEM_TO_DEV,
0410             .dst_addr = host->mem_res->start + DAVINCI_MMCDXR,
0411             .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
0412             .dst_maxburst =
0413                 rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
0414         };
0415         chan = host->dma_tx;
0416         dmaengine_slave_config(host->dma_tx, &dma_tx_conf);
0417 
0418         desc = dmaengine_prep_slave_sg(host->dma_tx,
0419                 data->sg,
0420                 host->sg_len,
0421                 DMA_MEM_TO_DEV,
0422                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0423         if (!desc) {
0424             dev_dbg(mmc_dev(host->mmc),
0425                 "failed to allocate DMA TX descriptor");
0426             ret = -1;
0427             goto out;
0428         }
0429     } else {
0430         struct dma_slave_config dma_rx_conf = {
0431             .direction = DMA_DEV_TO_MEM,
0432             .src_addr = host->mem_res->start + DAVINCI_MMCDRR,
0433             .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
0434             .src_maxburst =
0435                 rw_threshold / DMA_SLAVE_BUSWIDTH_4_BYTES,
0436         };
0437         chan = host->dma_rx;
0438         dmaengine_slave_config(host->dma_rx, &dma_rx_conf);
0439 
0440         desc = dmaengine_prep_slave_sg(host->dma_rx,
0441                 data->sg,
0442                 host->sg_len,
0443                 DMA_DEV_TO_MEM,
0444                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0445         if (!desc) {
0446             dev_dbg(mmc_dev(host->mmc),
0447                 "failed to allocate DMA RX descriptor");
0448             ret = -1;
0449             goto out;
0450         }
0451     }
0452 
0453     dmaengine_submit(desc);
0454     dma_async_issue_pending(chan);
0455 
0456 out:
0457     return ret;
0458 }
0459 
0460 static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
0461         struct mmc_data *data)
0462 {
0463     int i;
0464     int mask = rw_threshold - 1;
0465     int ret = 0;
0466 
0467     host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
0468                   mmc_get_dma_dir(data));
0469 
0470     /* no individual DMA segment should need a partial FIFO */
0471     for (i = 0; i < host->sg_len; i++) {
0472         if (sg_dma_len(data->sg + i) & mask) {
0473             dma_unmap_sg(mmc_dev(host->mmc),
0474                      data->sg, data->sg_len,
0475                      mmc_get_dma_dir(data));
0476             return -1;
0477         }
0478     }
0479 
0480     host->do_dma = 1;
0481     ret = mmc_davinci_send_dma_request(host, data);
0482 
0483     return ret;
0484 }
0485 
0486 static void davinci_release_dma_channels(struct mmc_davinci_host *host)
0487 {
0488     if (!host->use_dma)
0489         return;
0490 
0491     dma_release_channel(host->dma_tx);
0492     dma_release_channel(host->dma_rx);
0493 }
0494 
0495 static int davinci_acquire_dma_channels(struct mmc_davinci_host *host)
0496 {
0497     host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx");
0498     if (IS_ERR(host->dma_tx)) {
0499         dev_err(mmc_dev(host->mmc), "Can't get dma_tx channel\n");
0500         return PTR_ERR(host->dma_tx);
0501     }
0502 
0503     host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx");
0504     if (IS_ERR(host->dma_rx)) {
0505         dev_err(mmc_dev(host->mmc), "Can't get dma_rx channel\n");
0506         dma_release_channel(host->dma_tx);
0507         return PTR_ERR(host->dma_rx);
0508     }
0509 
0510     return 0;
0511 }
0512 
0513 /*----------------------------------------------------------------------*/
0514 
0515 static void
0516 mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req)
0517 {
0518     int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0;
0519     int timeout;
0520     struct mmc_data *data = req->data;
0521 
0522     if (host->version == MMC_CTLR_VERSION_2)
0523         fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0;
0524 
0525     host->data = data;
0526     if (data == NULL) {
0527         host->data_dir = DAVINCI_MMC_DATADIR_NONE;
0528         writel(0, host->base + DAVINCI_MMCBLEN);
0529         writel(0, host->base + DAVINCI_MMCNBLK);
0530         return;
0531     }
0532 
0533     dev_dbg(mmc_dev(host->mmc), "%s, %d blocks of %d bytes\n",
0534         (data->flags & MMC_DATA_WRITE) ? "write" : "read",
0535         data->blocks, data->blksz);
0536     dev_dbg(mmc_dev(host->mmc), "  DTO %d cycles + %d ns\n",
0537         data->timeout_clks, data->timeout_ns);
0538     timeout = data->timeout_clks +
0539         (data->timeout_ns / host->ns_in_one_cycle);
0540     if (timeout > 0xffff)
0541         timeout = 0xffff;
0542 
0543     writel(timeout, host->base + DAVINCI_MMCTOD);
0544     writel(data->blocks, host->base + DAVINCI_MMCNBLK);
0545     writel(data->blksz, host->base + DAVINCI_MMCBLEN);
0546 
0547     /* Configure the FIFO */
0548     if (data->flags & MMC_DATA_WRITE) {
0549         host->data_dir = DAVINCI_MMC_DATADIR_WRITE;
0550         writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST,
0551             host->base + DAVINCI_MMCFIFOCTL);
0552         writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR,
0553             host->base + DAVINCI_MMCFIFOCTL);
0554     } else {
0555         host->data_dir = DAVINCI_MMC_DATADIR_READ;
0556         writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST,
0557             host->base + DAVINCI_MMCFIFOCTL);
0558         writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD,
0559             host->base + DAVINCI_MMCFIFOCTL);
0560     }
0561 
0562     host->buffer = NULL;
0563     host->bytes_left = data->blocks * data->blksz;
0564 
0565     /* For now we try to use DMA whenever we won't need partial FIFO
0566      * reads or writes, either for the whole transfer (as tested here)
0567      * or for any individual scatterlist segment (tested when we call
0568      * start_dma_transfer).
0569      *
0570      * While we *could* change that, unusual block sizes are rarely
0571      * used.  The occasional fallback to PIO should't hurt.
0572      */
0573     if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0
0574             && mmc_davinci_start_dma_transfer(host, data) == 0) {
0575         /* zero this to ensure we take no PIO paths */
0576         host->bytes_left = 0;
0577     } else {
0578         /* Revert to CPU Copy */
0579         host->sg_len = data->sg_len;
0580         host->sg = host->data->sg;
0581         mmc_davinci_sg_to_buf(host);
0582     }
0583 }
0584 
0585 static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req)
0586 {
0587     struct mmc_davinci_host *host = mmc_priv(mmc);
0588     unsigned long timeout = jiffies + msecs_to_jiffies(900);
0589     u32 mmcst1 = 0;
0590 
0591     /* Card may still be sending BUSY after a previous operation,
0592      * typically some kind of write.  If so, we can't proceed yet.
0593      */
0594     while (time_before(jiffies, timeout)) {
0595         mmcst1  = readl(host->base + DAVINCI_MMCST1);
0596         if (!(mmcst1 & MMCST1_BUSY))
0597             break;
0598         cpu_relax();
0599     }
0600     if (mmcst1 & MMCST1_BUSY) {
0601         dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n");
0602         req->cmd->error = -ETIMEDOUT;
0603         mmc_request_done(mmc, req);
0604         return;
0605     }
0606 
0607     host->do_dma = 0;
0608     mmc_davinci_prepare_data(host, req);
0609     mmc_davinci_start_command(host, req->cmd);
0610 }
0611 
0612 static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host,
0613     unsigned int mmc_req_freq)
0614 {
0615     unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0;
0616 
0617     mmc_pclk = host->mmc_input_clk;
0618     if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq))
0619         mmc_push_pull_divisor = ((unsigned int)mmc_pclk
0620                 / (2 * mmc_req_freq)) - 1;
0621     else
0622         mmc_push_pull_divisor = 0;
0623 
0624     mmc_freq = (unsigned int)mmc_pclk
0625         / (2 * (mmc_push_pull_divisor + 1));
0626 
0627     if (mmc_freq > mmc_req_freq)
0628         mmc_push_pull_divisor = mmc_push_pull_divisor + 1;
0629     /* Convert ns to clock cycles */
0630     if (mmc_req_freq <= 400000)
0631         host->ns_in_one_cycle = (1000000) / (((mmc_pclk
0632                 / (2 * (mmc_push_pull_divisor + 1)))/1000));
0633     else
0634         host->ns_in_one_cycle = (1000000) / (((mmc_pclk
0635                 / (2 * (mmc_push_pull_divisor + 1)))/1000000));
0636 
0637     return mmc_push_pull_divisor;
0638 }
0639 
0640 static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios)
0641 {
0642     unsigned int open_drain_freq = 0, mmc_pclk = 0;
0643     unsigned int mmc_push_pull_freq = 0;
0644     struct mmc_davinci_host *host = mmc_priv(mmc);
0645 
0646     if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
0647         u32 temp;
0648 
0649         /* Ignoring the init clock value passed for fixing the inter
0650          * operability with different cards.
0651          */
0652         open_drain_freq = ((unsigned int)mmc_pclk
0653                 / (2 * MMCSD_INIT_CLOCK)) - 1;
0654 
0655         if (open_drain_freq > 0xFF)
0656             open_drain_freq = 0xFF;
0657 
0658         temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
0659         temp |= open_drain_freq;
0660         writel(temp, host->base + DAVINCI_MMCCLK);
0661 
0662         /* Convert ns to clock cycles */
0663         host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000);
0664     } else {
0665         u32 temp;
0666         mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock);
0667 
0668         if (mmc_push_pull_freq > 0xFF)
0669             mmc_push_pull_freq = 0xFF;
0670 
0671         temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN;
0672         writel(temp, host->base + DAVINCI_MMCCLK);
0673 
0674         udelay(10);
0675 
0676         temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
0677         temp |= mmc_push_pull_freq;
0678         writel(temp, host->base + DAVINCI_MMCCLK);
0679 
0680         writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
0681 
0682         udelay(10);
0683     }
0684 }
0685 
0686 static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0687 {
0688     struct mmc_davinci_host *host = mmc_priv(mmc);
0689     struct platform_device *pdev = to_platform_device(mmc->parent);
0690     struct davinci_mmc_config *config = pdev->dev.platform_data;
0691 
0692     dev_dbg(mmc_dev(host->mmc),
0693         "clock %dHz busmode %d powermode %d Vdd %04x\n",
0694         ios->clock, ios->bus_mode, ios->power_mode,
0695         ios->vdd);
0696 
0697     switch (ios->power_mode) {
0698     case MMC_POWER_OFF:
0699         if (config && config->set_power)
0700             config->set_power(pdev->id, false);
0701         break;
0702     case MMC_POWER_UP:
0703         if (config && config->set_power)
0704             config->set_power(pdev->id, true);
0705         break;
0706     }
0707 
0708     switch (ios->bus_width) {
0709     case MMC_BUS_WIDTH_8:
0710         dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n");
0711         writel((readl(host->base + DAVINCI_MMCCTL) &
0712             ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT,
0713             host->base + DAVINCI_MMCCTL);
0714         break;
0715     case MMC_BUS_WIDTH_4:
0716         dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n");
0717         if (host->version == MMC_CTLR_VERSION_2)
0718             writel((readl(host->base + DAVINCI_MMCCTL) &
0719                 ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT,
0720                 host->base + DAVINCI_MMCCTL);
0721         else
0722             writel(readl(host->base + DAVINCI_MMCCTL) |
0723                 MMCCTL_WIDTH_4_BIT,
0724                 host->base + DAVINCI_MMCCTL);
0725         break;
0726     case MMC_BUS_WIDTH_1:
0727         dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n");
0728         if (host->version == MMC_CTLR_VERSION_2)
0729             writel(readl(host->base + DAVINCI_MMCCTL) &
0730                 ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT),
0731                 host->base + DAVINCI_MMCCTL);
0732         else
0733             writel(readl(host->base + DAVINCI_MMCCTL) &
0734                 ~MMCCTL_WIDTH_4_BIT,
0735                 host->base + DAVINCI_MMCCTL);
0736         break;
0737     }
0738 
0739     calculate_clk_divider(mmc, ios);
0740 
0741     host->bus_mode = ios->bus_mode;
0742     if (ios->power_mode == MMC_POWER_UP) {
0743         unsigned long timeout = jiffies + msecs_to_jiffies(50);
0744         bool lose = true;
0745 
0746         /* Send clock cycles, poll completion */
0747         writel(0, host->base + DAVINCI_MMCARGHL);
0748         writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD);
0749         while (time_before(jiffies, timeout)) {
0750             u32 tmp = readl(host->base + DAVINCI_MMCST0);
0751 
0752             if (tmp & MMCST0_RSPDNE) {
0753                 lose = false;
0754                 break;
0755             }
0756             cpu_relax();
0757         }
0758         if (lose)
0759             dev_warn(mmc_dev(host->mmc), "powerup timeout\n");
0760     }
0761 
0762     /* FIXME on power OFF, reset things ... */
0763 }
0764 
0765 static void
0766 mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data)
0767 {
0768     host->data = NULL;
0769 
0770     if (host->mmc->caps & MMC_CAP_SDIO_IRQ) {
0771         /*
0772          * SDIO Interrupt Detection work-around as suggested by
0773          * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata
0774          * 2.1.6): Signal SDIO interrupt only if it is enabled by core
0775          */
0776         if (host->sdio_int && !(readl(host->base + DAVINCI_SDIOST0) &
0777                     SDIOST0_DAT1_HI)) {
0778             writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
0779             mmc_signal_sdio_irq(host->mmc);
0780         }
0781     }
0782 
0783     if (host->do_dma) {
0784         davinci_abort_dma(host);
0785 
0786         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
0787                  mmc_get_dma_dir(data));
0788         host->do_dma = false;
0789     }
0790     host->data_dir = DAVINCI_MMC_DATADIR_NONE;
0791 
0792     if (!data->stop || (host->cmd && host->cmd->error)) {
0793         mmc_request_done(host->mmc, data->mrq);
0794         writel(0, host->base + DAVINCI_MMCIM);
0795         host->active_request = false;
0796     } else
0797         mmc_davinci_start_command(host, data->stop);
0798 }
0799 
0800 static void mmc_davinci_cmd_done(struct mmc_davinci_host *host,
0801                  struct mmc_command *cmd)
0802 {
0803     host->cmd = NULL;
0804 
0805     if (cmd->flags & MMC_RSP_PRESENT) {
0806         if (cmd->flags & MMC_RSP_136) {
0807             /* response type 2 */
0808             cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01);
0809             cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23);
0810             cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45);
0811             cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
0812         } else {
0813             /* response types 1, 1b, 3, 4, 5, 6 */
0814             cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
0815         }
0816     }
0817 
0818     if (host->data == NULL || cmd->error) {
0819         if (cmd->error == -ETIMEDOUT)
0820             cmd->mrq->cmd->retries = 0;
0821         mmc_request_done(host->mmc, cmd->mrq);
0822         writel(0, host->base + DAVINCI_MMCIM);
0823         host->active_request = false;
0824     }
0825 }
0826 
0827 static inline void mmc_davinci_reset_ctrl(struct mmc_davinci_host *host,
0828                                 int val)
0829 {
0830     u32 temp;
0831 
0832     temp = readl(host->base + DAVINCI_MMCCTL);
0833     if (val)    /* reset */
0834         temp |= MMCCTL_CMDRST | MMCCTL_DATRST;
0835     else        /* enable */
0836         temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST);
0837 
0838     writel(temp, host->base + DAVINCI_MMCCTL);
0839     udelay(10);
0840 }
0841 
0842 static void
0843 davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data)
0844 {
0845     mmc_davinci_reset_ctrl(host, 1);
0846     mmc_davinci_reset_ctrl(host, 0);
0847 }
0848 
0849 static irqreturn_t mmc_davinci_sdio_irq(int irq, void *dev_id)
0850 {
0851     struct mmc_davinci_host *host = dev_id;
0852     unsigned int status;
0853 
0854     status = readl(host->base + DAVINCI_SDIOIST);
0855     if (status & SDIOIST_IOINT) {
0856         dev_dbg(mmc_dev(host->mmc),
0857             "SDIO interrupt status %x\n", status);
0858         writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
0859         mmc_signal_sdio_irq(host->mmc);
0860     }
0861     return IRQ_HANDLED;
0862 }
0863 
0864 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id)
0865 {
0866     struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
0867     unsigned int status, qstatus;
0868     int end_command = 0;
0869     int end_transfer = 0;
0870     struct mmc_data *data = host->data;
0871 
0872     if (host->cmd == NULL && host->data == NULL) {
0873         status = readl(host->base + DAVINCI_MMCST0);
0874         dev_dbg(mmc_dev(host->mmc),
0875             "Spurious interrupt 0x%04x\n", status);
0876         /* Disable the interrupt from mmcsd */
0877         writel(0, host->base + DAVINCI_MMCIM);
0878         return IRQ_NONE;
0879     }
0880 
0881     status = readl(host->base + DAVINCI_MMCST0);
0882     qstatus = status;
0883 
0884     /* handle FIFO first when using PIO for data.
0885      * bytes_left will decrease to zero as I/O progress and status will
0886      * read zero over iteration because this controller status
0887      * register(MMCST0) reports any status only once and it is cleared
0888      * by read. So, it is not unbouned loop even in the case of
0889      * non-dma.
0890      */
0891     if (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) {
0892         unsigned long im_val;
0893 
0894         /*
0895          * If interrupts fire during the following loop, they will be
0896          * handled by the handler, but the PIC will still buffer these.
0897          * As a result, the handler will be called again to serve these
0898          * needlessly. In order to avoid these spurious interrupts,
0899          * keep interrupts masked during the loop.
0900          */
0901         im_val = readl(host->base + DAVINCI_MMCIM);
0902         writel(0, host->base + DAVINCI_MMCIM);
0903 
0904         do {
0905             davinci_fifo_data_trans(host, rw_threshold);
0906             status = readl(host->base + DAVINCI_MMCST0);
0907             qstatus |= status;
0908         } while (host->bytes_left &&
0909              (status & (MMCST0_DXRDY | MMCST0_DRRDY)));
0910 
0911         /*
0912          * If an interrupt is pending, it is assumed it will fire when
0913          * it is unmasked. This assumption is also taken when the MMCIM
0914          * is first set. Otherwise, writing to MMCIM after reading the
0915          * status is race-prone.
0916          */
0917         writel(im_val, host->base + DAVINCI_MMCIM);
0918     }
0919 
0920     if (qstatus & MMCST0_DATDNE) {
0921         /* All blocks sent/received, and CRC checks passed */
0922         if (data != NULL) {
0923             if ((host->do_dma == 0) && (host->bytes_left > 0)) {
0924                 /* if datasize < rw_threshold
0925                  * no RX ints are generated
0926                  */
0927                 davinci_fifo_data_trans(host, host->bytes_left);
0928             }
0929             end_transfer = 1;
0930             data->bytes_xfered = data->blocks * data->blksz;
0931         } else {
0932             dev_err(mmc_dev(host->mmc),
0933                     "DATDNE with no host->data\n");
0934         }
0935     }
0936 
0937     if (qstatus & MMCST0_TOUTRD) {
0938         /* Read data timeout */
0939         data->error = -ETIMEDOUT;
0940         end_transfer = 1;
0941 
0942         dev_dbg(mmc_dev(host->mmc),
0943             "read data timeout, status %x\n",
0944             qstatus);
0945 
0946         davinci_abort_data(host, data);
0947     }
0948 
0949     if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) {
0950         /* Data CRC error */
0951         data->error = -EILSEQ;
0952         end_transfer = 1;
0953 
0954         /* NOTE:  this controller uses CRCWR to report both CRC
0955          * errors and timeouts (on writes).  MMCDRSP values are
0956          * only weakly documented, but 0x9f was clearly a timeout
0957          * case and the two three-bit patterns in various SD specs
0958          * (101, 010) aren't part of it ...
0959          */
0960         if (qstatus & MMCST0_CRCWR) {
0961             u32 temp = readb(host->base + DAVINCI_MMCDRSP);
0962 
0963             if (temp == 0x9f)
0964                 data->error = -ETIMEDOUT;
0965         }
0966         dev_dbg(mmc_dev(host->mmc), "data %s %s error\n",
0967             (qstatus & MMCST0_CRCWR) ? "write" : "read",
0968             (data->error == -ETIMEDOUT) ? "timeout" : "CRC");
0969 
0970         davinci_abort_data(host, data);
0971     }
0972 
0973     if (qstatus & MMCST0_TOUTRS) {
0974         /* Command timeout */
0975         if (host->cmd) {
0976             dev_dbg(mmc_dev(host->mmc),
0977                 "CMD%d timeout, status %x\n",
0978                 host->cmd->opcode, qstatus);
0979             host->cmd->error = -ETIMEDOUT;
0980             if (data) {
0981                 end_transfer = 1;
0982                 davinci_abort_data(host, data);
0983             } else
0984                 end_command = 1;
0985         }
0986     }
0987 
0988     if (qstatus & MMCST0_CRCRS) {
0989         /* Command CRC error */
0990         dev_dbg(mmc_dev(host->mmc), "Command CRC error\n");
0991         if (host->cmd) {
0992             host->cmd->error = -EILSEQ;
0993             end_command = 1;
0994         }
0995     }
0996 
0997     if (qstatus & MMCST0_RSPDNE) {
0998         /* End of command phase */
0999         end_command = host->cmd ? 1 : 0;
1000     }
1001 
1002     if (end_command)
1003         mmc_davinci_cmd_done(host, host->cmd);
1004     if (end_transfer)
1005         mmc_davinci_xfer_done(host, data);
1006     return IRQ_HANDLED;
1007 }
1008 
1009 static int mmc_davinci_get_cd(struct mmc_host *mmc)
1010 {
1011     struct platform_device *pdev = to_platform_device(mmc->parent);
1012     struct davinci_mmc_config *config = pdev->dev.platform_data;
1013 
1014     if (config && config->get_cd)
1015         return config->get_cd(pdev->id);
1016 
1017     return mmc_gpio_get_cd(mmc);
1018 }
1019 
1020 static int mmc_davinci_get_ro(struct mmc_host *mmc)
1021 {
1022     struct platform_device *pdev = to_platform_device(mmc->parent);
1023     struct davinci_mmc_config *config = pdev->dev.platform_data;
1024 
1025     if (config && config->get_ro)
1026         return config->get_ro(pdev->id);
1027 
1028     return mmc_gpio_get_ro(mmc);
1029 }
1030 
1031 static void mmc_davinci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1032 {
1033     struct mmc_davinci_host *host = mmc_priv(mmc);
1034 
1035     if (enable) {
1036         if (!(readl(host->base + DAVINCI_SDIOST0) & SDIOST0_DAT1_HI)) {
1037             writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
1038             mmc_signal_sdio_irq(host->mmc);
1039         } else {
1040             host->sdio_int = true;
1041             writel(readl(host->base + DAVINCI_SDIOIEN) |
1042                    SDIOIEN_IOINTEN, host->base + DAVINCI_SDIOIEN);
1043         }
1044     } else {
1045         host->sdio_int = false;
1046         writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN,
1047                host->base + DAVINCI_SDIOIEN);
1048     }
1049 }
1050 
1051 static const struct mmc_host_ops mmc_davinci_ops = {
1052     .request    = mmc_davinci_request,
1053     .set_ios    = mmc_davinci_set_ios,
1054     .get_cd     = mmc_davinci_get_cd,
1055     .get_ro     = mmc_davinci_get_ro,
1056     .enable_sdio_irq = mmc_davinci_enable_sdio_irq,
1057 };
1058 
1059 /*----------------------------------------------------------------------*/
1060 
1061 #ifdef CONFIG_CPU_FREQ
1062 static int mmc_davinci_cpufreq_transition(struct notifier_block *nb,
1063                      unsigned long val, void *data)
1064 {
1065     struct mmc_davinci_host *host;
1066     unsigned int mmc_pclk;
1067     struct mmc_host *mmc;
1068     unsigned long flags;
1069 
1070     host = container_of(nb, struct mmc_davinci_host, freq_transition);
1071     mmc = host->mmc;
1072     mmc_pclk = clk_get_rate(host->clk);
1073 
1074     if (val == CPUFREQ_POSTCHANGE) {
1075         spin_lock_irqsave(&mmc->lock, flags);
1076         host->mmc_input_clk = mmc_pclk;
1077         calculate_clk_divider(mmc, &mmc->ios);
1078         spin_unlock_irqrestore(&mmc->lock, flags);
1079     }
1080 
1081     return 0;
1082 }
1083 
1084 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1085 {
1086     host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition;
1087 
1088     return cpufreq_register_notifier(&host->freq_transition,
1089                      CPUFREQ_TRANSITION_NOTIFIER);
1090 }
1091 
1092 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1093 {
1094     cpufreq_unregister_notifier(&host->freq_transition,
1095                     CPUFREQ_TRANSITION_NOTIFIER);
1096 }
1097 #else
1098 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1099 {
1100     return 0;
1101 }
1102 
1103 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1104 {
1105 }
1106 #endif
1107 static void init_mmcsd_host(struct mmc_davinci_host *host)
1108 {
1109 
1110     mmc_davinci_reset_ctrl(host, 1);
1111 
1112     writel(0, host->base + DAVINCI_MMCCLK);
1113     writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
1114 
1115     writel(0x1FFF, host->base + DAVINCI_MMCTOR);
1116     writel(0xFFFF, host->base + DAVINCI_MMCTOD);
1117 
1118     mmc_davinci_reset_ctrl(host, 0);
1119 }
1120 
1121 static const struct platform_device_id davinci_mmc_devtype[] = {
1122     {
1123         .name   = "dm6441-mmc",
1124         .driver_data = MMC_CTLR_VERSION_1,
1125     }, {
1126         .name   = "da830-mmc",
1127         .driver_data = MMC_CTLR_VERSION_2,
1128     },
1129     {},
1130 };
1131 MODULE_DEVICE_TABLE(platform, davinci_mmc_devtype);
1132 
1133 static const struct of_device_id davinci_mmc_dt_ids[] = {
1134     {
1135         .compatible = "ti,dm6441-mmc",
1136         .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_1],
1137     },
1138     {
1139         .compatible = "ti,da830-mmc",
1140         .data = &davinci_mmc_devtype[MMC_CTLR_VERSION_2],
1141     },
1142     {},
1143 };
1144 MODULE_DEVICE_TABLE(of, davinci_mmc_dt_ids);
1145 
1146 static int mmc_davinci_parse_pdata(struct mmc_host *mmc)
1147 {
1148     struct platform_device *pdev = to_platform_device(mmc->parent);
1149     struct davinci_mmc_config *pdata = pdev->dev.platform_data;
1150     struct mmc_davinci_host *host;
1151     int ret;
1152 
1153     if (!pdata)
1154         return -EINVAL;
1155 
1156     host = mmc_priv(mmc);
1157     if (!host)
1158         return -EINVAL;
1159 
1160     if (pdata && pdata->nr_sg)
1161         host->nr_sg = pdata->nr_sg - 1;
1162 
1163     if (pdata && (pdata->wires == 4 || pdata->wires == 0))
1164         mmc->caps |= MMC_CAP_4_BIT_DATA;
1165 
1166     if (pdata && (pdata->wires == 8))
1167         mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
1168 
1169     mmc->f_min = 312500;
1170     mmc->f_max = 25000000;
1171     if (pdata && pdata->max_freq)
1172         mmc->f_max = pdata->max_freq;
1173     if (pdata && pdata->caps)
1174         mmc->caps |= pdata->caps;
1175 
1176     /* Register a cd gpio, if there is not one, enable polling */
1177     ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
1178     if (ret == -EPROBE_DEFER)
1179         return ret;
1180     else if (ret)
1181         mmc->caps |= MMC_CAP_NEEDS_POLL;
1182 
1183     ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0);
1184     if (ret == -EPROBE_DEFER)
1185         return ret;
1186 
1187     return 0;
1188 }
1189 
1190 static int davinci_mmcsd_probe(struct platform_device *pdev)
1191 {
1192     struct mmc_davinci_host *host = NULL;
1193     struct mmc_host *mmc = NULL;
1194     struct resource *r, *mem = NULL;
1195     int ret, irq;
1196     size_t mem_size;
1197     const struct platform_device_id *id_entry;
1198 
1199     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1200     if (!r)
1201         return -ENODEV;
1202     irq = platform_get_irq(pdev, 0);
1203     if (irq < 0)
1204         return irq;
1205 
1206     mem_size = resource_size(r);
1207     mem = devm_request_mem_region(&pdev->dev, r->start, mem_size,
1208                       pdev->name);
1209     if (!mem)
1210         return -EBUSY;
1211 
1212     mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev);
1213     if (!mmc)
1214         return -ENOMEM;
1215 
1216     host = mmc_priv(mmc);
1217     host->mmc = mmc;    /* Important */
1218 
1219     host->mem_res = mem;
1220     host->base = devm_ioremap(&pdev->dev, mem->start, mem_size);
1221     if (!host->base) {
1222         ret = -ENOMEM;
1223         goto ioremap_fail;
1224     }
1225 
1226     host->clk = devm_clk_get(&pdev->dev, NULL);
1227     if (IS_ERR(host->clk)) {
1228         ret = PTR_ERR(host->clk);
1229         goto clk_get_fail;
1230     }
1231     ret = clk_prepare_enable(host->clk);
1232     if (ret)
1233         goto clk_prepare_enable_fail;
1234 
1235     host->mmc_input_clk = clk_get_rate(host->clk);
1236 
1237     pdev->id_entry = of_device_get_match_data(&pdev->dev);
1238     if (pdev->id_entry) {
1239         ret = mmc_of_parse(mmc);
1240         if (ret) {
1241             dev_err_probe(&pdev->dev, ret,
1242                       "could not parse of data\n");
1243             goto parse_fail;
1244         }
1245     } else {
1246         ret = mmc_davinci_parse_pdata(mmc);
1247         if (ret) {
1248             dev_err(&pdev->dev,
1249                 "could not parse platform data: %d\n", ret);
1250             goto parse_fail;
1251     }   }
1252 
1253     if (host->nr_sg > MAX_NR_SG || !host->nr_sg)
1254         host->nr_sg = MAX_NR_SG;
1255 
1256     init_mmcsd_host(host);
1257 
1258     host->use_dma = use_dma;
1259     host->mmc_irq = irq;
1260     host->sdio_irq = platform_get_irq(pdev, 1);
1261 
1262     if (host->use_dma) {
1263         ret = davinci_acquire_dma_channels(host);
1264         if (ret == -EPROBE_DEFER)
1265             goto dma_probe_defer;
1266         else if (ret)
1267             host->use_dma = 0;
1268     }
1269 
1270     mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1271 
1272     id_entry = platform_get_device_id(pdev);
1273     if (id_entry)
1274         host->version = id_entry->driver_data;
1275 
1276     mmc->ops = &mmc_davinci_ops;
1277     mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1278 
1279     /* With no iommu coalescing pages, each phys_seg is a hw_seg.
1280      * Each hw_seg uses one EDMA parameter RAM slot, always one
1281      * channel and then usually some linked slots.
1282      */
1283     mmc->max_segs       = MAX_NR_SG;
1284 
1285     /* EDMA limit per hw segment (one or two MBytes) */
1286     mmc->max_seg_size   = MAX_CCNT * rw_threshold;
1287 
1288     /* MMC/SD controller limits for multiblock requests */
1289     mmc->max_blk_size   = 4095;  /* BLEN is 12 bits */
1290     mmc->max_blk_count  = 65535; /* NBLK is 16 bits */
1291     mmc->max_req_size   = mmc->max_blk_size * mmc->max_blk_count;
1292 
1293     dev_dbg(mmc_dev(host->mmc), "max_segs=%d\n", mmc->max_segs);
1294     dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size);
1295     dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size);
1296     dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size);
1297 
1298     platform_set_drvdata(pdev, host);
1299 
1300     ret = mmc_davinci_cpufreq_register(host);
1301     if (ret) {
1302         dev_err(&pdev->dev, "failed to register cpufreq\n");
1303         goto cpu_freq_fail;
1304     }
1305 
1306     ret = mmc_add_host(mmc);
1307     if (ret < 0)
1308         goto mmc_add_host_fail;
1309 
1310     ret = devm_request_irq(&pdev->dev, irq, mmc_davinci_irq, 0,
1311                    mmc_hostname(mmc), host);
1312     if (ret)
1313         goto request_irq_fail;
1314 
1315     if (host->sdio_irq >= 0) {
1316         ret = devm_request_irq(&pdev->dev, host->sdio_irq,
1317                        mmc_davinci_sdio_irq, 0,
1318                        mmc_hostname(mmc), host);
1319         if (!ret)
1320             mmc->caps |= MMC_CAP_SDIO_IRQ;
1321     }
1322 
1323     rename_region(mem, mmc_hostname(mmc));
1324 
1325     dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n",
1326         host->use_dma ? "DMA" : "PIO",
1327         (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
1328 
1329     return 0;
1330 
1331 request_irq_fail:
1332     mmc_remove_host(mmc);
1333 mmc_add_host_fail:
1334     mmc_davinci_cpufreq_deregister(host);
1335 cpu_freq_fail:
1336     davinci_release_dma_channels(host);
1337 parse_fail:
1338 dma_probe_defer:
1339     clk_disable_unprepare(host->clk);
1340 clk_prepare_enable_fail:
1341 clk_get_fail:
1342 ioremap_fail:
1343     mmc_free_host(mmc);
1344 
1345     return ret;
1346 }
1347 
1348 static int __exit davinci_mmcsd_remove(struct platform_device *pdev)
1349 {
1350     struct mmc_davinci_host *host = platform_get_drvdata(pdev);
1351 
1352     mmc_remove_host(host->mmc);
1353     mmc_davinci_cpufreq_deregister(host);
1354     davinci_release_dma_channels(host);
1355     clk_disable_unprepare(host->clk);
1356     mmc_free_host(host->mmc);
1357 
1358     return 0;
1359 }
1360 
1361 #ifdef CONFIG_PM
1362 static int davinci_mmcsd_suspend(struct device *dev)
1363 {
1364     struct mmc_davinci_host *host = dev_get_drvdata(dev);
1365 
1366     writel(0, host->base + DAVINCI_MMCIM);
1367     mmc_davinci_reset_ctrl(host, 1);
1368     clk_disable(host->clk);
1369 
1370     return 0;
1371 }
1372 
1373 static int davinci_mmcsd_resume(struct device *dev)
1374 {
1375     struct mmc_davinci_host *host = dev_get_drvdata(dev);
1376     int ret;
1377 
1378     ret = clk_enable(host->clk);
1379     if (ret)
1380         return ret;
1381 
1382     mmc_davinci_reset_ctrl(host, 0);
1383 
1384     return 0;
1385 }
1386 
1387 static const struct dev_pm_ops davinci_mmcsd_pm = {
1388     .suspend        = davinci_mmcsd_suspend,
1389     .resume         = davinci_mmcsd_resume,
1390 };
1391 
1392 #define davinci_mmcsd_pm_ops (&davinci_mmcsd_pm)
1393 #else
1394 #define davinci_mmcsd_pm_ops NULL
1395 #endif
1396 
1397 static struct platform_driver davinci_mmcsd_driver = {
1398     .driver     = {
1399         .name   = "davinci_mmc",
1400         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1401         .pm = davinci_mmcsd_pm_ops,
1402         .of_match_table = davinci_mmc_dt_ids,
1403     },
1404     .probe      = davinci_mmcsd_probe,
1405     .remove     = __exit_p(davinci_mmcsd_remove),
1406     .id_table   = davinci_mmc_devtype,
1407 };
1408 
1409 module_platform_driver(davinci_mmcsd_driver);
1410 
1411 MODULE_AUTHOR("Texas Instruments India");
1412 MODULE_LICENSE("GPL");
1413 MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller");
1414 MODULE_ALIAS("platform:davinci_mmc");
1415
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