mmc/host/cqhci.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
0003  */
0004 #ifndef LINUX_MMC_CQHCI_H
0005 #define LINUX_MMC_CQHCI_H
0006
0007 #include <linux/compiler.h>
0008 #include <linux/bitops.h>
0009 #include <linux/spinlock_types.h>
0010 #include <linux/types.h>
0011 #include <linux/completion.h>
0012 #include <linux/wait.h>
0013 #include <linux/irqreturn.h>
0014 #include <asm/io.h>
0015
0016 /* registers */
0017 /* version */
0018 #define CQHCI_VER           0x00
0019 #define CQHCI_VER_MAJOR(x)      (((x) & GENMASK(11, 8)) >> 8)
0020 #define CQHCI_VER_MINOR1(x)     (((x) & GENMASK(7, 4)) >> 4)
0021 #define CQHCI_VER_MINOR2(x)     ((x) & GENMASK(3, 0))
0022
0023 /* capabilities */
0024 #define CQHCI_CAP           0x04
0025 #define CQHCI_CAP_CS            0x10000000 /* Crypto Support */
0026
0027 /* configuration */
0028 #define CQHCI_CFG           0x08
0029 #define CQHCI_DCMD          0x00001000
0030 #define CQHCI_TASK_DESC_SZ      0x00000100
0031 #define CQHCI_CRYPTO_GENERAL_ENABLE 0x00000002
0032 #define CQHCI_ENABLE            0x00000001
0033
0034 /* control */
0035 #define CQHCI_CTL           0x0C
0036 #define CQHCI_CLEAR_ALL_TASKS       0x00000100
0037 #define CQHCI_HALT          0x00000001
0038
0039 /* interrupt status */
0040 #define CQHCI_IS            0x10
0041 #define CQHCI_IS_HAC            BIT(0)
0042 #define CQHCI_IS_TCC            BIT(1)
0043 #define CQHCI_IS_RED            BIT(2)
0044 #define CQHCI_IS_TCL            BIT(3)
0045 #define CQHCI_IS_GCE            BIT(4) /* General Crypto Error */
0046 #define CQHCI_IS_ICCE           BIT(5) /* Invalid Crypto Config Error */
0047
0048 #define CQHCI_IS_MASK (CQHCI_IS_TCC | CQHCI_IS_RED | \
0049                CQHCI_IS_GCE | CQHCI_IS_ICCE)
0050
0051 /* interrupt status enable */
0052 #define CQHCI_ISTE          0x14
0053
0054 /* interrupt signal enable */
0055 #define CQHCI_ISGE          0x18
0056
0057 /* interrupt coalescing */
0058 #define CQHCI_IC            0x1C
0059 #define CQHCI_IC_ENABLE         BIT(31)
0060 #define CQHCI_IC_RESET          BIT(16)
0061 #define CQHCI_IC_ICCTHWEN       BIT(15)
0062 #define CQHCI_IC_ICCTH(x)       (((x) & 0x1F) << 8)
0063 #define CQHCI_IC_ICTOVALWEN     BIT(7)
0064 #define CQHCI_IC_ICTOVAL(x)     ((x) & 0x7F)
0065
0066 /* task list base address */
0067 #define CQHCI_TDLBA         0x20
0068
0069 /* task list base address upper */
0070 #define CQHCI_TDLBAU            0x24
0071
0072 /* door-bell */
0073 #define CQHCI_TDBR          0x28
0074
0075 /* task completion notification */
0076 #define CQHCI_TCN           0x2C
0077
0078 /* device queue status */
0079 #define CQHCI_DQS           0x30
0080
0081 /* device pending tasks */
0082 #define CQHCI_DPT           0x34
0083
0084 /* task clear */
0085 #define CQHCI_TCLR          0x38
0086
0087 /* task descriptor processing error */
0088 #define CQHCI_TDPE          0x3c
0089
0090 /* send status config 1 */
0091 #define CQHCI_SSC1          0x40
0092 #define CQHCI_SSC1_CBC_MASK     GENMASK(19, 16)
0093
0094 /* send status config 2 */
0095 #define CQHCI_SSC2          0x44
0096
0097 /* response for dcmd */
0098 #define CQHCI_CRDCT         0x48
0099
0100 /* response mode error mask */
0101 #define CQHCI_RMEM          0x50
0102
0103 /* task error info */
0104 #define CQHCI_TERRI         0x54
0105
0106 #define CQHCI_TERRI_C_INDEX(x)      ((x) & GENMASK(5, 0))
0107 #define CQHCI_TERRI_C_TASK(x)       (((x) & GENMASK(12, 8)) >> 8)
0108 #define CQHCI_TERRI_C_VALID(x)      ((x) & BIT(15))
0109 #define CQHCI_TERRI_D_INDEX(x)      (((x) & GENMASK(21, 16)) >> 16)
0110 #define CQHCI_TERRI_D_TASK(x)       (((x) & GENMASK(28, 24)) >> 24)
0111 #define CQHCI_TERRI_D_VALID(x)      ((x) & BIT(31))
0112
0113 /* command response index */
0114 #define CQHCI_CRI           0x58
0115
0116 /* command response argument */
0117 #define CQHCI_CRA           0x5C
0118
0119 /* crypto capabilities */
0120 #define CQHCI_CCAP          0x100
0121 #define CQHCI_CRYPTOCAP         0x104
0122
0123 #define CQHCI_INT_ALL           0xF
0124 #define CQHCI_IC_DEFAULT_ICCTH      31
0125 #define CQHCI_IC_DEFAULT_ICTOVAL    1
0126
0127 /* attribute fields */
0128 #define CQHCI_VALID(x)          (((x) & 1) << 0)
0129 #define CQHCI_END(x)            (((x) & 1) << 1)
0130 #define CQHCI_INT(x)            (((x) & 1) << 2)
0131 #define CQHCI_ACT(x)            (((x) & 0x7) << 3)
0132
0133 /* data command task descriptor fields */
0134 #define CQHCI_FORCED_PROG(x)        (((x) & 1) << 6)
0135 #define CQHCI_CONTEXT(x)        (((x) & 0xF) << 7)
0136 #define CQHCI_DATA_TAG(x)       (((x) & 1) << 11)
0137 #define CQHCI_DATA_DIR(x)       (((x) & 1) << 12)
0138 #define CQHCI_PRIORITY(x)       (((x) & 1) << 13)
0139 #define CQHCI_QBAR(x)           (((x) & 1) << 14)
0140 #define CQHCI_REL_WRITE(x)      (((x) & 1) << 15)
0141 #define CQHCI_BLK_COUNT(x)      (((x) & 0xFFFF) << 16)
0142 #define CQHCI_BLK_ADDR(x)       (((x) & 0xFFFFFFFF) << 32)
0143
0144 /* direct command task descriptor fields */
0145 #define CQHCI_CMD_INDEX(x)      (((x) & 0x3F) << 16)
0146 #define CQHCI_CMD_TIMING(x)     (((x) & 1) << 22)
0147 #define CQHCI_RESP_TYPE(x)      (((x) & 0x3) << 23)
0148
0149 /* crypto task descriptor fields (for bits 64-127 of task descriptor) */
0150 #define CQHCI_CRYPTO_ENABLE_BIT     (1ULL << 47)
0151 #define CQHCI_CRYPTO_KEYSLOT(x)     ((u64)(x) << 32)
0152
0153 /* transfer descriptor fields */
0154 #define CQHCI_DAT_LENGTH(x)     (((x) & 0xFFFF) << 16)
0155 #define CQHCI_DAT_ADDR_LO(x)        (((x) & 0xFFFFFFFF) << 32)
0156 #define CQHCI_DAT_ADDR_HI(x)        (((x) & 0xFFFFFFFF) << 0)
0157
0158 /* CCAP - Crypto Capability 100h */
0159 union cqhci_crypto_capabilities {
0160     __le32 reg_val;
0161     struct {
0162         u8 num_crypto_cap;
0163         u8 config_count;
0164         u8 reserved;
0165         u8 config_array_ptr;
0166     };
0167 };
0168
0169 enum cqhci_crypto_key_size {
0170     CQHCI_CRYPTO_KEY_SIZE_INVALID   = 0,
0171     CQHCI_CRYPTO_KEY_SIZE_128   = 1,
0172     CQHCI_CRYPTO_KEY_SIZE_192   = 2,
0173     CQHCI_CRYPTO_KEY_SIZE_256   = 3,
0174     CQHCI_CRYPTO_KEY_SIZE_512   = 4,
0175 };
0176
0177 enum cqhci_crypto_alg {
0178     CQHCI_CRYPTO_ALG_AES_XTS        = 0,
0179     CQHCI_CRYPTO_ALG_BITLOCKER_AES_CBC  = 1,
0180     CQHCI_CRYPTO_ALG_AES_ECB        = 2,
0181     CQHCI_CRYPTO_ALG_ESSIV_AES_CBC      = 3,
0182 };
0183
0184 /* x-CRYPTOCAP - Crypto Capability X */
0185 union cqhci_crypto_cap_entry {
0186     __le32 reg_val;
0187     struct {
0188         u8 algorithm_id;
0189         u8 sdus_mask; /* Supported data unit size mask */
0190         u8 key_size;
0191         u8 reserved;
0192     };
0193 };
0194
0195 #define CQHCI_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
0196 #define CQHCI_CRYPTO_KEY_MAX_SIZE 64
0197 /* x-CRYPTOCFG - Crypto Configuration X */
0198 union cqhci_crypto_cfg_entry {
0199     __le32 reg_val[32];
0200     struct {
0201         u8 crypto_key[CQHCI_CRYPTO_KEY_MAX_SIZE];
0202         u8 data_unit_size;
0203         u8 crypto_cap_idx;
0204         u8 reserved_1;
0205         u8 config_enable;
0206         u8 reserved_multi_host;
0207         u8 reserved_2;
0208         u8 vsb[2];
0209         u8 reserved_3[56];
0210     };
0211 };
0212
0213 struct cqhci_host_ops;
0214 struct mmc_host;
0215 struct mmc_request;
0216 struct cqhci_slot;
0217
0218 struct cqhci_host {
0219     const struct cqhci_host_ops *ops;
0220     void __iomem *mmio;
0221     struct mmc_host *mmc;
0222
0223     spinlock_t lock;
0224
0225     /* relative card address of device */
0226     unsigned int rca;
0227
0228     /* 64 bit DMA */
0229     bool dma64;
0230     int num_slots;
0231     int qcnt;
0232
0233     u32 dcmd_slot;
0234     u32 caps;
0235 #define CQHCI_TASK_DESC_SZ_128      0x1
0236
0237     u32 quirks;
0238 #define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ  0x1
0239
0240     bool enabled;
0241     bool halted;
0242     bool init_done;
0243     bool activated;
0244     bool waiting_for_idle;
0245     bool recovery_halt;
0246
0247     size_t desc_size;
0248     size_t data_size;
0249
0250     u8 *desc_base;
0251
0252     /* total descriptor size */
0253     u8 slot_sz;
0254
0255     /* 64/128 bit depends on CQHCI_CFG */
0256     u8 task_desc_len;
0257
0258     /* 64 bit on 32-bit arch, 128 bit on 64-bit */
0259     u8 link_desc_len;
0260
0261     u8 *trans_desc_base;
0262     /* same length as transfer descriptor */
0263     u8 trans_desc_len;
0264
0265     dma_addr_t desc_dma_base;
0266     dma_addr_t trans_desc_dma_base;
0267
0268     struct completion halt_comp;
0269     wait_queue_head_t wait_queue;
0270     struct cqhci_slot *slot;
0271
0272 #ifdef CONFIG_MMC_CRYPTO
0273     union cqhci_crypto_capabilities crypto_capabilities;
0274     union cqhci_crypto_cap_entry *crypto_cap_array;
0275     u32 crypto_cfg_register;
0276 #endif
0277 };
0278
0279 struct cqhci_host_ops {
0280     void (*dumpregs)(struct mmc_host *mmc);
0281     void (*write_l)(struct cqhci_host *host, u32 val, int reg);
0282     u32 (*read_l)(struct cqhci_host *host, int reg);
0283     void (*enable)(struct mmc_host *mmc);
0284     void (*disable)(struct mmc_host *mmc, bool recovery);
0285     void (*update_dcmd_desc)(struct mmc_host *mmc, struct mmc_request *mrq,
0286                  u64 *data);
0287     void (*pre_enable)(struct mmc_host *mmc);
0288     void (*post_disable)(struct mmc_host *mmc);
0289 #ifdef CONFIG_MMC_CRYPTO
0290     int (*program_key)(struct cqhci_host *cq_host,
0291                const union cqhci_crypto_cfg_entry *cfg, int slot);
0292 #endif
0293 };
0294
0295 static inline void cqhci_writel(struct cqhci_host *host, u32 val, int reg)
0296 {
0297     if (unlikely(host->ops->write_l))
0298         host->ops->write_l(host, val, reg);
0299     else
0300         writel_relaxed(val, host->mmio + reg);
0301 }
0302
0303 static inline u32 cqhci_readl(struct cqhci_host *host, int reg)
0304 {
0305     if (unlikely(host->ops->read_l))
0306         return host->ops->read_l(host, reg);
0307     else
0308         return readl_relaxed(host->mmio + reg);
0309 }
0310
0311 struct platform_device;
0312
0313 irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
0314               int data_error);
0315 int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64);
0316 struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev);
0317 int cqhci_deactivate(struct mmc_host *mmc);
0318 static inline int cqhci_suspend(struct mmc_host *mmc)
0319 {
0320     return cqhci_deactivate(mmc);
0321 }
0322 int cqhci_resume(struct mmc_host *mmc);
0323
0324 #endif