mmc/host/cqhci-crypto.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * CQHCI crypto engine (inline encryption) support
0004  *
0005  * Copyright 2020 Google LLC
0006  */
0007
0008 #include <linux/blk-crypto.h>
0009 #include <linux/blk-crypto-profile.h>
0010 #include <linux/mmc/host.h>
0011
0012 #include "cqhci-crypto.h"
0013
0014 /* Map from blk-crypto modes to CQHCI crypto algorithm IDs and key sizes */
0015 static const struct cqhci_crypto_alg_entry {
0016     enum cqhci_crypto_alg alg;
0017     enum cqhci_crypto_key_size key_size;
0018 } cqhci_crypto_algs[BLK_ENCRYPTION_MODE_MAX] = {
0019     [BLK_ENCRYPTION_MODE_AES_256_XTS] = {
0020         .alg = CQHCI_CRYPTO_ALG_AES_XTS,
0021         .key_size = CQHCI_CRYPTO_KEY_SIZE_256,
0022     },
0023 };
0024
0025 static inline struct cqhci_host *
0026 cqhci_host_from_crypto_profile(struct blk_crypto_profile *profile)
0027 {
0028     struct mmc_host *mmc =
0029         container_of(profile, struct mmc_host, crypto_profile);
0030
0031     return mmc->cqe_private;
0032 }
0033
0034 static int cqhci_crypto_program_key(struct cqhci_host *cq_host,
0035                     const union cqhci_crypto_cfg_entry *cfg,
0036                     int slot)
0037 {
0038     u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg);
0039     int i;
0040
0041     if (cq_host->ops->program_key)
0042         return cq_host->ops->program_key(cq_host, cfg, slot);
0043
0044     /* Clear CFGE */
0045     cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0]));
0046
0047     /* Write the key */
0048     for (i = 0; i < 16; i++) {
0049         cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[i]),
0050                  slot_offset + i * sizeof(cfg->reg_val[0]));
0051     }
0052     /* Write dword 17 */
0053     cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[17]),
0054              slot_offset + 17 * sizeof(cfg->reg_val[0]));
0055     /* Write dword 16, which includes the new value of CFGE */
0056     cqhci_writel(cq_host, le32_to_cpu(cfg->reg_val[16]),
0057              slot_offset + 16 * sizeof(cfg->reg_val[0]));
0058     return 0;
0059 }
0060
0061 static int cqhci_crypto_keyslot_program(struct blk_crypto_profile *profile,
0062                     const struct blk_crypto_key *key,
0063                     unsigned int slot)
0064
0065 {
0066     struct cqhci_host *cq_host = cqhci_host_from_crypto_profile(profile);
0067     const union cqhci_crypto_cap_entry *ccap_array =
0068         cq_host->crypto_cap_array;
0069     const struct cqhci_crypto_alg_entry *alg =
0070             &cqhci_crypto_algs[key->crypto_cfg.crypto_mode];
0071     u8 data_unit_mask = key->crypto_cfg.data_unit_size / 512;
0072     int i;
0073     int cap_idx = -1;
0074     union cqhci_crypto_cfg_entry cfg = {};
0075     int err;
0076
0077     BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0);
0078     for (i = 0; i < cq_host->crypto_capabilities.num_crypto_cap; i++) {
0079         if (ccap_array[i].algorithm_id == alg->alg &&
0080             ccap_array[i].key_size == alg->key_size &&
0081             (ccap_array[i].sdus_mask & data_unit_mask)) {
0082             cap_idx = i;
0083             break;
0084         }
0085     }
0086     if (WARN_ON(cap_idx < 0))
0087         return -EOPNOTSUPP;
0088
0089     cfg.data_unit_size = data_unit_mask;
0090     cfg.crypto_cap_idx = cap_idx;
0091     cfg.config_enable = CQHCI_CRYPTO_CONFIGURATION_ENABLE;
0092
0093     if (ccap_array[cap_idx].algorithm_id == CQHCI_CRYPTO_ALG_AES_XTS) {
0094         /* In XTS mode, the blk_crypto_key's size is already doubled */
0095         memcpy(cfg.crypto_key, key->raw, key->size/2);
0096         memcpy(cfg.crypto_key + CQHCI_CRYPTO_KEY_MAX_SIZE/2,
0097                key->raw + key->size/2, key->size/2);
0098     } else {
0099         memcpy(cfg.crypto_key, key->raw, key->size);
0100     }
0101
0102     err = cqhci_crypto_program_key(cq_host, &cfg, slot);
0103
0104     memzero_explicit(&cfg, sizeof(cfg));
0105     return err;
0106 }
0107
0108 static int cqhci_crypto_clear_keyslot(struct cqhci_host *cq_host, int slot)
0109 {
0110     /*
0111      * Clear the crypto cfg on the device. Clearing CFGE
0112      * might not be sufficient, so just clear the entire cfg.
0113      */
0114     union cqhci_crypto_cfg_entry cfg = {};
0115
0116     return cqhci_crypto_program_key(cq_host, &cfg, slot);
0117 }
0118
0119 static int cqhci_crypto_keyslot_evict(struct blk_crypto_profile *profile,
0120                       const struct blk_crypto_key *key,
0121                       unsigned int slot)
0122 {
0123     struct cqhci_host *cq_host = cqhci_host_from_crypto_profile(profile);
0124
0125     return cqhci_crypto_clear_keyslot(cq_host, slot);
0126 }
0127
0128 /*
0129  * The keyslot management operations for CQHCI crypto.
0130  *
0131  * Note that the block layer ensures that these are never called while the host
0132  * controller is runtime-suspended.  However, the CQE won't necessarily be
0133  * "enabled" when these are called, i.e. CQHCI_ENABLE might not be set in the
0134  * CQHCI_CFG register.  But the hardware allows that.
0135  */
0136 static const struct blk_crypto_ll_ops cqhci_crypto_ops = {
0137     .keyslot_program    = cqhci_crypto_keyslot_program,
0138     .keyslot_evict      = cqhci_crypto_keyslot_evict,
0139 };
0140
0141 static enum blk_crypto_mode_num
0142 cqhci_find_blk_crypto_mode(union cqhci_crypto_cap_entry cap)
0143 {
0144     int i;
0145
0146     for (i = 0; i < ARRAY_SIZE(cqhci_crypto_algs); i++) {
0147         BUILD_BUG_ON(CQHCI_CRYPTO_KEY_SIZE_INVALID != 0);
0148         if (cqhci_crypto_algs[i].alg == cap.algorithm_id &&
0149             cqhci_crypto_algs[i].key_size == cap.key_size)
0150             return i;
0151     }
0152     return BLK_ENCRYPTION_MODE_INVALID;
0153 }
0154
0155 /**
0156  * cqhci_crypto_init - initialize CQHCI crypto support
0157  * @cq_host: a cqhci host
0158  *
0159  * If the driver previously set MMC_CAP2_CRYPTO and the CQE declares
0160  * CQHCI_CAP_CS, initialize the crypto support.  This involves reading the
0161  * crypto capability registers, initializing the blk_crypto_profile, clearing
0162  * all keyslots, and enabling 128-bit task descriptors.
0163  *
0164  * Return: 0 if crypto was initialized or isn't supported; whether
0165  *     MMC_CAP2_CRYPTO remains set indicates which one of those cases it is.
0166  *     Also can return a negative errno value on unexpected error.
0167  */
0168 int cqhci_crypto_init(struct cqhci_host *cq_host)
0169 {
0170     struct mmc_host *mmc = cq_host->mmc;
0171     struct device *dev = mmc_dev(mmc);
0172     struct blk_crypto_profile *profile = &mmc->crypto_profile;
0173     unsigned int num_keyslots;
0174     unsigned int cap_idx;
0175     enum blk_crypto_mode_num blk_mode_num;
0176     unsigned int slot;
0177     int err = 0;
0178
0179     if (!(mmc->caps2 & MMC_CAP2_CRYPTO) ||
0180         !(cqhci_readl(cq_host, CQHCI_CAP) & CQHCI_CAP_CS))
0181         goto out;
0182
0183     cq_host->crypto_capabilities.reg_val =
0184             cpu_to_le32(cqhci_readl(cq_host, CQHCI_CCAP));
0185
0186     cq_host->crypto_cfg_register =
0187         (u32)cq_host->crypto_capabilities.config_array_ptr * 0x100;
0188
0189     cq_host->crypto_cap_array =
0190         devm_kcalloc(dev, cq_host->crypto_capabilities.num_crypto_cap,
0191                  sizeof(cq_host->crypto_cap_array[0]), GFP_KERNEL);
0192     if (!cq_host->crypto_cap_array) {
0193         err = -ENOMEM;
0194         goto out;
0195     }
0196
0197     /*
0198      * CCAP.CFGC is off by one, so the actual number of crypto
0199      * configurations (a.k.a. keyslots) is CCAP.CFGC + 1.
0200      */
0201     num_keyslots = cq_host->crypto_capabilities.config_count + 1;
0202
0203     err = devm_blk_crypto_profile_init(dev, profile, num_keyslots);
0204     if (err)
0205         goto out;
0206
0207     profile->ll_ops = cqhci_crypto_ops;
0208     profile->dev = dev;
0209
0210     /* Unfortunately, CQHCI crypto only supports 32 DUN bits. */
0211     profile->max_dun_bytes_supported = 4;
0212
0213     /*
0214      * Cache all the crypto capabilities and advertise the supported crypto
0215      * modes and data unit sizes to the block layer.
0216      */
0217     for (cap_idx = 0; cap_idx < cq_host->crypto_capabilities.num_crypto_cap;
0218          cap_idx++) {
0219         cq_host->crypto_cap_array[cap_idx].reg_val =
0220             cpu_to_le32(cqhci_readl(cq_host,
0221                         CQHCI_CRYPTOCAP +
0222                         cap_idx * sizeof(__le32)));
0223         blk_mode_num = cqhci_find_blk_crypto_mode(
0224                     cq_host->crypto_cap_array[cap_idx]);
0225         if (blk_mode_num == BLK_ENCRYPTION_MODE_INVALID)
0226             continue;
0227         profile->modes_supported[blk_mode_num] |=
0228             cq_host->crypto_cap_array[cap_idx].sdus_mask * 512;
0229     }
0230
0231     /* Clear all the keyslots so that we start in a known state. */
0232     for (slot = 0; slot < num_keyslots; slot++)
0233         cqhci_crypto_clear_keyslot(cq_host, slot);
0234
0235     /* CQHCI crypto requires the use of 128-bit task descriptors. */
0236     cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
0237
0238     return 0;
0239
0240 out:
0241     mmc->caps2 &= ~MMC_CAP2_CRYPTO;
0242     return err;
0243 }