Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  cb710/mmc.c
0004  *
0005  *  Copyright by Michał Mirosław, 2008-2009
0006  */
0007 #include <linux/kernel.h>
0008 #include <linux/module.h>
0009 #include <linux/pci.h>
0010 #include <linux/delay.h>
0011 #include "cb710-mmc.h"
0012 
0013 #define CB710_MMC_REQ_TIMEOUT_MS    2000
0014 
0015 static const u8 cb710_clock_divider_log2[8] = {
0016 /*  1, 2, 4, 8, 16, 32, 128, 512 */
0017     0, 1, 2, 3,  4,  5,   7,   9
0018 };
0019 #define CB710_MAX_DIVIDER_IDX   \
0020     (ARRAY_SIZE(cb710_clock_divider_log2) - 1)
0021 
0022 static const u8 cb710_src_freq_mhz[16] = {
0023     33, 10, 20, 25, 30, 35, 40, 45,
0024     50, 55, 60, 65, 70, 75, 80, 85
0025 };
0026 
0027 static void cb710_mmc_select_clock_divider(struct mmc_host *mmc, int hz)
0028 {
0029     struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
0030     struct pci_dev *pdev = cb710_slot_to_chip(slot)->pdev;
0031     u32 src_freq_idx;
0032     u32 divider_idx;
0033     int src_hz;
0034 
0035     /* on CB710 in HP nx9500:
0036      *   src_freq_idx == 0
0037      *   indexes 1-7 work as written in the table
0038      *   indexes 0,8-15 give no clock output
0039      */
0040     pci_read_config_dword(pdev, 0x48, &src_freq_idx);
0041     src_freq_idx = (src_freq_idx >> 16) & 0xF;
0042     src_hz = cb710_src_freq_mhz[src_freq_idx] * 1000000;
0043 
0044     for (divider_idx = 0; divider_idx < CB710_MAX_DIVIDER_IDX; ++divider_idx) {
0045         if (hz >= src_hz >> cb710_clock_divider_log2[divider_idx])
0046             break;
0047     }
0048 
0049     if (src_freq_idx)
0050         divider_idx |= 0x8;
0051     else if (divider_idx == 0)
0052         divider_idx = 1;
0053 
0054     cb710_pci_update_config_reg(pdev, 0x40, ~0xF0000000, divider_idx << 28);
0055 
0056     dev_dbg(cb710_slot_dev(slot),
0057         "clock set to %d Hz, wanted %d Hz; src_freq_idx = %d, divider_idx = %d|%d\n",
0058         src_hz >> cb710_clock_divider_log2[divider_idx & 7],
0059         hz, src_freq_idx, divider_idx & 7, divider_idx & 8);
0060 }
0061 
0062 static void __cb710_mmc_enable_irq(struct cb710_slot *slot,
0063     unsigned short enable, unsigned short mask)
0064 {
0065     /* clear global IE
0066      * - it gets set later if any interrupt sources are enabled */
0067     mask |= CB710_MMC_IE_IRQ_ENABLE;
0068 
0069     /* look like interrupt is fired whenever
0070      * WORD[0x0C] & WORD[0x10] != 0;
0071      * -> bit 15 port 0x0C seems to be global interrupt enable
0072      */
0073 
0074     enable = (cb710_read_port_16(slot, CB710_MMC_IRQ_ENABLE_PORT)
0075         & ~mask) | enable;
0076 
0077     if (enable)
0078         enable |= CB710_MMC_IE_IRQ_ENABLE;
0079 
0080     cb710_write_port_16(slot, CB710_MMC_IRQ_ENABLE_PORT, enable);
0081 }
0082 
0083 static void cb710_mmc_enable_irq(struct cb710_slot *slot,
0084     unsigned short enable, unsigned short mask)
0085 {
0086     struct cb710_mmc_reader *reader = mmc_priv(cb710_slot_to_mmc(slot));
0087     unsigned long flags;
0088 
0089     spin_lock_irqsave(&reader->irq_lock, flags);
0090     /* this is the only thing irq_lock protects */
0091     __cb710_mmc_enable_irq(slot, enable, mask);
0092     spin_unlock_irqrestore(&reader->irq_lock, flags);
0093 }
0094 
0095 static void cb710_mmc_reset_events(struct cb710_slot *slot)
0096 {
0097     cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT, 0xFF);
0098     cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT, 0xFF);
0099     cb710_write_port_8(slot, CB710_MMC_STATUS2_PORT, 0xFF);
0100 }
0101 
0102 static void cb710_mmc_enable_4bit_data(struct cb710_slot *slot, int enable)
0103 {
0104     if (enable)
0105         cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT,
0106             CB710_MMC_C1_4BIT_DATA_BUS, 0);
0107     else
0108         cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT,
0109             0, CB710_MMC_C1_4BIT_DATA_BUS);
0110 }
0111 
0112 static int cb710_check_event(struct cb710_slot *slot, u8 what)
0113 {
0114     u16 status;
0115 
0116     status = cb710_read_port_16(slot, CB710_MMC_STATUS_PORT);
0117 
0118     if (status & CB710_MMC_S0_FIFO_UNDERFLOW) {
0119         /* it is just a guess, so log it */
0120         dev_dbg(cb710_slot_dev(slot),
0121             "CHECK : ignoring bit 6 in status %04X\n", status);
0122         cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT,
0123             CB710_MMC_S0_FIFO_UNDERFLOW);
0124         status &= ~CB710_MMC_S0_FIFO_UNDERFLOW;
0125     }
0126 
0127     if (status & CB710_MMC_STATUS_ERROR_EVENTS) {
0128         dev_dbg(cb710_slot_dev(slot),
0129             "CHECK : returning EIO on status %04X\n", status);
0130         cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT, status & 0xFF);
0131         cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT,
0132             CB710_MMC_S1_RESET);
0133         return -EIO;
0134     }
0135 
0136     /* 'what' is a bit in MMC_STATUS1 */
0137     if ((status >> 8) & what) {
0138         cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT, what);
0139         return 1;
0140     }
0141 
0142     return 0;
0143 }
0144 
0145 static int cb710_wait_for_event(struct cb710_slot *slot, u8 what)
0146 {
0147     int err = 0;
0148     unsigned limit = 2000000;   /* FIXME: real timeout */
0149 
0150 #ifdef CONFIG_CB710_DEBUG
0151     u32 e, x;
0152     e = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
0153 #endif
0154 
0155     while (!(err = cb710_check_event(slot, what))) {
0156         if (!--limit) {
0157             cb710_dump_regs(cb710_slot_to_chip(slot),
0158                 CB710_DUMP_REGS_MMC);
0159             err = -ETIMEDOUT;
0160             break;
0161         }
0162         udelay(1);
0163     }
0164 
0165 #ifdef CONFIG_CB710_DEBUG
0166     x = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
0167 
0168     limit = 2000000 - limit;
0169     if (limit > 100)
0170         dev_dbg(cb710_slot_dev(slot),
0171             "WAIT10: waited %d loops, what %d, entry val %08X, exit val %08X\n",
0172             limit, what, e, x);
0173 #endif
0174     return err < 0 ? err : 0;
0175 }
0176 
0177 
0178 static int cb710_wait_while_busy(struct cb710_slot *slot, uint8_t mask)
0179 {
0180     unsigned limit = 500000;    /* FIXME: real timeout */
0181     int err = 0;
0182 
0183 #ifdef CONFIG_CB710_DEBUG
0184     u32 e, x;
0185     e = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
0186 #endif
0187 
0188     while (cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT) & mask) {
0189         if (!--limit) {
0190             cb710_dump_regs(cb710_slot_to_chip(slot),
0191                 CB710_DUMP_REGS_MMC);
0192             err = -ETIMEDOUT;
0193             break;
0194         }
0195         udelay(1);
0196     }
0197 
0198 #ifdef CONFIG_CB710_DEBUG
0199     x = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
0200 
0201     limit = 500000 - limit;
0202     if (limit > 100)
0203         dev_dbg(cb710_slot_dev(slot),
0204             "WAIT12: waited %d loops, mask %02X, entry val %08X, exit val %08X\n",
0205             limit, mask, e, x);
0206 #endif
0207     return err;
0208 }
0209 
0210 static void cb710_mmc_set_transfer_size(struct cb710_slot *slot,
0211     size_t count, size_t blocksize)
0212 {
0213     cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
0214     cb710_write_port_32(slot, CB710_MMC_TRANSFER_SIZE_PORT,
0215         ((count - 1) << 16)|(blocksize - 1));
0216 
0217     dev_vdbg(cb710_slot_dev(slot), "set up for %zu block%s of %zu bytes\n",
0218         count, count == 1 ? "" : "s", blocksize);
0219 }
0220 
0221 static void cb710_mmc_fifo_hack(struct cb710_slot *slot)
0222 {
0223     /* without this, received data is prepended with 8-bytes of zeroes */
0224     u32 r1, r2;
0225     int ok = 0;
0226 
0227     r1 = cb710_read_port_32(slot, CB710_MMC_DATA_PORT);
0228     r2 = cb710_read_port_32(slot, CB710_MMC_DATA_PORT);
0229     if (cb710_read_port_8(slot, CB710_MMC_STATUS0_PORT)
0230         & CB710_MMC_S0_FIFO_UNDERFLOW) {
0231         cb710_write_port_8(slot, CB710_MMC_STATUS0_PORT,
0232             CB710_MMC_S0_FIFO_UNDERFLOW);
0233         ok = 1;
0234     }
0235 
0236     dev_dbg(cb710_slot_dev(slot),
0237         "FIFO-read-hack: expected STATUS0 bit was %s\n",
0238         ok ? "set." : "NOT SET!");
0239     dev_dbg(cb710_slot_dev(slot),
0240         "FIFO-read-hack: dwords ignored: %08X %08X - %s\n",
0241         r1, r2, (r1|r2) ? "BAD (NOT ZERO)!" : "ok");
0242 }
0243 
0244 static int cb710_mmc_receive_pio(struct cb710_slot *slot,
0245     struct sg_mapping_iter *miter, size_t dw_count)
0246 {
0247     if (!(cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT) & CB710_MMC_S2_FIFO_READY)) {
0248         int err = cb710_wait_for_event(slot,
0249             CB710_MMC_S1_PIO_TRANSFER_DONE);
0250         if (err)
0251             return err;
0252     }
0253 
0254     cb710_sg_dwiter_write_from_io(miter,
0255         slot->iobase + CB710_MMC_DATA_PORT, dw_count);
0256 
0257     return 0;
0258 }
0259 
0260 static bool cb710_is_transfer_size_supported(struct mmc_data *data)
0261 {
0262     return !(data->blksz & 15 && (data->blocks != 1 || data->blksz != 8));
0263 }
0264 
0265 static int cb710_mmc_receive(struct cb710_slot *slot, struct mmc_data *data)
0266 {
0267     struct sg_mapping_iter miter;
0268     size_t len, blocks = data->blocks;
0269     int err = 0;
0270 
0271     /* TODO: I don't know how/if the hardware handles non-16B-boundary blocks
0272      * except single 8B block */
0273     if (unlikely(data->blksz & 15 && (data->blocks != 1 || data->blksz != 8)))
0274         return -EINVAL;
0275 
0276     sg_miter_start(&miter, data->sg, data->sg_len, SG_MITER_TO_SG);
0277 
0278     cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT,
0279         15, CB710_MMC_C2_READ_PIO_SIZE_MASK);
0280 
0281     cb710_mmc_fifo_hack(slot);
0282 
0283     while (blocks-- > 0) {
0284         len = data->blksz;
0285 
0286         while (len >= 16) {
0287             err = cb710_mmc_receive_pio(slot, &miter, 4);
0288             if (err)
0289                 goto out;
0290             len -= 16;
0291         }
0292 
0293         if (!len)
0294             continue;
0295 
0296         cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT,
0297             len - 1, CB710_MMC_C2_READ_PIO_SIZE_MASK);
0298 
0299         len = (len >= 8) ? 4 : 2;
0300         err = cb710_mmc_receive_pio(slot, &miter, len);
0301         if (err)
0302             goto out;
0303     }
0304 out:
0305     sg_miter_stop(&miter);
0306     return err;
0307 }
0308 
0309 static int cb710_mmc_send(struct cb710_slot *slot, struct mmc_data *data)
0310 {
0311     struct sg_mapping_iter miter;
0312     size_t len, blocks = data->blocks;
0313     int err = 0;
0314 
0315     /* TODO: I don't know how/if the hardware handles multiple
0316      * non-16B-boundary blocks */
0317     if (unlikely(data->blocks > 1 && data->blksz & 15))
0318         return -EINVAL;
0319 
0320     sg_miter_start(&miter, data->sg, data->sg_len, SG_MITER_FROM_SG);
0321 
0322     cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT,
0323         0, CB710_MMC_C2_READ_PIO_SIZE_MASK);
0324 
0325     while (blocks-- > 0) {
0326         len = (data->blksz + 15) >> 4;
0327         do {
0328             if (!(cb710_read_port_8(slot, CB710_MMC_STATUS2_PORT)
0329                 & CB710_MMC_S2_FIFO_EMPTY)) {
0330                 err = cb710_wait_for_event(slot,
0331                     CB710_MMC_S1_PIO_TRANSFER_DONE);
0332                 if (err)
0333                     goto out;
0334             }
0335             cb710_sg_dwiter_read_to_io(&miter,
0336                 slot->iobase + CB710_MMC_DATA_PORT, 4);
0337         } while (--len);
0338     }
0339 out:
0340     sg_miter_stop(&miter);
0341     return err;
0342 }
0343 
0344 static u16 cb710_encode_cmd_flags(struct cb710_mmc_reader *reader,
0345     struct mmc_command *cmd)
0346 {
0347     unsigned int flags = cmd->flags;
0348     u16 cb_flags = 0;
0349 
0350     /* Windows driver returned 0 for commands for which no response
0351      * is expected. It happened that there were only two such commands
0352      * used: MMC_GO_IDLE_STATE and MMC_GO_INACTIVE_STATE so it might
0353      * as well be a bug in that driver.
0354      *
0355      * Original driver set bit 14 for MMC/SD application
0356      * commands. There's no difference 'on the wire' and
0357      * it apparently works without it anyway.
0358      */
0359 
0360     switch (flags & MMC_CMD_MASK) {
0361     case MMC_CMD_AC:    cb_flags = CB710_MMC_CMD_AC;    break;
0362     case MMC_CMD_ADTC:  cb_flags = CB710_MMC_CMD_ADTC;  break;
0363     case MMC_CMD_BC:    cb_flags = CB710_MMC_CMD_BC;    break;
0364     case MMC_CMD_BCR:   cb_flags = CB710_MMC_CMD_BCR;   break;
0365     }
0366 
0367     if (flags & MMC_RSP_BUSY)
0368         cb_flags |= CB710_MMC_RSP_BUSY;
0369 
0370     cb_flags |= cmd->opcode << CB710_MMC_CMD_CODE_SHIFT;
0371 
0372     if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
0373         cb_flags |= CB710_MMC_DATA_READ;
0374 
0375     if (flags & MMC_RSP_PRESENT) {
0376         /* Windows driver set 01 at bits 4,3 except for
0377          * MMC_SET_BLOCKLEN where it set 10. Maybe the
0378          * hardware can do something special about this
0379          * command? The original driver looks buggy/incomplete
0380          * anyway so we ignore this for now.
0381          *
0382          * I assume that 00 here means no response is expected.
0383          */
0384         cb_flags |= CB710_MMC_RSP_PRESENT;
0385 
0386         if (flags & MMC_RSP_136)
0387             cb_flags |= CB710_MMC_RSP_136;
0388         if (!(flags & MMC_RSP_CRC))
0389             cb_flags |= CB710_MMC_RSP_NO_CRC;
0390     }
0391 
0392     return cb_flags;
0393 }
0394 
0395 static void cb710_receive_response(struct cb710_slot *slot,
0396     struct mmc_command *cmd)
0397 {
0398     unsigned rsp_opcode, wanted_opcode;
0399 
0400     /* Looks like final byte with CRC is always stripped (same as SDHCI) */
0401     if (cmd->flags & MMC_RSP_136) {
0402         u32 resp[4];
0403 
0404         resp[0] = cb710_read_port_32(slot, CB710_MMC_RESPONSE3_PORT);
0405         resp[1] = cb710_read_port_32(slot, CB710_MMC_RESPONSE2_PORT);
0406         resp[2] = cb710_read_port_32(slot, CB710_MMC_RESPONSE1_PORT);
0407         resp[3] = cb710_read_port_32(slot, CB710_MMC_RESPONSE0_PORT);
0408         rsp_opcode = resp[0] >> 24;
0409 
0410         cmd->resp[0] = (resp[0] << 8)|(resp[1] >> 24);
0411         cmd->resp[1] = (resp[1] << 8)|(resp[2] >> 24);
0412         cmd->resp[2] = (resp[2] << 8)|(resp[3] >> 24);
0413         cmd->resp[3] = (resp[3] << 8);
0414     } else {
0415         rsp_opcode = cb710_read_port_32(slot, CB710_MMC_RESPONSE1_PORT) & 0x3F;
0416         cmd->resp[0] = cb710_read_port_32(slot, CB710_MMC_RESPONSE0_PORT);
0417     }
0418 
0419     wanted_opcode = (cmd->flags & MMC_RSP_OPCODE) ? cmd->opcode : 0x3F;
0420     if (rsp_opcode != wanted_opcode)
0421         cmd->error = -EILSEQ;
0422 }
0423 
0424 static int cb710_mmc_transfer_data(struct cb710_slot *slot,
0425     struct mmc_data *data)
0426 {
0427     int error, to;
0428 
0429     if (data->flags & MMC_DATA_READ)
0430         error = cb710_mmc_receive(slot, data);
0431     else
0432         error = cb710_mmc_send(slot, data);
0433 
0434     to = cb710_wait_for_event(slot, CB710_MMC_S1_DATA_TRANSFER_DONE);
0435     if (!error)
0436         error = to;
0437 
0438     if (!error)
0439         data->bytes_xfered = data->blksz * data->blocks;
0440     return error;
0441 }
0442 
0443 static int cb710_mmc_command(struct mmc_host *mmc, struct mmc_command *cmd)
0444 {
0445     struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
0446     struct cb710_mmc_reader *reader = mmc_priv(mmc);
0447     struct mmc_data *data = cmd->data;
0448 
0449     u16 cb_cmd = cb710_encode_cmd_flags(reader, cmd);
0450     dev_dbg(cb710_slot_dev(slot), "cmd request: 0x%04X\n", cb_cmd);
0451 
0452     if (data) {
0453         if (!cb710_is_transfer_size_supported(data)) {
0454             data->error = -EINVAL;
0455             return -1;
0456         }
0457         cb710_mmc_set_transfer_size(slot, data->blocks, data->blksz);
0458     }
0459 
0460     cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20|CB710_MMC_S2_BUSY_10);
0461     cb710_write_port_16(slot, CB710_MMC_CMD_TYPE_PORT, cb_cmd);
0462     cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
0463     cb710_write_port_32(slot, CB710_MMC_CMD_PARAM_PORT, cmd->arg);
0464     cb710_mmc_reset_events(slot);
0465     cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
0466     cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x01, 0);
0467 
0468     cmd->error = cb710_wait_for_event(slot, CB710_MMC_S1_COMMAND_SENT);
0469     if (cmd->error)
0470         return -1;
0471 
0472     if (cmd->flags & MMC_RSP_PRESENT) {
0473         cb710_receive_response(slot, cmd);
0474         if (cmd->error)
0475             return -1;
0476     }
0477 
0478     if (data)
0479         data->error = cb710_mmc_transfer_data(slot, data);
0480     return 0;
0481 }
0482 
0483 static void cb710_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
0484 {
0485     struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
0486     struct cb710_mmc_reader *reader = mmc_priv(mmc);
0487 
0488     WARN_ON(reader->mrq != NULL);
0489 
0490     reader->mrq = mrq;
0491     cb710_mmc_enable_irq(slot, CB710_MMC_IE_TEST_MASK, 0);
0492 
0493     if (!cb710_mmc_command(mmc, mrq->cmd) && mrq->stop)
0494         cb710_mmc_command(mmc, mrq->stop);
0495 
0496     tasklet_schedule(&reader->finish_req_tasklet);
0497 }
0498 
0499 static int cb710_mmc_powerup(struct cb710_slot *slot)
0500 {
0501 #ifdef CONFIG_CB710_DEBUG
0502     struct cb710_chip *chip = cb710_slot_to_chip(slot);
0503 #endif
0504     int err;
0505 
0506     /* a lot of magic for now */
0507     dev_dbg(cb710_slot_dev(slot), "bus powerup\n");
0508     cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
0509     err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
0510     if (unlikely(err))
0511         return err;
0512     cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x80, 0);
0513     cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0x80, 0);
0514     cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
0515     mdelay(1);
0516     dev_dbg(cb710_slot_dev(slot), "after delay 1\n");
0517     cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
0518     err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
0519     if (unlikely(err))
0520         return err;
0521     cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x09, 0);
0522     cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
0523     mdelay(1);
0524     dev_dbg(cb710_slot_dev(slot), "after delay 2\n");
0525     cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
0526     err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
0527     if (unlikely(err))
0528         return err;
0529     cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0, 0x08);
0530     cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
0531     mdelay(2);
0532     dev_dbg(cb710_slot_dev(slot), "after delay 3\n");
0533     cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
0534     cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x06, 0);
0535     cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0x70, 0);
0536     cb710_modify_port_8(slot, CB710_MMC_CONFIG2_PORT, 0x80, 0);
0537     cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0x03, 0);
0538     cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
0539     err = cb710_wait_while_busy(slot, CB710_MMC_S2_BUSY_20);
0540     if (unlikely(err))
0541         return err;
0542     /* This port behaves weird: quick byte reads of 0x08,0x09 return
0543      * 0xFF,0x00 after writing 0xFFFF to 0x08; it works correctly when
0544      * read/written from userspace...  What am I missing here?
0545      * (it doesn't depend on write-to-read delay) */
0546     cb710_write_port_16(slot, CB710_MMC_CONFIGB_PORT, 0xFFFF);
0547     cb710_modify_port_8(slot, CB710_MMC_CONFIG0_PORT, 0x06, 0);
0548     cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
0549     dev_dbg(cb710_slot_dev(slot), "bus powerup finished\n");
0550 
0551     return cb710_check_event(slot, 0);
0552 }
0553 
0554 static void cb710_mmc_powerdown(struct cb710_slot *slot)
0555 {
0556     cb710_modify_port_8(slot, CB710_MMC_CONFIG1_PORT, 0, 0x81);
0557     cb710_modify_port_8(slot, CB710_MMC_CONFIG3_PORT, 0, 0x80);
0558 }
0559 
0560 static void cb710_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
0561 {
0562     struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
0563     struct cb710_mmc_reader *reader = mmc_priv(mmc);
0564     int err;
0565 
0566     cb710_mmc_select_clock_divider(mmc, ios->clock);
0567 
0568     if (ios->power_mode != reader->last_power_mode) {
0569         switch (ios->power_mode) {
0570         case MMC_POWER_ON:
0571             err = cb710_mmc_powerup(slot);
0572             if (err) {
0573                 dev_warn(cb710_slot_dev(slot),
0574                     "powerup failed (%d)- retrying\n", err);
0575                 cb710_mmc_powerdown(slot);
0576                 udelay(1);
0577                 err = cb710_mmc_powerup(slot);
0578                 if (err)
0579                     dev_warn(cb710_slot_dev(slot),
0580                         "powerup retry failed (%d) - expect errors\n",
0581                     err);
0582             }
0583             reader->last_power_mode = MMC_POWER_ON;
0584             break;
0585         case MMC_POWER_OFF:
0586             cb710_mmc_powerdown(slot);
0587             reader->last_power_mode = MMC_POWER_OFF;
0588             break;
0589         case MMC_POWER_UP:
0590         default:
0591             /* ignore */
0592             break;
0593         }
0594     }
0595 
0596     cb710_mmc_enable_4bit_data(slot, ios->bus_width != MMC_BUS_WIDTH_1);
0597 
0598     cb710_mmc_enable_irq(slot, CB710_MMC_IE_TEST_MASK, 0);
0599 }
0600 
0601 static int cb710_mmc_get_ro(struct mmc_host *mmc)
0602 {
0603     struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
0604 
0605     return cb710_read_port_8(slot, CB710_MMC_STATUS3_PORT)
0606         & CB710_MMC_S3_WRITE_PROTECTED;
0607 }
0608 
0609 static int cb710_mmc_get_cd(struct mmc_host *mmc)
0610 {
0611     struct cb710_slot *slot = cb710_mmc_to_slot(mmc);
0612 
0613     return cb710_read_port_8(slot, CB710_MMC_STATUS3_PORT)
0614         & CB710_MMC_S3_CARD_DETECTED;
0615 }
0616 
0617 static int cb710_mmc_irq_handler(struct cb710_slot *slot)
0618 {
0619     struct mmc_host *mmc = cb710_slot_to_mmc(slot);
0620     struct cb710_mmc_reader *reader = mmc_priv(mmc);
0621     u32 status, config1, config2, irqen;
0622 
0623     status = cb710_read_port_32(slot, CB710_MMC_STATUS_PORT);
0624     irqen = cb710_read_port_32(slot, CB710_MMC_IRQ_ENABLE_PORT);
0625     config2 = cb710_read_port_32(slot, CB710_MMC_CONFIGB_PORT);
0626     config1 = cb710_read_port_32(slot, CB710_MMC_CONFIG_PORT);
0627 
0628     dev_dbg(cb710_slot_dev(slot), "interrupt; status: %08X, "
0629         "ie: %08X, c2: %08X, c1: %08X\n",
0630         status, irqen, config2, config1);
0631 
0632     if (status & (CB710_MMC_S1_CARD_CHANGED << 8)) {
0633         /* ack the event */
0634         cb710_write_port_8(slot, CB710_MMC_STATUS1_PORT,
0635             CB710_MMC_S1_CARD_CHANGED);
0636         if ((irqen & CB710_MMC_IE_CISTATUS_MASK)
0637             == CB710_MMC_IE_CISTATUS_MASK)
0638             mmc_detect_change(mmc, HZ/5);
0639     } else {
0640         dev_dbg(cb710_slot_dev(slot), "unknown interrupt (test)\n");
0641         spin_lock(&reader->irq_lock);
0642         __cb710_mmc_enable_irq(slot, 0, CB710_MMC_IE_TEST_MASK);
0643         spin_unlock(&reader->irq_lock);
0644     }
0645 
0646     return 1;
0647 }
0648 
0649 static void cb710_mmc_finish_request_tasklet(struct tasklet_struct *t)
0650 {
0651     struct cb710_mmc_reader *reader = from_tasklet(reader, t,
0652                                finish_req_tasklet);
0653     struct mmc_request *mrq = reader->mrq;
0654 
0655     reader->mrq = NULL;
0656     mmc_request_done(mmc_from_priv(reader), mrq);
0657 }
0658 
0659 static const struct mmc_host_ops cb710_mmc_host = {
0660     .request = cb710_mmc_request,
0661     .set_ios = cb710_mmc_set_ios,
0662     .get_ro = cb710_mmc_get_ro,
0663     .get_cd = cb710_mmc_get_cd,
0664 };
0665 
0666 #ifdef CONFIG_PM
0667 
0668 static int cb710_mmc_suspend(struct platform_device *pdev, pm_message_t state)
0669 {
0670     struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
0671 
0672     cb710_mmc_enable_irq(slot, 0, ~0);
0673     return 0;
0674 }
0675 
0676 static int cb710_mmc_resume(struct platform_device *pdev)
0677 {
0678     struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
0679 
0680     cb710_mmc_enable_irq(slot, 0, ~0);
0681     return 0;
0682 }
0683 
0684 #endif /* CONFIG_PM */
0685 
0686 static int cb710_mmc_init(struct platform_device *pdev)
0687 {
0688     struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
0689     struct cb710_chip *chip = cb710_slot_to_chip(slot);
0690     struct mmc_host *mmc;
0691     struct cb710_mmc_reader *reader;
0692     int err;
0693     u32 val;
0694 
0695     mmc = mmc_alloc_host(sizeof(*reader), cb710_slot_dev(slot));
0696     if (!mmc)
0697         return -ENOMEM;
0698 
0699     platform_set_drvdata(pdev, mmc);
0700 
0701     /* harmless (maybe) magic */
0702     pci_read_config_dword(chip->pdev, 0x48, &val);
0703     val = cb710_src_freq_mhz[(val >> 16) & 0xF];
0704     dev_dbg(cb710_slot_dev(slot), "source frequency: %dMHz\n", val);
0705     val *= 1000000;
0706 
0707     mmc->ops = &cb710_mmc_host;
0708     mmc->f_max = val;
0709     mmc->f_min = val >> cb710_clock_divider_log2[CB710_MAX_DIVIDER_IDX];
0710     mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
0711     mmc->caps = MMC_CAP_4_BIT_DATA;
0712     /*
0713      * In cb710_wait_for_event() we use a fixed timeout of ~2s, hence let's
0714      * inform the core about it. A future improvement should instead make
0715      * use of the cmd->busy_timeout.
0716      */
0717     mmc->max_busy_timeout = CB710_MMC_REQ_TIMEOUT_MS;
0718 
0719     reader = mmc_priv(mmc);
0720 
0721     tasklet_setup(&reader->finish_req_tasklet,
0722               cb710_mmc_finish_request_tasklet);
0723     spin_lock_init(&reader->irq_lock);
0724     cb710_dump_regs(chip, CB710_DUMP_REGS_MMC);
0725 
0726     cb710_mmc_enable_irq(slot, 0, ~0);
0727     cb710_set_irq_handler(slot, cb710_mmc_irq_handler);
0728 
0729     err = mmc_add_host(mmc);
0730     if (unlikely(err))
0731         goto err_free_mmc;
0732 
0733     dev_dbg(cb710_slot_dev(slot), "mmc_hostname is %s\n",
0734         mmc_hostname(mmc));
0735 
0736     cb710_mmc_enable_irq(slot, CB710_MMC_IE_CARD_INSERTION_STATUS, 0);
0737 
0738     return 0;
0739 
0740 err_free_mmc:
0741     dev_dbg(cb710_slot_dev(slot), "mmc_add_host() failed: %d\n", err);
0742 
0743     cb710_set_irq_handler(slot, NULL);
0744     mmc_free_host(mmc);
0745     return err;
0746 }
0747 
0748 static int cb710_mmc_exit(struct platform_device *pdev)
0749 {
0750     struct cb710_slot *slot = cb710_pdev_to_slot(pdev);
0751     struct mmc_host *mmc = cb710_slot_to_mmc(slot);
0752     struct cb710_mmc_reader *reader = mmc_priv(mmc);
0753 
0754     cb710_mmc_enable_irq(slot, 0, CB710_MMC_IE_CARD_INSERTION_STATUS);
0755 
0756     mmc_remove_host(mmc);
0757 
0758     /* IRQs should be disabled now, but let's stay on the safe side */
0759     cb710_mmc_enable_irq(slot, 0, ~0);
0760     cb710_set_irq_handler(slot, NULL);
0761 
0762     /* clear config ports - just in case */
0763     cb710_write_port_32(slot, CB710_MMC_CONFIG_PORT, 0);
0764     cb710_write_port_16(slot, CB710_MMC_CONFIGB_PORT, 0);
0765 
0766     tasklet_kill(&reader->finish_req_tasklet);
0767 
0768     mmc_free_host(mmc);
0769     return 0;
0770 }
0771 
0772 static struct platform_driver cb710_mmc_driver = {
0773     .driver.name = "cb710-mmc",
0774     .probe = cb710_mmc_init,
0775     .remove = cb710_mmc_exit,
0776 #ifdef CONFIG_PM
0777     .suspend = cb710_mmc_suspend,
0778     .resume = cb710_mmc_resume,
0779 #endif
0780 };
0781 
0782 module_platform_driver(cb710_mmc_driver);
0783 
0784 MODULE_AUTHOR("Michał Mirosław <mirq-linux@rere.qmqm.pl>");
0785 MODULE_DESCRIPTION("ENE CB710 memory card reader driver - MMC/SD part");
0786 MODULE_LICENSE("GPL");
0787 MODULE_ALIAS("platform:cb710-mmc");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!