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0001 /*
0002  * Driver for MMC and SSD cards for Cavium OCTEON and ThunderX SOCs.
0003  *
0004  * This file is subject to the terms and conditions of the GNU General Public
0005  * License.  See the file "COPYING" in the main directory of this archive
0006  * for more details.
0007  *
0008  * Copyright (C) 2012-2017 Cavium Inc.
0009  */
0010 
0011 #ifndef _CAVIUM_MMC_H_
0012 #define _CAVIUM_MMC_H_
0013 
0014 #include <linux/bitops.h>
0015 #include <linux/clk.h>
0016 #include <linux/gpio/consumer.h>
0017 #include <linux/io.h>
0018 #include <linux/mmc/host.h>
0019 #include <linux/of.h>
0020 #include <linux/scatterlist.h>
0021 #include <linux/semaphore.h>
0022 
0023 #define CAVIUM_MAX_MMC      4
0024 
0025 /* DMA register addresses */
0026 #define MIO_EMM_DMA_FIFO_CFG(x) (0x00 + x->reg_off_dma)
0027 #define MIO_EMM_DMA_FIFO_ADR(x) (0x10 + x->reg_off_dma)
0028 #define MIO_EMM_DMA_FIFO_CMD(x) (0x18 + x->reg_off_dma)
0029 #define MIO_EMM_DMA_CFG(x)  (0x20 + x->reg_off_dma)
0030 #define MIO_EMM_DMA_ADR(x)  (0x28 + x->reg_off_dma)
0031 #define MIO_EMM_DMA_INT(x)  (0x30 + x->reg_off_dma)
0032 #define MIO_EMM_DMA_INT_W1S(x)  (0x38 + x->reg_off_dma)
0033 #define MIO_EMM_DMA_INT_ENA_W1S(x) (0x40 + x->reg_off_dma)
0034 #define MIO_EMM_DMA_INT_ENA_W1C(x) (0x48 + x->reg_off_dma)
0035 
0036 /* register addresses */
0037 #define MIO_EMM_CFG(x)      (0x00 + x->reg_off)
0038 #define MIO_EMM_SWITCH(x)   (0x48 + x->reg_off)
0039 #define MIO_EMM_DMA(x)      (0x50 + x->reg_off)
0040 #define MIO_EMM_CMD(x)      (0x58 + x->reg_off)
0041 #define MIO_EMM_RSP_STS(x)  (0x60 + x->reg_off)
0042 #define MIO_EMM_RSP_LO(x)   (0x68 + x->reg_off)
0043 #define MIO_EMM_RSP_HI(x)   (0x70 + x->reg_off)
0044 #define MIO_EMM_INT(x)      (0x78 + x->reg_off)
0045 #define MIO_EMM_INT_EN(x)   (0x80 + x->reg_off)
0046 #define MIO_EMM_WDOG(x)     (0x88 + x->reg_off)
0047 #define MIO_EMM_SAMPLE(x)   (0x90 + x->reg_off)
0048 #define MIO_EMM_STS_MASK(x) (0x98 + x->reg_off)
0049 #define MIO_EMM_RCA(x)      (0xa0 + x->reg_off)
0050 #define MIO_EMM_INT_EN_SET(x)   (0xb0 + x->reg_off)
0051 #define MIO_EMM_INT_EN_CLR(x)   (0xb8 + x->reg_off)
0052 #define MIO_EMM_BUF_IDX(x)  (0xe0 + x->reg_off)
0053 #define MIO_EMM_BUF_DAT(x)  (0xe8 + x->reg_off)
0054 
0055 struct cvm_mmc_host {
0056     struct device *dev;
0057     void __iomem *base;
0058     void __iomem *dma_base;
0059     int reg_off;
0060     int reg_off_dma;
0061     u64 emm_cfg;
0062     u64 n_minus_one;    /* OCTEON II workaround location */
0063     int last_slot;
0064     struct clk *clk;
0065     int sys_freq;
0066 
0067     struct mmc_request *current_req;
0068     struct sg_mapping_iter smi;
0069     bool dma_active;
0070     bool use_sg;
0071 
0072     bool has_ciu3;
0073     bool big_dma_addr;
0074     bool need_irq_handler_lock;
0075     spinlock_t irq_handler_lock;
0076     struct semaphore mmc_serializer;
0077 
0078     struct gpio_desc *global_pwr_gpiod;
0079     atomic_t shared_power_users;
0080 
0081     struct cvm_mmc_slot *slot[CAVIUM_MAX_MMC];
0082     struct platform_device *slot_pdev[CAVIUM_MAX_MMC];
0083 
0084     void (*set_shared_power)(struct cvm_mmc_host *, int);
0085     void (*acquire_bus)(struct cvm_mmc_host *);
0086     void (*release_bus)(struct cvm_mmc_host *);
0087     void (*int_enable)(struct cvm_mmc_host *, u64);
0088     /* required on some MIPS models */
0089     void (*dmar_fixup)(struct cvm_mmc_host *, struct mmc_command *,
0090                struct mmc_data *, u64);
0091     void (*dmar_fixup_done)(struct cvm_mmc_host *);
0092 };
0093 
0094 struct cvm_mmc_slot {
0095     struct mmc_host *mmc;       /* slot-level mmc_core object */
0096     struct cvm_mmc_host *host;  /* common hw for all slots */
0097 
0098     u64 clock;
0099 
0100     u64 cached_switch;
0101     u64 cached_rca;
0102 
0103     unsigned int cmd_cnt;       /* sample delay */
0104     unsigned int dat_cnt;       /* sample delay */
0105 
0106     int bus_id;
0107 };
0108 
0109 struct cvm_mmc_cr_type {
0110     u8 ctype;
0111     u8 rtype;
0112 };
0113 
0114 struct cvm_mmc_cr_mods {
0115     u8 ctype_xor;
0116     u8 rtype_xor;
0117 };
0118 
0119 /* Bitfield definitions */
0120 #define MIO_EMM_DMA_FIFO_CFG_CLR    BIT_ULL(16)
0121 #define MIO_EMM_DMA_FIFO_CFG_INT_LVL    GENMASK_ULL(12, 8)
0122 #define MIO_EMM_DMA_FIFO_CFG_COUNT  GENMASK_ULL(4, 0)
0123 
0124 #define MIO_EMM_DMA_FIFO_CMD_RW     BIT_ULL(62)
0125 #define MIO_EMM_DMA_FIFO_CMD_INTDIS BIT_ULL(60)
0126 #define MIO_EMM_DMA_FIFO_CMD_SWAP32 BIT_ULL(59)
0127 #define MIO_EMM_DMA_FIFO_CMD_SWAP16 BIT_ULL(58)
0128 #define MIO_EMM_DMA_FIFO_CMD_SWAP8  BIT_ULL(57)
0129 #define MIO_EMM_DMA_FIFO_CMD_ENDIAN BIT_ULL(56)
0130 #define MIO_EMM_DMA_FIFO_CMD_SIZE   GENMASK_ULL(55, 36)
0131 
0132 #define MIO_EMM_CMD_SKIP_BUSY       BIT_ULL(62)
0133 #define MIO_EMM_CMD_BUS_ID      GENMASK_ULL(61, 60)
0134 #define MIO_EMM_CMD_VAL         BIT_ULL(59)
0135 #define MIO_EMM_CMD_DBUF        BIT_ULL(55)
0136 #define MIO_EMM_CMD_OFFSET      GENMASK_ULL(54, 49)
0137 #define MIO_EMM_CMD_CTYPE_XOR       GENMASK_ULL(42, 41)
0138 #define MIO_EMM_CMD_RTYPE_XOR       GENMASK_ULL(40, 38)
0139 #define MIO_EMM_CMD_IDX         GENMASK_ULL(37, 32)
0140 #define MIO_EMM_CMD_ARG         GENMASK_ULL(31, 0)
0141 
0142 #define MIO_EMM_DMA_SKIP_BUSY       BIT_ULL(62)
0143 #define MIO_EMM_DMA_BUS_ID      GENMASK_ULL(61, 60)
0144 #define MIO_EMM_DMA_VAL         BIT_ULL(59)
0145 #define MIO_EMM_DMA_SECTOR      BIT_ULL(58)
0146 #define MIO_EMM_DMA_DAT_NULL        BIT_ULL(57)
0147 #define MIO_EMM_DMA_THRES       GENMASK_ULL(56, 51)
0148 #define MIO_EMM_DMA_REL_WR      BIT_ULL(50)
0149 #define MIO_EMM_DMA_RW          BIT_ULL(49)
0150 #define MIO_EMM_DMA_MULTI       BIT_ULL(48)
0151 #define MIO_EMM_DMA_BLOCK_CNT       GENMASK_ULL(47, 32)
0152 #define MIO_EMM_DMA_CARD_ADDR       GENMASK_ULL(31, 0)
0153 
0154 #define MIO_EMM_DMA_CFG_EN      BIT_ULL(63)
0155 #define MIO_EMM_DMA_CFG_RW      BIT_ULL(62)
0156 #define MIO_EMM_DMA_CFG_CLR     BIT_ULL(61)
0157 #define MIO_EMM_DMA_CFG_SWAP32      BIT_ULL(59)
0158 #define MIO_EMM_DMA_CFG_SWAP16      BIT_ULL(58)
0159 #define MIO_EMM_DMA_CFG_SWAP8       BIT_ULL(57)
0160 #define MIO_EMM_DMA_CFG_ENDIAN      BIT_ULL(56)
0161 #define MIO_EMM_DMA_CFG_SIZE        GENMASK_ULL(55, 36)
0162 #define MIO_EMM_DMA_CFG_ADR     GENMASK_ULL(35, 0)
0163 
0164 #define MIO_EMM_INT_SWITCH_ERR      BIT_ULL(6)
0165 #define MIO_EMM_INT_SWITCH_DONE     BIT_ULL(5)
0166 #define MIO_EMM_INT_DMA_ERR     BIT_ULL(4)
0167 #define MIO_EMM_INT_CMD_ERR     BIT_ULL(3)
0168 #define MIO_EMM_INT_DMA_DONE        BIT_ULL(2)
0169 #define MIO_EMM_INT_CMD_DONE        BIT_ULL(1)
0170 #define MIO_EMM_INT_BUF_DONE        BIT_ULL(0)
0171 
0172 #define MIO_EMM_RSP_STS_BUS_ID      GENMASK_ULL(61, 60)
0173 #define MIO_EMM_RSP_STS_CMD_VAL     BIT_ULL(59)
0174 #define MIO_EMM_RSP_STS_SWITCH_VAL  BIT_ULL(58)
0175 #define MIO_EMM_RSP_STS_DMA_VAL     BIT_ULL(57)
0176 #define MIO_EMM_RSP_STS_DMA_PEND    BIT_ULL(56)
0177 #define MIO_EMM_RSP_STS_DBUF_ERR    BIT_ULL(28)
0178 #define MIO_EMM_RSP_STS_DBUF        BIT_ULL(23)
0179 #define MIO_EMM_RSP_STS_BLK_TIMEOUT BIT_ULL(22)
0180 #define MIO_EMM_RSP_STS_BLK_CRC_ERR BIT_ULL(21)
0181 #define MIO_EMM_RSP_STS_RSP_BUSYBIT BIT_ULL(20)
0182 #define MIO_EMM_RSP_STS_STP_TIMEOUT BIT_ULL(19)
0183 #define MIO_EMM_RSP_STS_STP_CRC_ERR BIT_ULL(18)
0184 #define MIO_EMM_RSP_STS_STP_BAD_STS BIT_ULL(17)
0185 #define MIO_EMM_RSP_STS_STP_VAL     BIT_ULL(16)
0186 #define MIO_EMM_RSP_STS_RSP_TIMEOUT BIT_ULL(15)
0187 #define MIO_EMM_RSP_STS_RSP_CRC_ERR BIT_ULL(14)
0188 #define MIO_EMM_RSP_STS_RSP_BAD_STS BIT_ULL(13)
0189 #define MIO_EMM_RSP_STS_RSP_VAL     BIT_ULL(12)
0190 #define MIO_EMM_RSP_STS_RSP_TYPE    GENMASK_ULL(11, 9)
0191 #define MIO_EMM_RSP_STS_CMD_TYPE    GENMASK_ULL(8, 7)
0192 #define MIO_EMM_RSP_STS_CMD_IDX     GENMASK_ULL(6, 1)
0193 #define MIO_EMM_RSP_STS_CMD_DONE    BIT_ULL(0)
0194 
0195 #define MIO_EMM_SAMPLE_CMD_CNT      GENMASK_ULL(25, 16)
0196 #define MIO_EMM_SAMPLE_DAT_CNT      GENMASK_ULL(9, 0)
0197 
0198 #define MIO_EMM_SWITCH_BUS_ID       GENMASK_ULL(61, 60)
0199 #define MIO_EMM_SWITCH_EXE      BIT_ULL(59)
0200 #define MIO_EMM_SWITCH_ERR0     BIT_ULL(58)
0201 #define MIO_EMM_SWITCH_ERR1     BIT_ULL(57)
0202 #define MIO_EMM_SWITCH_ERR2     BIT_ULL(56)
0203 #define MIO_EMM_SWITCH_HS_TIMING    BIT_ULL(48)
0204 #define MIO_EMM_SWITCH_BUS_WIDTH    GENMASK_ULL(42, 40)
0205 #define MIO_EMM_SWITCH_POWER_CLASS  GENMASK_ULL(35, 32)
0206 #define MIO_EMM_SWITCH_CLK_HI       GENMASK_ULL(31, 16)
0207 #define MIO_EMM_SWITCH_CLK_LO       GENMASK_ULL(15, 0)
0208 
0209 /* Protoypes */
0210 irqreturn_t cvm_mmc_interrupt(int irq, void *dev_id);
0211 int cvm_mmc_of_slot_probe(struct device *dev, struct cvm_mmc_host *host);
0212 int cvm_mmc_of_slot_remove(struct cvm_mmc_slot *slot);
0213 extern const char *cvm_mmc_irq_names[];
0214 
0215 #endif
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