mmc/host/cavium-octeon.c

0001 /*
0002  * Driver for MMC and SSD cards for Cavium OCTEON SOCs.
0003  *
0004  * This file is subject to the terms and conditions of the GNU General Public
0005  * License.  See the file "COPYING" in the main directory of this archive
0006  * for more details.
0007  *
0008  * Copyright (C) 2012-2017 Cavium Inc.
0009  */
0010 #include <linux/dma-mapping.h>
0011 #include <linux/gpio/consumer.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/mmc/mmc.h>
0014 #include <linux/mmc/slot-gpio.h>
0015 #include <linux/module.h>
0016 #include <linux/of_platform.h>
0017 #include <asm/octeon/octeon.h>
0018 #include "cavium.h"
0019
0020 #define CVMX_MIO_BOOT_CTL CVMX_ADD_IO_SEG(0x00011800000000D0ull)
0021
0022 /*
0023  * The l2c* functions below are used for the EMMC-17978 workaround.
0024  *
0025  * Due to a bug in the design of the MMC bus hardware, the 2nd to last
0026  * cache block of a DMA read must be locked into the L2 Cache.
0027  * Otherwise, data corruption may occur.
0028  */
0029 static inline void *phys_to_ptr(u64 address)
0030 {
0031     return (void *)(address | (1ull << 63)); /* XKPHYS */
0032 }
0033
0034 /*
0035  * Lock a single line into L2. The line is zeroed before locking
0036  * to make sure no dram accesses are made.
0037  */
0038 static void l2c_lock_line(u64 addr)
0039 {
0040     char *addr_ptr = phys_to_ptr(addr);
0041
0042     asm volatile (
0043         "cache 31, %[line]" /* Unlock the line */
0044         ::[line] "m" (*addr_ptr));
0045 }
0046
0047 /* Unlock a single line in the L2 cache. */
0048 static void l2c_unlock_line(u64 addr)
0049 {
0050     char *addr_ptr = phys_to_ptr(addr);
0051
0052     asm volatile (
0053         "cache 23, %[line]" /* Unlock the line */
0054         ::[line] "m" (*addr_ptr));
0055 }
0056
0057 /* Locks a memory region in the L2 cache. */
0058 static void l2c_lock_mem_region(u64 start, u64 len)
0059 {
0060     u64 end;
0061
0062     /* Round start/end to cache line boundaries */
0063     end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE);
0064     start = ALIGN(start, CVMX_CACHE_LINE_SIZE);
0065
0066     while (start <= end) {
0067         l2c_lock_line(start);
0068         start += CVMX_CACHE_LINE_SIZE;
0069     }
0070     asm volatile("sync");
0071 }
0072
0073 /* Unlock a memory region in the L2 cache. */
0074 static void l2c_unlock_mem_region(u64 start, u64 len)
0075 {
0076     u64 end;
0077
0078     /* Round start/end to cache line boundaries */
0079     end = ALIGN(start + len - 1, CVMX_CACHE_LINE_SIZE);
0080     start = ALIGN(start, CVMX_CACHE_LINE_SIZE);
0081
0082     while (start <= end) {
0083         l2c_unlock_line(start);
0084         start += CVMX_CACHE_LINE_SIZE;
0085     }
0086 }
0087
0088 static void octeon_mmc_acquire_bus(struct cvm_mmc_host *host)
0089 {
0090     if (!host->has_ciu3) {
0091         down(&octeon_bootbus_sem);
0092         /* For CN70XX, switch the MMC controller onto the bus. */
0093         if (OCTEON_IS_MODEL(OCTEON_CN70XX))
0094             writeq(0, (void __iomem *)CVMX_MIO_BOOT_CTL);
0095     } else {
0096         down(&host->mmc_serializer);
0097     }
0098 }
0099
0100 static void octeon_mmc_release_bus(struct cvm_mmc_host *host)
0101 {
0102     if (!host->has_ciu3)
0103         up(&octeon_bootbus_sem);
0104     else
0105         up(&host->mmc_serializer);
0106 }
0107
0108 static void octeon_mmc_int_enable(struct cvm_mmc_host *host, u64 val)
0109 {
0110     writeq(val, host->base + MIO_EMM_INT(host));
0111     if (!host->has_ciu3)
0112         writeq(val, host->base + MIO_EMM_INT_EN(host));
0113 }
0114
0115 static void octeon_mmc_set_shared_power(struct cvm_mmc_host *host, int dir)
0116 {
0117     if (dir == 0)
0118         if (!atomic_dec_return(&host->shared_power_users))
0119             gpiod_set_value_cansleep(host->global_pwr_gpiod, 0);
0120     if (dir == 1)
0121         if (atomic_inc_return(&host->shared_power_users) == 1)
0122             gpiod_set_value_cansleep(host->global_pwr_gpiod, 1);
0123 }
0124
0125 static void octeon_mmc_dmar_fixup(struct cvm_mmc_host *host,
0126                   struct mmc_command *cmd,
0127                   struct mmc_data *data,
0128                   u64 addr)
0129 {
0130     if (cmd->opcode != MMC_WRITE_MULTIPLE_BLOCK)
0131         return;
0132     if (data->blksz * data->blocks <= 1024)
0133         return;
0134
0135     host->n_minus_one = addr + (data->blksz * data->blocks) - 1024;
0136     l2c_lock_mem_region(host->n_minus_one, 512);
0137 }
0138
0139 static void octeon_mmc_dmar_fixup_done(struct cvm_mmc_host *host)
0140 {
0141     if (!host->n_minus_one)
0142         return;
0143     l2c_unlock_mem_region(host->n_minus_one, 512);
0144     host->n_minus_one = 0;
0145 }
0146
0147 static int octeon_mmc_probe(struct platform_device *pdev)
0148 {
0149     struct device_node *cn, *node = pdev->dev.of_node;
0150     struct cvm_mmc_host *host;
0151     void __iomem *base;
0152     int mmc_irq[9];
0153     int i, ret = 0;
0154     u64 val;
0155
0156     host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
0157     if (!host)
0158         return -ENOMEM;
0159
0160     spin_lock_init(&host->irq_handler_lock);
0161     sema_init(&host->mmc_serializer, 1);
0162
0163     host->dev = &pdev->dev;
0164     host->acquire_bus = octeon_mmc_acquire_bus;
0165     host->release_bus = octeon_mmc_release_bus;
0166     host->int_enable = octeon_mmc_int_enable;
0167     host->set_shared_power = octeon_mmc_set_shared_power;
0168     if (OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
0169         OCTEON_IS_MODEL(OCTEON_CNF7XXX)) {
0170         host->dmar_fixup = octeon_mmc_dmar_fixup;
0171         host->dmar_fixup_done = octeon_mmc_dmar_fixup_done;
0172     }
0173
0174     host->sys_freq = octeon_get_io_clock_rate();
0175
0176     if (of_device_is_compatible(node, "cavium,octeon-7890-mmc")) {
0177         host->big_dma_addr = true;
0178         host->need_irq_handler_lock = true;
0179         host->has_ciu3 = true;
0180         host->use_sg = true;
0181         /*
0182          * First seven are the EMM_INT bits 0..6, then two for
0183          * the EMM_DMA_INT bits
0184          */
0185         for (i = 0; i < 9; i++) {
0186             mmc_irq[i] = platform_get_irq(pdev, i);
0187             if (mmc_irq[i] < 0)
0188                 return mmc_irq[i];
0189
0190             /* work around legacy u-boot device trees */
0191             irq_set_irq_type(mmc_irq[i], IRQ_TYPE_EDGE_RISING);
0192         }
0193     } else {
0194         host->big_dma_addr = false;
0195         host->need_irq_handler_lock = false;
0196         host->has_ciu3 = false;
0197         /* First one is EMM second DMA */
0198         for (i = 0; i < 2; i++) {
0199             mmc_irq[i] = platform_get_irq(pdev, i);
0200             if (mmc_irq[i] < 0)
0201                 return mmc_irq[i];
0202         }
0203     }
0204
0205     host->last_slot = -1;
0206
0207     base = devm_platform_ioremap_resource(pdev, 0);
0208     if (IS_ERR(base))
0209         return PTR_ERR(base);
0210     host->base = base;
0211     host->reg_off = 0;
0212
0213     base = devm_platform_ioremap_resource(pdev, 1);
0214     if (IS_ERR(base))
0215         return PTR_ERR(base);
0216     host->dma_base = base;
0217     /*
0218      * To keep the register addresses shared we intentionaly use
0219      * a negative offset here, first register used on Octeon therefore
0220      * starts at 0x20 (MIO_EMM_DMA_CFG).
0221      */
0222     host->reg_off_dma = -0x20;
0223
0224     ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
0225     if (ret)
0226         return ret;
0227
0228     /*
0229      * Clear out any pending interrupts that may be left over from
0230      * bootloader.
0231      */
0232     val = readq(host->base + MIO_EMM_INT(host));
0233     writeq(val, host->base + MIO_EMM_INT(host));
0234
0235     if (host->has_ciu3) {
0236         /* Only CMD_DONE, DMA_DONE, CMD_ERR, DMA_ERR */
0237         for (i = 1; i <= 4; i++) {
0238             ret = devm_request_irq(&pdev->dev, mmc_irq[i],
0239                            cvm_mmc_interrupt,
0240                            0, cvm_mmc_irq_names[i], host);
0241             if (ret < 0) {
0242                 dev_err(&pdev->dev, "Error: devm_request_irq %d\n",
0243                     mmc_irq[i]);
0244                 return ret;
0245             }
0246         }
0247     } else {
0248         ret = devm_request_irq(&pdev->dev, mmc_irq[0],
0249                        cvm_mmc_interrupt, 0, KBUILD_MODNAME,
0250                        host);
0251         if (ret < 0) {
0252             dev_err(&pdev->dev, "Error: devm_request_irq %d\n",
0253                 mmc_irq[0]);
0254             return ret;
0255         }
0256     }
0257
0258     host->global_pwr_gpiod = devm_gpiod_get_optional(&pdev->dev,
0259                              "power",
0260                              GPIOD_OUT_HIGH);
0261     if (IS_ERR(host->global_pwr_gpiod)) {
0262         dev_err(&pdev->dev, "Invalid power GPIO\n");
0263         return PTR_ERR(host->global_pwr_gpiod);
0264     }
0265
0266     platform_set_drvdata(pdev, host);
0267
0268     i = 0;
0269     for_each_child_of_node(node, cn) {
0270         host->slot_pdev[i] =
0271             of_platform_device_create(cn, NULL, &pdev->dev);
0272         if (!host->slot_pdev[i]) {
0273             i++;
0274             continue;
0275         }
0276         ret = cvm_mmc_of_slot_probe(&host->slot_pdev[i]->dev, host);
0277         if (ret) {
0278             dev_err(&pdev->dev, "Error populating slots\n");
0279             octeon_mmc_set_shared_power(host, 0);
0280             of_node_put(cn);
0281             goto error;
0282         }
0283         i++;
0284     }
0285     return 0;
0286
0287 error:
0288     for (i = 0; i < CAVIUM_MAX_MMC; i++) {
0289         if (host->slot[i])
0290             cvm_mmc_of_slot_remove(host->slot[i]);
0291         if (host->slot_pdev[i])
0292             of_platform_device_destroy(&host->slot_pdev[i]->dev, NULL);
0293     }
0294     return ret;
0295 }
0296
0297 static int octeon_mmc_remove(struct platform_device *pdev)
0298 {
0299     struct cvm_mmc_host *host = platform_get_drvdata(pdev);
0300     u64 dma_cfg;
0301     int i;
0302
0303     for (i = 0; i < CAVIUM_MAX_MMC; i++)
0304         if (host->slot[i])
0305             cvm_mmc_of_slot_remove(host->slot[i]);
0306
0307     dma_cfg = readq(host->dma_base + MIO_EMM_DMA_CFG(host));
0308     dma_cfg &= ~MIO_EMM_DMA_CFG_EN;
0309     writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host));
0310
0311     octeon_mmc_set_shared_power(host, 0);
0312     return 0;
0313 }
0314
0315 static const struct of_device_id octeon_mmc_match[] = {
0316     {
0317         .compatible = "cavium,octeon-6130-mmc",
0318     },
0319     {
0320         .compatible = "cavium,octeon-7890-mmc",
0321     },
0322     {},
0323 };
0324 MODULE_DEVICE_TABLE(of, octeon_mmc_match);
0325
0326 static struct platform_driver octeon_mmc_driver = {
0327     .probe      = octeon_mmc_probe,
0328     .remove     = octeon_mmc_remove,
0329     .driver     = {
0330         .name   = KBUILD_MODNAME,
0331         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
0332         .of_match_table = octeon_mmc_match,
0333     },
0334 };
0335
0336 module_platform_driver(octeon_mmc_driver);
0337
0338 MODULE_AUTHOR("Cavium Inc. <support@cavium.com>");
0339 MODULE_DESCRIPTION("Low-level driver for Cavium OCTEON MMC/SSD card");
0340 MODULE_LICENSE("GPL");