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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * bcm2835 sdhost driver.
0004  *
0005  * The 2835 has two SD controllers: The Arasan sdhci controller
0006  * (supported by the iproc driver) and a custom sdhost controller
0007  * (supported by this driver).
0008  *
0009  * The sdhci controller supports both sdcard and sdio.  The sdhost
0010  * controller supports the sdcard only, but has better performance.
0011  * Also note that the rpi3 has sdio wifi, so driving the sdcard with
0012  * the sdhost controller allows to use the sdhci controller for wifi
0013  * support.
0014  *
0015  * The configuration is done by devicetree via pin muxing.  Both
0016  * SD controller are available on the same pins (2 pin groups = pin 22
0017  * to 27 + pin 48 to 53).  So it's possible to use both SD controllers
0018  * at the same time with different pin groups.
0019  *
0020  * Author:      Phil Elwell <phil@raspberrypi.org>
0021  *              Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
0022  *
0023  * Based on
0024  *  mmc-bcm2835.c by Gellert Weisz
0025  * which is, in turn, based on
0026  *  sdhci-bcm2708.c by Broadcom
0027  *  sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
0028  *  sdhci.c and sdhci-pci.c by Pierre Ossman
0029  */
0030 #include <linux/clk.h>
0031 #include <linux/delay.h>
0032 #include <linux/device.h>
0033 #include <linux/dmaengine.h>
0034 #include <linux/dma-mapping.h>
0035 #include <linux/err.h>
0036 #include <linux/highmem.h>
0037 #include <linux/interrupt.h>
0038 #include <linux/io.h>
0039 #include <linux/iopoll.h>
0040 #include <linux/module.h>
0041 #include <linux/of_address.h>
0042 #include <linux/of_irq.h>
0043 #include <linux/platform_device.h>
0044 #include <linux/scatterlist.h>
0045 #include <linux/time.h>
0046 #include <linux/workqueue.h>
0047 
0048 #include <linux/mmc/host.h>
0049 #include <linux/mmc/mmc.h>
0050 #include <linux/mmc/sd.h>
0051 
0052 #define SDCMD  0x00 /* Command to SD card              - 16 R/W */
0053 #define SDARG  0x04 /* Argument to SD card             - 32 R/W */
0054 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
0055 #define SDCDIV 0x0c /* Start value for clock divider   - 11 R/W */
0056 #define SDRSP0 0x10 /* SD card response (31:0)         - 32 R   */
0057 #define SDRSP1 0x14 /* SD card response (63:32)        - 32 R   */
0058 #define SDRSP2 0x18 /* SD card response (95:64)        - 32 R   */
0059 #define SDRSP3 0x1c /* SD card response (127:96)       - 32 R   */
0060 #define SDHSTS 0x20 /* SD host status                  - 11 R/W */
0061 #define SDVDD  0x30 /* SD card power control           -  1 R/W */
0062 #define SDEDM  0x34 /* Emergency Debug Mode            - 13 R/W */
0063 #define SDHCFG 0x38 /* Host configuration              -  2 R/W */
0064 #define SDHBCT 0x3c /* Host byte count (debug)         - 32 R/W */
0065 #define SDDATA 0x40 /* Data to/from SD card            - 32 R/W */
0066 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC)    -  9 R/W */
0067 
0068 #define SDCMD_NEW_FLAG          0x8000
0069 #define SDCMD_FAIL_FLAG         0x4000
0070 #define SDCMD_BUSYWAIT          0x800
0071 #define SDCMD_NO_RESPONSE       0x400
0072 #define SDCMD_LONG_RESPONSE     0x200
0073 #define SDCMD_WRITE_CMD         0x80
0074 #define SDCMD_READ_CMD          0x40
0075 #define SDCMD_CMD_MASK          0x3f
0076 
0077 #define SDCDIV_MAX_CDIV         0x7ff
0078 
0079 #define SDHSTS_BUSY_IRPT        0x400
0080 #define SDHSTS_BLOCK_IRPT       0x200
0081 #define SDHSTS_SDIO_IRPT        0x100
0082 #define SDHSTS_REW_TIME_OUT     0x80
0083 #define SDHSTS_CMD_TIME_OUT     0x40
0084 #define SDHSTS_CRC16_ERROR      0x20
0085 #define SDHSTS_CRC7_ERROR       0x10
0086 #define SDHSTS_FIFO_ERROR       0x08
0087 /* Reserved */
0088 /* Reserved */
0089 #define SDHSTS_DATA_FLAG        0x01
0090 
0091 #define SDHSTS_TRANSFER_ERROR_MASK  (SDHSTS_CRC7_ERROR | \
0092                      SDHSTS_CRC16_ERROR | \
0093                      SDHSTS_REW_TIME_OUT | \
0094                      SDHSTS_FIFO_ERROR)
0095 
0096 #define SDHSTS_ERROR_MASK       (SDHSTS_CMD_TIME_OUT | \
0097                      SDHSTS_TRANSFER_ERROR_MASK)
0098 
0099 #define SDHCFG_BUSY_IRPT_EN BIT(10)
0100 #define SDHCFG_BLOCK_IRPT_EN    BIT(8)
0101 #define SDHCFG_SDIO_IRPT_EN BIT(5)
0102 #define SDHCFG_DATA_IRPT_EN BIT(4)
0103 #define SDHCFG_SLOW_CARD    BIT(3)
0104 #define SDHCFG_WIDE_EXT_BUS BIT(2)
0105 #define SDHCFG_WIDE_INT_BUS BIT(1)
0106 #define SDHCFG_REL_CMD_LINE BIT(0)
0107 
0108 #define SDVDD_POWER_OFF     0
0109 #define SDVDD_POWER_ON      1
0110 
0111 #define SDEDM_FORCE_DATA_MODE   BIT(19)
0112 #define SDEDM_CLOCK_PULSE   BIT(20)
0113 #define SDEDM_BYPASS        BIT(21)
0114 
0115 #define SDEDM_WRITE_THRESHOLD_SHIFT 9
0116 #define SDEDM_READ_THRESHOLD_SHIFT  14
0117 #define SDEDM_THRESHOLD_MASK        0x1f
0118 
0119 #define SDEDM_FSM_MASK      0xf
0120 #define SDEDM_FSM_IDENTMODE 0x0
0121 #define SDEDM_FSM_DATAMODE  0x1
0122 #define SDEDM_FSM_READDATA  0x2
0123 #define SDEDM_FSM_WRITEDATA 0x3
0124 #define SDEDM_FSM_READWAIT  0x4
0125 #define SDEDM_FSM_READCRC   0x5
0126 #define SDEDM_FSM_WRITECRC  0x6
0127 #define SDEDM_FSM_WRITEWAIT1    0x7
0128 #define SDEDM_FSM_POWERDOWN 0x8
0129 #define SDEDM_FSM_POWERUP   0x9
0130 #define SDEDM_FSM_WRITESTART1   0xa
0131 #define SDEDM_FSM_WRITESTART2   0xb
0132 #define SDEDM_FSM_GENPULSES 0xc
0133 #define SDEDM_FSM_WRITEWAIT2    0xd
0134 #define SDEDM_FSM_STARTPOWDOWN  0xf
0135 
0136 #define SDDATA_FIFO_WORDS   16
0137 
0138 #define FIFO_READ_THRESHOLD 4
0139 #define FIFO_WRITE_THRESHOLD    4
0140 #define SDDATA_FIFO_PIO_BURST   8
0141 
0142 #define PIO_THRESHOLD   1  /* Maximum block count for PIO (0 = always DMA) */
0143 
0144 struct bcm2835_host {
0145     spinlock_t      lock;
0146     struct mutex        mutex;
0147 
0148     void __iomem        *ioaddr;
0149     u32         phys_addr;
0150 
0151     struct platform_device  *pdev;
0152 
0153     int         clock;      /* Current clock speed */
0154     unsigned int        max_clk;    /* Max possible freq */
0155     struct work_struct  dma_work;
0156     struct delayed_work timeout_work;   /* Timer for timeouts */
0157     struct sg_mapping_iter  sg_miter;   /* SG state for PIO */
0158     unsigned int        blocks;     /* remaining PIO blocks */
0159     int         irq;        /* Device IRQ */
0160 
0161     u32         ns_per_fifo_word;
0162 
0163     /* cached registers */
0164     u32         hcfg;
0165     u32         cdiv;
0166 
0167     struct mmc_request  *mrq;       /* Current request */
0168     struct mmc_command  *cmd;       /* Current command */
0169     struct mmc_data     *data;      /* Current data request */
0170     bool            data_complete:1;/* Data finished before cmd */
0171     bool            use_busy:1; /* Wait for busy interrupt */
0172     bool            use_sbc:1;  /* Send CMD23 */
0173 
0174     /* for threaded irq handler */
0175     bool            irq_block;
0176     bool            irq_busy;
0177     bool            irq_data;
0178 
0179     /* DMA part */
0180     struct dma_chan     *dma_chan_rxtx;
0181     struct dma_chan     *dma_chan;
0182     struct dma_slave_config dma_cfg_rx;
0183     struct dma_slave_config dma_cfg_tx;
0184     struct dma_async_tx_descriptor  *dma_desc;
0185     u32         dma_dir;
0186     u32         drain_words;
0187     struct page     *drain_page;
0188     u32         drain_offset;
0189     bool            use_dma;
0190 };
0191 
0192 static void bcm2835_dumpcmd(struct bcm2835_host *host, struct mmc_command *cmd,
0193                 const char *label)
0194 {
0195     struct device *dev = &host->pdev->dev;
0196 
0197     if (!cmd)
0198         return;
0199 
0200     dev_dbg(dev, "%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n",
0201         (cmd == host->cmd) ? '>' : ' ',
0202         label, cmd->opcode, cmd->arg, cmd->flags,
0203         cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3],
0204         cmd->error);
0205 }
0206 
0207 static void bcm2835_dumpregs(struct bcm2835_host *host)
0208 {
0209     struct mmc_request *mrq = host->mrq;
0210     struct device *dev = &host->pdev->dev;
0211 
0212     if (mrq) {
0213         bcm2835_dumpcmd(host, mrq->sbc, "sbc");
0214         bcm2835_dumpcmd(host, mrq->cmd, "cmd");
0215         if (mrq->data) {
0216             dev_dbg(dev, "data blocks %x blksz %x - err %d\n",
0217                 mrq->data->blocks,
0218                 mrq->data->blksz,
0219                 mrq->data->error);
0220         }
0221         bcm2835_dumpcmd(host, mrq->stop, "stop");
0222     }
0223 
0224     dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
0225     dev_dbg(dev, "SDCMD  0x%08x\n", readl(host->ioaddr + SDCMD));
0226     dev_dbg(dev, "SDARG  0x%08x\n", readl(host->ioaddr + SDARG));
0227     dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
0228     dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
0229     dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
0230     dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
0231     dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
0232     dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
0233     dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
0234     dev_dbg(dev, "SDVDD  0x%08x\n", readl(host->ioaddr + SDVDD));
0235     dev_dbg(dev, "SDEDM  0x%08x\n", readl(host->ioaddr + SDEDM));
0236     dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
0237     dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
0238     dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
0239     dev_dbg(dev, "===========================================\n");
0240 }
0241 
0242 static void bcm2835_reset_internal(struct bcm2835_host *host)
0243 {
0244     u32 temp;
0245 
0246     writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
0247     writel(0, host->ioaddr + SDCMD);
0248     writel(0, host->ioaddr + SDARG);
0249     writel(0xf00000, host->ioaddr + SDTOUT);
0250     writel(0, host->ioaddr + SDCDIV);
0251     writel(0x7f8, host->ioaddr + SDHSTS); /* Write 1s to clear */
0252     writel(0, host->ioaddr + SDHCFG);
0253     writel(0, host->ioaddr + SDHBCT);
0254     writel(0, host->ioaddr + SDHBLC);
0255 
0256     /* Limit fifo usage due to silicon bug */
0257     temp = readl(host->ioaddr + SDEDM);
0258     temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
0259           (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
0260     temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
0261         (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
0262     writel(temp, host->ioaddr + SDEDM);
0263     msleep(20);
0264     writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
0265     msleep(20);
0266     host->clock = 0;
0267     writel(host->hcfg, host->ioaddr + SDHCFG);
0268     writel(host->cdiv, host->ioaddr + SDCDIV);
0269 }
0270 
0271 static void bcm2835_reset(struct mmc_host *mmc)
0272 {
0273     struct bcm2835_host *host = mmc_priv(mmc);
0274 
0275     if (host->dma_chan)
0276         dmaengine_terminate_sync(host->dma_chan);
0277     host->dma_chan = NULL;
0278     bcm2835_reset_internal(host);
0279 }
0280 
0281 static void bcm2835_finish_command(struct bcm2835_host *host);
0282 
0283 static void bcm2835_wait_transfer_complete(struct bcm2835_host *host)
0284 {
0285     int timediff;
0286     u32 alternate_idle;
0287 
0288     alternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ?
0289         SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1;
0290 
0291     timediff = 0;
0292 
0293     while (1) {
0294         u32 edm, fsm;
0295 
0296         edm = readl(host->ioaddr + SDEDM);
0297         fsm = edm & SDEDM_FSM_MASK;
0298 
0299         if ((fsm == SDEDM_FSM_IDENTMODE) ||
0300             (fsm == SDEDM_FSM_DATAMODE))
0301             break;
0302         if (fsm == alternate_idle) {
0303             writel(edm | SDEDM_FORCE_DATA_MODE,
0304                    host->ioaddr + SDEDM);
0305             break;
0306         }
0307 
0308         timediff++;
0309         if (timediff == 100000) {
0310             dev_err(&host->pdev->dev,
0311                 "wait_transfer_complete - still waiting after %d retries\n",
0312                 timediff);
0313             bcm2835_dumpregs(host);
0314             host->mrq->data->error = -ETIMEDOUT;
0315             return;
0316         }
0317         cpu_relax();
0318     }
0319 }
0320 
0321 static void bcm2835_dma_complete(void *param)
0322 {
0323     struct bcm2835_host *host = param;
0324 
0325     schedule_work(&host->dma_work);
0326 }
0327 
0328 static void bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
0329 {
0330     unsigned long flags;
0331     size_t blksize;
0332     unsigned long wait_max;
0333 
0334     blksize = host->data->blksz;
0335 
0336     wait_max = jiffies + msecs_to_jiffies(500);
0337 
0338     local_irq_save(flags);
0339 
0340     while (blksize) {
0341         int copy_words;
0342         u32 hsts = 0;
0343         size_t len;
0344         u32 *buf;
0345 
0346         if (!sg_miter_next(&host->sg_miter)) {
0347             host->data->error = -EINVAL;
0348             break;
0349         }
0350 
0351         len = min(host->sg_miter.length, blksize);
0352         if (len % 4) {
0353             host->data->error = -EINVAL;
0354             break;
0355         }
0356 
0357         blksize -= len;
0358         host->sg_miter.consumed = len;
0359 
0360         buf = (u32 *)host->sg_miter.addr;
0361 
0362         copy_words = len / 4;
0363 
0364         while (copy_words) {
0365             int burst_words, words;
0366             u32 edm;
0367 
0368             burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
0369             edm = readl(host->ioaddr + SDEDM);
0370             if (is_read)
0371                 words = ((edm >> 4) & 0x1f);
0372             else
0373                 words = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f);
0374 
0375             if (words < burst_words) {
0376                 int fsm_state = (edm & SDEDM_FSM_MASK);
0377                 struct device *dev = &host->pdev->dev;
0378 
0379                 if ((is_read &&
0380                      (fsm_state != SDEDM_FSM_READDATA &&
0381                       fsm_state != SDEDM_FSM_READWAIT &&
0382                       fsm_state != SDEDM_FSM_READCRC)) ||
0383                     (!is_read &&
0384                      (fsm_state != SDEDM_FSM_WRITEDATA &&
0385                       fsm_state != SDEDM_FSM_WRITESTART1 &&
0386                       fsm_state != SDEDM_FSM_WRITESTART2))) {
0387                     hsts = readl(host->ioaddr + SDHSTS);
0388                     dev_err(dev, "fsm %x, hsts %08x\n",
0389                         fsm_state, hsts);
0390                     if (hsts & SDHSTS_ERROR_MASK)
0391                         break;
0392                 }
0393 
0394                 if (time_after(jiffies, wait_max)) {
0395                     dev_err(dev, "PIO %s timeout - EDM %08x\n",
0396                         is_read ? "read" : "write",
0397                         edm);
0398                     hsts = SDHSTS_REW_TIME_OUT;
0399                     break;
0400                 }
0401                 ndelay((burst_words - words) *
0402                        host->ns_per_fifo_word);
0403                 continue;
0404             } else if (words > copy_words) {
0405                 words = copy_words;
0406             }
0407 
0408             copy_words -= words;
0409 
0410             while (words) {
0411                 if (is_read)
0412                     *(buf++) = readl(host->ioaddr + SDDATA);
0413                 else
0414                     writel(*(buf++), host->ioaddr + SDDATA);
0415                 words--;
0416             }
0417         }
0418 
0419         if (hsts & SDHSTS_ERROR_MASK)
0420             break;
0421     }
0422 
0423     sg_miter_stop(&host->sg_miter);
0424 
0425     local_irq_restore(flags);
0426 }
0427 
0428 static void bcm2835_transfer_pio(struct bcm2835_host *host)
0429 {
0430     struct device *dev = &host->pdev->dev;
0431     u32 sdhsts;
0432     bool is_read;
0433 
0434     is_read = (host->data->flags & MMC_DATA_READ) != 0;
0435     bcm2835_transfer_block_pio(host, is_read);
0436 
0437     sdhsts = readl(host->ioaddr + SDHSTS);
0438     if (sdhsts & (SDHSTS_CRC16_ERROR |
0439               SDHSTS_CRC7_ERROR |
0440               SDHSTS_FIFO_ERROR)) {
0441         dev_err(dev, "%s transfer error - HSTS %08x\n",
0442             is_read ? "read" : "write", sdhsts);
0443         host->data->error = -EILSEQ;
0444     } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
0445                   SDHSTS_REW_TIME_OUT))) {
0446         dev_err(dev, "%s timeout error - HSTS %08x\n",
0447             is_read ? "read" : "write", sdhsts);
0448         host->data->error = -ETIMEDOUT;
0449     }
0450 }
0451 
0452 static
0453 void bcm2835_prepare_dma(struct bcm2835_host *host, struct mmc_data *data)
0454 {
0455     int sg_len, dir_data, dir_slave;
0456     struct dma_async_tx_descriptor *desc = NULL;
0457     struct dma_chan *dma_chan;
0458 
0459     dma_chan = host->dma_chan_rxtx;
0460     if (data->flags & MMC_DATA_READ) {
0461         dir_data = DMA_FROM_DEVICE;
0462         dir_slave = DMA_DEV_TO_MEM;
0463     } else {
0464         dir_data = DMA_TO_DEVICE;
0465         dir_slave = DMA_MEM_TO_DEV;
0466     }
0467 
0468     /* The block doesn't manage the FIFO DREQs properly for
0469      * multi-block transfers, so don't attempt to DMA the final
0470      * few words.  Unfortunately this requires the final sg entry
0471      * to be trimmed.  N.B. This code demands that the overspill
0472      * is contained in a single sg entry.
0473      */
0474 
0475     host->drain_words = 0;
0476     if ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) {
0477         struct scatterlist *sg;
0478         u32 len;
0479         int i;
0480 
0481         len = min((u32)(FIFO_READ_THRESHOLD - 1) * 4,
0482               (u32)data->blocks * data->blksz);
0483 
0484         for_each_sg(data->sg, sg, data->sg_len, i) {
0485             if (sg_is_last(sg)) {
0486                 WARN_ON(sg->length < len);
0487                 sg->length -= len;
0488                 host->drain_page = sg_page(sg);
0489                 host->drain_offset = sg->offset + sg->length;
0490             }
0491         }
0492         host->drain_words = len / 4;
0493     }
0494 
0495     /* The parameters have already been validated, so this will not fail */
0496     (void)dmaengine_slave_config(dma_chan,
0497                      (dir_data == DMA_FROM_DEVICE) ?
0498                      &host->dma_cfg_rx :
0499                      &host->dma_cfg_tx);
0500 
0501     sg_len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len,
0502                 dir_data);
0503     if (!sg_len)
0504         return;
0505 
0506     desc = dmaengine_prep_slave_sg(dma_chan, data->sg, sg_len, dir_slave,
0507                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0508 
0509     if (!desc) {
0510         dma_unmap_sg(dma_chan->device->dev, data->sg, sg_len, dir_data);
0511         return;
0512     }
0513 
0514     desc->callback = bcm2835_dma_complete;
0515     desc->callback_param = host;
0516     host->dma_desc = desc;
0517     host->dma_chan = dma_chan;
0518     host->dma_dir = dir_data;
0519 }
0520 
0521 static void bcm2835_start_dma(struct bcm2835_host *host)
0522 {
0523     dmaengine_submit(host->dma_desc);
0524     dma_async_issue_pending(host->dma_chan);
0525 }
0526 
0527 static void bcm2835_set_transfer_irqs(struct bcm2835_host *host)
0528 {
0529     u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
0530         SDHCFG_BUSY_IRPT_EN;
0531 
0532     if (host->dma_desc) {
0533         host->hcfg = (host->hcfg & ~all_irqs) |
0534             SDHCFG_BUSY_IRPT_EN;
0535     } else {
0536         host->hcfg = (host->hcfg & ~all_irqs) |
0537             SDHCFG_DATA_IRPT_EN |
0538             SDHCFG_BUSY_IRPT_EN;
0539     }
0540 
0541     writel(host->hcfg, host->ioaddr + SDHCFG);
0542 }
0543 
0544 static
0545 void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
0546 {
0547     struct mmc_data *data = cmd->data;
0548 
0549     WARN_ON(host->data);
0550 
0551     host->data = data;
0552     if (!data)
0553         return;
0554 
0555     host->data_complete = false;
0556     host->data->bytes_xfered = 0;
0557 
0558     if (!host->dma_desc) {
0559         /* Use PIO */
0560         int flags = SG_MITER_ATOMIC;
0561 
0562         if (data->flags & MMC_DATA_READ)
0563             flags |= SG_MITER_TO_SG;
0564         else
0565             flags |= SG_MITER_FROM_SG;
0566         sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
0567         host->blocks = data->blocks;
0568     }
0569 
0570     bcm2835_set_transfer_irqs(host);
0571 
0572     writel(data->blksz, host->ioaddr + SDHBCT);
0573     writel(data->blocks, host->ioaddr + SDHBLC);
0574 }
0575 
0576 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host, u32 max_ms)
0577 {
0578     struct device *dev = &host->pdev->dev;
0579     u32 value;
0580     int ret;
0581 
0582     ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
0583                  !(value & SDCMD_NEW_FLAG), 1, 10);
0584     if (ret == -ETIMEDOUT)
0585         /* if it takes a while make poll interval bigger */
0586         ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
0587                      !(value & SDCMD_NEW_FLAG),
0588                      10, max_ms * 1000);
0589     if (ret == -ETIMEDOUT)
0590         dev_err(dev, "%s: timeout (%d ms)\n", __func__, max_ms);
0591 
0592     return value;
0593 }
0594 
0595 static void bcm2835_finish_request(struct bcm2835_host *host)
0596 {
0597     struct dma_chan *terminate_chan = NULL;
0598     struct mmc_request *mrq;
0599 
0600     cancel_delayed_work(&host->timeout_work);
0601 
0602     mrq = host->mrq;
0603 
0604     host->mrq = NULL;
0605     host->cmd = NULL;
0606     host->data = NULL;
0607 
0608     host->dma_desc = NULL;
0609     terminate_chan = host->dma_chan;
0610     host->dma_chan = NULL;
0611 
0612     if (terminate_chan) {
0613         int err = dmaengine_terminate_all(terminate_chan);
0614 
0615         if (err)
0616             dev_err(&host->pdev->dev,
0617                 "failed to terminate DMA (%d)\n", err);
0618     }
0619 
0620     mmc_request_done(mmc_from_priv(host), mrq);
0621 }
0622 
0623 static
0624 bool bcm2835_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
0625 {
0626     struct device *dev = &host->pdev->dev;
0627     u32 sdcmd, sdhsts;
0628     unsigned long timeout;
0629 
0630     WARN_ON(host->cmd);
0631 
0632     sdcmd = bcm2835_read_wait_sdcmd(host, 100);
0633     if (sdcmd & SDCMD_NEW_FLAG) {
0634         dev_err(dev, "previous command never completed.\n");
0635         bcm2835_dumpregs(host);
0636         cmd->error = -EILSEQ;
0637         bcm2835_finish_request(host);
0638         return false;
0639     }
0640 
0641     if (!cmd->data && cmd->busy_timeout > 9000)
0642         timeout = DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
0643     else
0644         timeout = 10 * HZ;
0645     schedule_delayed_work(&host->timeout_work, timeout);
0646 
0647     host->cmd = cmd;
0648 
0649     /* Clear any error flags */
0650     sdhsts = readl(host->ioaddr + SDHSTS);
0651     if (sdhsts & SDHSTS_ERROR_MASK)
0652         writel(sdhsts, host->ioaddr + SDHSTS);
0653 
0654     if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
0655         dev_err(dev, "unsupported response type!\n");
0656         cmd->error = -EINVAL;
0657         bcm2835_finish_request(host);
0658         return false;
0659     }
0660 
0661     bcm2835_prepare_data(host, cmd);
0662 
0663     writel(cmd->arg, host->ioaddr + SDARG);
0664 
0665     sdcmd = cmd->opcode & SDCMD_CMD_MASK;
0666 
0667     host->use_busy = false;
0668     if (!(cmd->flags & MMC_RSP_PRESENT)) {
0669         sdcmd |= SDCMD_NO_RESPONSE;
0670     } else {
0671         if (cmd->flags & MMC_RSP_136)
0672             sdcmd |= SDCMD_LONG_RESPONSE;
0673         if (cmd->flags & MMC_RSP_BUSY) {
0674             sdcmd |= SDCMD_BUSYWAIT;
0675             host->use_busy = true;
0676         }
0677     }
0678 
0679     if (cmd->data) {
0680         if (cmd->data->flags & MMC_DATA_WRITE)
0681             sdcmd |= SDCMD_WRITE_CMD;
0682         if (cmd->data->flags & MMC_DATA_READ)
0683             sdcmd |= SDCMD_READ_CMD;
0684     }
0685 
0686     writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
0687 
0688     return true;
0689 }
0690 
0691 static void bcm2835_transfer_complete(struct bcm2835_host *host)
0692 {
0693     struct mmc_data *data;
0694 
0695     WARN_ON(!host->data_complete);
0696 
0697     data = host->data;
0698     host->data = NULL;
0699 
0700     /* Need to send CMD12 if -
0701      * a) open-ended multiblock transfer (no CMD23)
0702      * b) error in multiblock transfer
0703      */
0704     if (host->mrq->stop && (data->error || !host->use_sbc)) {
0705         if (bcm2835_send_command(host, host->mrq->stop)) {
0706             /* No busy, so poll for completion */
0707             if (!host->use_busy)
0708                 bcm2835_finish_command(host);
0709         }
0710     } else {
0711         bcm2835_wait_transfer_complete(host);
0712         bcm2835_finish_request(host);
0713     }
0714 }
0715 
0716 static void bcm2835_finish_data(struct bcm2835_host *host)
0717 {
0718     struct device *dev = &host->pdev->dev;
0719     struct mmc_data *data;
0720 
0721     data = host->data;
0722 
0723     host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
0724     writel(host->hcfg, host->ioaddr + SDHCFG);
0725 
0726     data->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks);
0727 
0728     host->data_complete = true;
0729 
0730     if (host->cmd) {
0731         /* Data managed to finish before the
0732          * command completed. Make sure we do
0733          * things in the proper order.
0734          */
0735         dev_dbg(dev, "Finished early - HSTS %08x\n",
0736             readl(host->ioaddr + SDHSTS));
0737     } else {
0738         bcm2835_transfer_complete(host);
0739     }
0740 }
0741 
0742 static void bcm2835_finish_command(struct bcm2835_host *host)
0743 {
0744     struct device *dev = &host->pdev->dev;
0745     struct mmc_command *cmd = host->cmd;
0746     u32 sdcmd;
0747 
0748     sdcmd = bcm2835_read_wait_sdcmd(host, 100);
0749 
0750     /* Check for errors */
0751     if (sdcmd & SDCMD_NEW_FLAG) {
0752         dev_err(dev, "command never completed.\n");
0753         bcm2835_dumpregs(host);
0754         host->cmd->error = -EIO;
0755         bcm2835_finish_request(host);
0756         return;
0757     } else if (sdcmd & SDCMD_FAIL_FLAG) {
0758         u32 sdhsts = readl(host->ioaddr + SDHSTS);
0759 
0760         /* Clear the errors */
0761         writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
0762 
0763         if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
0764             (host->cmd->opcode != MMC_SEND_OP_COND)) {
0765             u32 edm, fsm;
0766 
0767             if (sdhsts & SDHSTS_CMD_TIME_OUT) {
0768                 host->cmd->error = -ETIMEDOUT;
0769             } else {
0770                 dev_err(dev, "unexpected command %d error\n",
0771                     host->cmd->opcode);
0772                 bcm2835_dumpregs(host);
0773                 host->cmd->error = -EILSEQ;
0774             }
0775             edm = readl(host->ioaddr + SDEDM);
0776             fsm = edm & SDEDM_FSM_MASK;
0777             if (fsm == SDEDM_FSM_READWAIT ||
0778                 fsm == SDEDM_FSM_WRITESTART1)
0779                 /* Kick the FSM out of its wait */
0780                 writel(edm | SDEDM_FORCE_DATA_MODE,
0781                        host->ioaddr + SDEDM);
0782             bcm2835_finish_request(host);
0783             return;
0784         }
0785     }
0786 
0787     if (cmd->flags & MMC_RSP_PRESENT) {
0788         if (cmd->flags & MMC_RSP_136) {
0789             int i;
0790 
0791             for (i = 0; i < 4; i++) {
0792                 cmd->resp[3 - i] =
0793                     readl(host->ioaddr + SDRSP0 + i * 4);
0794             }
0795         } else {
0796             cmd->resp[0] = readl(host->ioaddr + SDRSP0);
0797         }
0798     }
0799 
0800     if (cmd == host->mrq->sbc) {
0801         /* Finished CMD23, now send actual command. */
0802         host->cmd = NULL;
0803         if (bcm2835_send_command(host, host->mrq->cmd)) {
0804             if (host->data && host->dma_desc)
0805                 /* DMA transfer starts now, PIO starts
0806                  * after irq
0807                  */
0808                 bcm2835_start_dma(host);
0809 
0810             if (!host->use_busy)
0811                 bcm2835_finish_command(host);
0812         }
0813     } else if (cmd == host->mrq->stop) {
0814         /* Finished CMD12 */
0815         bcm2835_finish_request(host);
0816     } else {
0817         /* Processed actual command. */
0818         host->cmd = NULL;
0819         if (!host->data)
0820             bcm2835_finish_request(host);
0821         else if (host->data_complete)
0822             bcm2835_transfer_complete(host);
0823     }
0824 }
0825 
0826 static void bcm2835_timeout(struct work_struct *work)
0827 {
0828     struct delayed_work *d = to_delayed_work(work);
0829     struct bcm2835_host *host =
0830         container_of(d, struct bcm2835_host, timeout_work);
0831     struct device *dev = &host->pdev->dev;
0832 
0833     mutex_lock(&host->mutex);
0834 
0835     if (host->mrq) {
0836         dev_err(dev, "timeout waiting for hardware interrupt.\n");
0837         bcm2835_dumpregs(host);
0838 
0839         bcm2835_reset(mmc_from_priv(host));
0840 
0841         if (host->data) {
0842             host->data->error = -ETIMEDOUT;
0843             bcm2835_finish_data(host);
0844         } else {
0845             if (host->cmd)
0846                 host->cmd->error = -ETIMEDOUT;
0847             else
0848                 host->mrq->cmd->error = -ETIMEDOUT;
0849 
0850             bcm2835_finish_request(host);
0851         }
0852     }
0853 
0854     mutex_unlock(&host->mutex);
0855 }
0856 
0857 static bool bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
0858 {
0859     struct device *dev = &host->pdev->dev;
0860 
0861     if (!(intmask & SDHSTS_ERROR_MASK))
0862         return false;
0863 
0864     if (!host->cmd)
0865         return true;
0866 
0867     dev_err(dev, "sdhost_busy_irq: intmask %08x\n", intmask);
0868     if (intmask & SDHSTS_CRC7_ERROR) {
0869         host->cmd->error = -EILSEQ;
0870     } else if (intmask & (SDHSTS_CRC16_ERROR |
0871                   SDHSTS_FIFO_ERROR)) {
0872         if (host->mrq->data)
0873             host->mrq->data->error = -EILSEQ;
0874         else
0875             host->cmd->error = -EILSEQ;
0876     } else if (intmask & SDHSTS_REW_TIME_OUT) {
0877         if (host->mrq->data)
0878             host->mrq->data->error = -ETIMEDOUT;
0879         else
0880             host->cmd->error = -ETIMEDOUT;
0881     } else if (intmask & SDHSTS_CMD_TIME_OUT) {
0882         host->cmd->error = -ETIMEDOUT;
0883     }
0884     bcm2835_dumpregs(host);
0885     return true;
0886 }
0887 
0888 static void bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
0889 {
0890     if (!host->data)
0891         return;
0892     if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
0893         host->data->error = -EILSEQ;
0894     if (intmask & SDHSTS_REW_TIME_OUT)
0895         host->data->error = -ETIMEDOUT;
0896 }
0897 
0898 static void bcm2835_busy_irq(struct bcm2835_host *host)
0899 {
0900     if (WARN_ON(!host->cmd)) {
0901         bcm2835_dumpregs(host);
0902         return;
0903     }
0904 
0905     if (WARN_ON(!host->use_busy)) {
0906         bcm2835_dumpregs(host);
0907         return;
0908     }
0909     host->use_busy = false;
0910 
0911     bcm2835_finish_command(host);
0912 }
0913 
0914 static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask)
0915 {
0916     /* There are no dedicated data/space available interrupt
0917      * status bits, so it is necessary to use the single shared
0918      * data/space available FIFO status bits. It is therefore not
0919      * an error to get here when there is no data transfer in
0920      * progress.
0921      */
0922     if (!host->data)
0923         return;
0924 
0925     bcm2835_check_data_error(host, intmask);
0926     if (host->data->error)
0927         goto finished;
0928 
0929     if (host->data->flags & MMC_DATA_WRITE) {
0930         /* Use the block interrupt for writes after the first block */
0931         host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
0932         host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
0933         writel(host->hcfg, host->ioaddr + SDHCFG);
0934         bcm2835_transfer_pio(host);
0935     } else {
0936         bcm2835_transfer_pio(host);
0937         host->blocks--;
0938         if ((host->blocks == 0) || host->data->error)
0939             goto finished;
0940     }
0941     return;
0942 
0943 finished:
0944     host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
0945     writel(host->hcfg, host->ioaddr + SDHCFG);
0946 }
0947 
0948 static void bcm2835_data_threaded_irq(struct bcm2835_host *host)
0949 {
0950     if (!host->data)
0951         return;
0952     if ((host->blocks == 0) || host->data->error)
0953         bcm2835_finish_data(host);
0954 }
0955 
0956 static void bcm2835_block_irq(struct bcm2835_host *host)
0957 {
0958     if (WARN_ON(!host->data)) {
0959         bcm2835_dumpregs(host);
0960         return;
0961     }
0962 
0963     if (!host->dma_desc) {
0964         WARN_ON(!host->blocks);
0965         if (host->data->error || (--host->blocks == 0))
0966             bcm2835_finish_data(host);
0967         else
0968             bcm2835_transfer_pio(host);
0969     } else if (host->data->flags & MMC_DATA_WRITE) {
0970         bcm2835_finish_data(host);
0971     }
0972 }
0973 
0974 static irqreturn_t bcm2835_irq(int irq, void *dev_id)
0975 {
0976     irqreturn_t result = IRQ_NONE;
0977     struct bcm2835_host *host = dev_id;
0978     u32 intmask;
0979 
0980     spin_lock(&host->lock);
0981 
0982     intmask = readl(host->ioaddr + SDHSTS);
0983 
0984     writel(SDHSTS_BUSY_IRPT |
0985            SDHSTS_BLOCK_IRPT |
0986            SDHSTS_SDIO_IRPT |
0987            SDHSTS_DATA_FLAG,
0988            host->ioaddr + SDHSTS);
0989 
0990     if (intmask & SDHSTS_BLOCK_IRPT) {
0991         bcm2835_check_data_error(host, intmask);
0992         host->irq_block = true;
0993         result = IRQ_WAKE_THREAD;
0994     }
0995 
0996     if (intmask & SDHSTS_BUSY_IRPT) {
0997         if (!bcm2835_check_cmd_error(host, intmask)) {
0998             host->irq_busy = true;
0999             result = IRQ_WAKE_THREAD;
1000         } else {
1001             result = IRQ_HANDLED;
1002         }
1003     }
1004 
1005     /* There is no true data interrupt status bit, so it is
1006      * necessary to qualify the data flag with the interrupt
1007      * enable bit.
1008      */
1009     if ((intmask & SDHSTS_DATA_FLAG) &&
1010         (host->hcfg & SDHCFG_DATA_IRPT_EN)) {
1011         bcm2835_data_irq(host, intmask);
1012         host->irq_data = true;
1013         result = IRQ_WAKE_THREAD;
1014     }
1015 
1016     spin_unlock(&host->lock);
1017 
1018     return result;
1019 }
1020 
1021 static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id)
1022 {
1023     struct bcm2835_host *host = dev_id;
1024     unsigned long flags;
1025     bool block, busy, data;
1026 
1027     spin_lock_irqsave(&host->lock, flags);
1028 
1029     block = host->irq_block;
1030     busy  = host->irq_busy;
1031     data  = host->irq_data;
1032     host->irq_block = false;
1033     host->irq_busy  = false;
1034     host->irq_data  = false;
1035 
1036     spin_unlock_irqrestore(&host->lock, flags);
1037 
1038     mutex_lock(&host->mutex);
1039 
1040     if (block)
1041         bcm2835_block_irq(host);
1042     if (busy)
1043         bcm2835_busy_irq(host);
1044     if (data)
1045         bcm2835_data_threaded_irq(host);
1046 
1047     mutex_unlock(&host->mutex);
1048 
1049     return IRQ_HANDLED;
1050 }
1051 
1052 static void bcm2835_dma_complete_work(struct work_struct *work)
1053 {
1054     struct bcm2835_host *host =
1055         container_of(work, struct bcm2835_host, dma_work);
1056     struct mmc_data *data;
1057 
1058     mutex_lock(&host->mutex);
1059 
1060     data = host->data;
1061 
1062     if (host->dma_chan) {
1063         dma_unmap_sg(host->dma_chan->device->dev,
1064                  data->sg, data->sg_len,
1065                  host->dma_dir);
1066 
1067         host->dma_chan = NULL;
1068     }
1069 
1070     if (host->drain_words) {
1071         unsigned long flags;
1072         void *page;
1073         u32 *buf;
1074 
1075         if (host->drain_offset & PAGE_MASK) {
1076             host->drain_page += host->drain_offset >> PAGE_SHIFT;
1077             host->drain_offset &= ~PAGE_MASK;
1078         }
1079         local_irq_save(flags);
1080         page = kmap_atomic(host->drain_page);
1081         buf = page + host->drain_offset;
1082 
1083         while (host->drain_words) {
1084             u32 edm = readl(host->ioaddr + SDEDM);
1085 
1086             if ((edm >> 4) & 0x1f)
1087                 *(buf++) = readl(host->ioaddr + SDDATA);
1088             host->drain_words--;
1089         }
1090 
1091         kunmap_atomic(page);
1092         local_irq_restore(flags);
1093     }
1094 
1095     bcm2835_finish_data(host);
1096 
1097     mutex_unlock(&host->mutex);
1098 }
1099 
1100 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
1101 {
1102     struct mmc_host *mmc = mmc_from_priv(host);
1103     int div;
1104 
1105     /* The SDCDIV register has 11 bits, and holds (div - 2).  But
1106      * in data mode the max is 50MHz wihout a minimum, and only
1107      * the bottom 3 bits are used. Since the switch over is
1108      * automatic (unless we have marked the card as slow...),
1109      * chosen values have to make sense in both modes.  Ident mode
1110      * must be 100-400KHz, so can range check the requested
1111      * clock. CMD15 must be used to return to data mode, so this
1112      * can be monitored.
1113      *
1114      * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
1115      *                 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
1116      *
1117      *       623->400KHz/27.8MHz
1118      *       reset value (507)->491159/50MHz
1119      *
1120      * BUT, the 3-bit clock divisor in data mode is too small if
1121      * the core clock is higher than 250MHz, so instead use the
1122      * SLOW_CARD configuration bit to force the use of the ident
1123      * clock divisor at all times.
1124      */
1125 
1126     if (clock < 100000) {
1127         /* Can't stop the clock, but make it as slow as possible
1128          * to show willing
1129          */
1130         host->cdiv = SDCDIV_MAX_CDIV;
1131         writel(host->cdiv, host->ioaddr + SDCDIV);
1132         return;
1133     }
1134 
1135     div = host->max_clk / clock;
1136     if (div < 2)
1137         div = 2;
1138     if ((host->max_clk / div) > clock)
1139         div++;
1140     div -= 2;
1141 
1142     if (div > SDCDIV_MAX_CDIV)
1143         div = SDCDIV_MAX_CDIV;
1144 
1145     clock = host->max_clk / (div + 2);
1146     mmc->actual_clock = clock;
1147 
1148     /* Calibrate some delays */
1149 
1150     host->ns_per_fifo_word = (1000000000 / clock) *
1151         ((mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32);
1152 
1153     host->cdiv = div;
1154     writel(host->cdiv, host->ioaddr + SDCDIV);
1155 
1156     /* Set the timeout to 500ms */
1157     writel(mmc->actual_clock / 2, host->ioaddr + SDTOUT);
1158 }
1159 
1160 static void bcm2835_request(struct mmc_host *mmc, struct mmc_request *mrq)
1161 {
1162     struct bcm2835_host *host = mmc_priv(mmc);
1163     struct device *dev = &host->pdev->dev;
1164     u32 edm, fsm;
1165 
1166     /* Reset the error statuses in case this is a retry */
1167     if (mrq->sbc)
1168         mrq->sbc->error = 0;
1169     if (mrq->cmd)
1170         mrq->cmd->error = 0;
1171     if (mrq->data)
1172         mrq->data->error = 0;
1173     if (mrq->stop)
1174         mrq->stop->error = 0;
1175 
1176     if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
1177         dev_err(dev, "unsupported block size (%d bytes)\n",
1178             mrq->data->blksz);
1179 
1180         if (mrq->cmd)
1181             mrq->cmd->error = -EINVAL;
1182 
1183         mmc_request_done(mmc, mrq);
1184         return;
1185     }
1186 
1187     mutex_lock(&host->mutex);
1188 
1189     WARN_ON(host->mrq);
1190     host->mrq = mrq;
1191 
1192     edm = readl(host->ioaddr + SDEDM);
1193     fsm = edm & SDEDM_FSM_MASK;
1194 
1195     if ((fsm != SDEDM_FSM_IDENTMODE) &&
1196         (fsm != SDEDM_FSM_DATAMODE)) {
1197         dev_err(dev, "previous command (%d) not complete (EDM %08x)\n",
1198             readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK,
1199             edm);
1200         bcm2835_dumpregs(host);
1201 
1202         if (mrq->cmd)
1203             mrq->cmd->error = -EILSEQ;
1204 
1205         bcm2835_finish_request(host);
1206         mutex_unlock(&host->mutex);
1207         return;
1208     }
1209 
1210     if (host->use_dma && mrq->data && (mrq->data->blocks > PIO_THRESHOLD))
1211         bcm2835_prepare_dma(host, mrq->data);
1212 
1213     host->use_sbc = !!mrq->sbc && host->mrq->data &&
1214             (host->mrq->data->flags & MMC_DATA_READ);
1215     if (host->use_sbc) {
1216         if (bcm2835_send_command(host, mrq->sbc)) {
1217             if (!host->use_busy)
1218                 bcm2835_finish_command(host);
1219         }
1220     } else if (mrq->cmd && bcm2835_send_command(host, mrq->cmd)) {
1221         if (host->data && host->dma_desc) {
1222             /* DMA transfer starts now, PIO starts after irq */
1223             bcm2835_start_dma(host);
1224         }
1225 
1226         if (!host->use_busy)
1227             bcm2835_finish_command(host);
1228     }
1229 
1230     mutex_unlock(&host->mutex);
1231 }
1232 
1233 static void bcm2835_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1234 {
1235     struct bcm2835_host *host = mmc_priv(mmc);
1236 
1237     mutex_lock(&host->mutex);
1238 
1239     if (!ios->clock || ios->clock != host->clock) {
1240         bcm2835_set_clock(host, ios->clock);
1241         host->clock = ios->clock;
1242     }
1243 
1244     /* set bus width */
1245     host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
1246     if (ios->bus_width == MMC_BUS_WIDTH_4)
1247         host->hcfg |= SDHCFG_WIDE_EXT_BUS;
1248 
1249     host->hcfg |= SDHCFG_WIDE_INT_BUS;
1250 
1251     /* Disable clever clock switching, to cope with fast core clocks */
1252     host->hcfg |= SDHCFG_SLOW_CARD;
1253 
1254     writel(host->hcfg, host->ioaddr + SDHCFG);
1255 
1256     mutex_unlock(&host->mutex);
1257 }
1258 
1259 static const struct mmc_host_ops bcm2835_ops = {
1260     .request = bcm2835_request,
1261     .set_ios = bcm2835_set_ios,
1262     .card_hw_reset = bcm2835_reset,
1263 };
1264 
1265 static int bcm2835_add_host(struct bcm2835_host *host)
1266 {
1267     struct mmc_host *mmc = mmc_from_priv(host);
1268     struct device *dev = &host->pdev->dev;
1269     char pio_limit_string[20];
1270     int ret;
1271 
1272     if (!mmc->f_max || mmc->f_max > host->max_clk)
1273         mmc->f_max = host->max_clk;
1274     mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
1275 
1276     mmc->max_busy_timeout = ~0 / (mmc->f_max / 1000);
1277 
1278     dev_dbg(dev, "f_max %d, f_min %d, max_busy_timeout %d\n",
1279         mmc->f_max, mmc->f_min, mmc->max_busy_timeout);
1280 
1281     /* host controller capabilities */
1282     mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
1283              MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_CMD23;
1284 
1285     spin_lock_init(&host->lock);
1286     mutex_init(&host->mutex);
1287 
1288     if (!host->dma_chan_rxtx) {
1289         dev_warn(dev, "unable to initialise DMA channel. Falling back to PIO\n");
1290         host->use_dma = false;
1291     } else {
1292         host->use_dma = true;
1293 
1294         host->dma_cfg_tx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1295         host->dma_cfg_tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1296         host->dma_cfg_tx.direction = DMA_MEM_TO_DEV;
1297         host->dma_cfg_tx.src_addr = 0;
1298         host->dma_cfg_tx.dst_addr = host->phys_addr + SDDATA;
1299 
1300         host->dma_cfg_rx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1301         host->dma_cfg_rx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1302         host->dma_cfg_rx.direction = DMA_DEV_TO_MEM;
1303         host->dma_cfg_rx.src_addr = host->phys_addr + SDDATA;
1304         host->dma_cfg_rx.dst_addr = 0;
1305 
1306         if (dmaengine_slave_config(host->dma_chan_rxtx,
1307                        &host->dma_cfg_tx) != 0 ||
1308             dmaengine_slave_config(host->dma_chan_rxtx,
1309                        &host->dma_cfg_rx) != 0)
1310             host->use_dma = false;
1311     }
1312 
1313     mmc->max_segs = 128;
1314     mmc->max_req_size = min_t(size_t, 524288, dma_max_mapping_size(dev));
1315     mmc->max_seg_size = mmc->max_req_size;
1316     mmc->max_blk_size = 1024;
1317     mmc->max_blk_count =  65535;
1318 
1319     /* report supported voltage ranges */
1320     mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1321 
1322     INIT_WORK(&host->dma_work, bcm2835_dma_complete_work);
1323     INIT_DELAYED_WORK(&host->timeout_work, bcm2835_timeout);
1324 
1325     /* Set interrupt enables */
1326     host->hcfg = SDHCFG_BUSY_IRPT_EN;
1327 
1328     bcm2835_reset_internal(host);
1329 
1330     ret = request_threaded_irq(host->irq, bcm2835_irq,
1331                    bcm2835_threaded_irq,
1332                    0, mmc_hostname(mmc), host);
1333     if (ret) {
1334         dev_err(dev, "failed to request IRQ %d: %d\n", host->irq, ret);
1335         return ret;
1336     }
1337 
1338     ret = mmc_add_host(mmc);
1339     if (ret) {
1340         free_irq(host->irq, host);
1341         return ret;
1342     }
1343 
1344     pio_limit_string[0] = '\0';
1345     if (host->use_dma && (PIO_THRESHOLD > 0))
1346         sprintf(pio_limit_string, " (>%d)", PIO_THRESHOLD);
1347     dev_info(dev, "loaded - DMA %s%s\n",
1348          host->use_dma ? "enabled" : "disabled", pio_limit_string);
1349 
1350     return 0;
1351 }
1352 
1353 static int bcm2835_probe(struct platform_device *pdev)
1354 {
1355     struct device *dev = &pdev->dev;
1356     struct clk *clk;
1357     struct bcm2835_host *host;
1358     struct mmc_host *mmc;
1359     const __be32 *regaddr_p;
1360     int ret;
1361 
1362     dev_dbg(dev, "%s\n", __func__);
1363     mmc = mmc_alloc_host(sizeof(*host), dev);
1364     if (!mmc)
1365         return -ENOMEM;
1366 
1367     mmc->ops = &bcm2835_ops;
1368     host = mmc_priv(mmc);
1369     host->pdev = pdev;
1370     spin_lock_init(&host->lock);
1371 
1372     host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
1373     if (IS_ERR(host->ioaddr)) {
1374         ret = PTR_ERR(host->ioaddr);
1375         goto err;
1376     }
1377 
1378     /* Parse OF address directly to get the physical address for
1379      * DMA to our registers.
1380      */
1381     regaddr_p = of_get_address(pdev->dev.of_node, 0, NULL, NULL);
1382     if (!regaddr_p) {
1383         dev_err(dev, "Can't get phys address\n");
1384         ret = -EINVAL;
1385         goto err;
1386     }
1387 
1388     host->phys_addr = be32_to_cpup(regaddr_p);
1389 
1390     host->dma_chan = NULL;
1391     host->dma_desc = NULL;
1392 
1393     host->dma_chan_rxtx = dma_request_chan(dev, "rx-tx");
1394     if (IS_ERR(host->dma_chan_rxtx)) {
1395         ret = PTR_ERR(host->dma_chan_rxtx);
1396         host->dma_chan_rxtx = NULL;
1397 
1398         if (ret == -EPROBE_DEFER)
1399             goto err;
1400 
1401         /* Ignore errors to fall back to PIO mode */
1402     }
1403 
1404 
1405     clk = devm_clk_get(dev, NULL);
1406     if (IS_ERR(clk)) {
1407         ret = dev_err_probe(dev, PTR_ERR(clk), "could not get clk\n");
1408         goto err;
1409     }
1410 
1411     host->max_clk = clk_get_rate(clk);
1412 
1413     host->irq = platform_get_irq(pdev, 0);
1414     if (host->irq <= 0) {
1415         ret = -EINVAL;
1416         goto err;
1417     }
1418 
1419     ret = mmc_of_parse(mmc);
1420     if (ret)
1421         goto err;
1422 
1423     ret = bcm2835_add_host(host);
1424     if (ret)
1425         goto err;
1426 
1427     platform_set_drvdata(pdev, host);
1428 
1429     dev_dbg(dev, "%s -> OK\n", __func__);
1430 
1431     return 0;
1432 
1433 err:
1434     dev_dbg(dev, "%s -> err %d\n", __func__, ret);
1435     if (host->dma_chan_rxtx)
1436         dma_release_channel(host->dma_chan_rxtx);
1437     mmc_free_host(mmc);
1438 
1439     return ret;
1440 }
1441 
1442 static int bcm2835_remove(struct platform_device *pdev)
1443 {
1444     struct bcm2835_host *host = platform_get_drvdata(pdev);
1445     struct mmc_host *mmc = mmc_from_priv(host);
1446 
1447     mmc_remove_host(mmc);
1448 
1449     writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
1450 
1451     free_irq(host->irq, host);
1452 
1453     cancel_work_sync(&host->dma_work);
1454     cancel_delayed_work_sync(&host->timeout_work);
1455 
1456     if (host->dma_chan_rxtx)
1457         dma_release_channel(host->dma_chan_rxtx);
1458 
1459     mmc_free_host(mmc);
1460 
1461     return 0;
1462 }
1463 
1464 static const struct of_device_id bcm2835_match[] = {
1465     { .compatible = "brcm,bcm2835-sdhost" },
1466     { }
1467 };
1468 MODULE_DEVICE_TABLE(of, bcm2835_match);
1469 
1470 static struct platform_driver bcm2835_driver = {
1471     .probe      = bcm2835_probe,
1472     .remove     = bcm2835_remove,
1473     .driver     = {
1474         .name       = "sdhost-bcm2835",
1475         .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1476         .of_match_table = bcm2835_match,
1477     },
1478 };
1479 module_platform_driver(bcm2835_driver);
1480 
1481 MODULE_ALIAS("platform:sdhost-bcm2835");
1482 MODULE_DESCRIPTION("BCM2835 SDHost driver");
1483 MODULE_LICENSE("GPL v2");
1484 MODULE_AUTHOR("Phil Elwell");
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