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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /**
0003  * Host side test driver to test endpoint functionality
0004  *
0005  * Copyright (C) 2017 Texas Instruments
0006  * Author: Kishon Vijay Abraham I <kishon@ti.com>
0007  */
0008 
0009 #include <linux/crc32.h>
0010 #include <linux/delay.h>
0011 #include <linux/fs.h>
0012 #include <linux/io.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/irq.h>
0015 #include <linux/miscdevice.h>
0016 #include <linux/module.h>
0017 #include <linux/mutex.h>
0018 #include <linux/random.h>
0019 #include <linux/slab.h>
0020 #include <linux/uaccess.h>
0021 #include <linux/pci.h>
0022 #include <linux/pci_ids.h>
0023 
0024 #include <linux/pci_regs.h>
0025 
0026 #include <uapi/linux/pcitest.h>
0027 
0028 #define DRV_MODULE_NAME             "pci-endpoint-test"
0029 
0030 #define IRQ_TYPE_UNDEFINED          -1
0031 #define IRQ_TYPE_LEGACY             0
0032 #define IRQ_TYPE_MSI                1
0033 #define IRQ_TYPE_MSIX               2
0034 
0035 #define PCI_ENDPOINT_TEST_MAGIC         0x0
0036 
0037 #define PCI_ENDPOINT_TEST_COMMAND       0x4
0038 #define COMMAND_RAISE_LEGACY_IRQ        BIT(0)
0039 #define COMMAND_RAISE_MSI_IRQ           BIT(1)
0040 #define COMMAND_RAISE_MSIX_IRQ          BIT(2)
0041 #define COMMAND_READ                BIT(3)
0042 #define COMMAND_WRITE               BIT(4)
0043 #define COMMAND_COPY                BIT(5)
0044 
0045 #define PCI_ENDPOINT_TEST_STATUS        0x8
0046 #define STATUS_READ_SUCCESS         BIT(0)
0047 #define STATUS_READ_FAIL            BIT(1)
0048 #define STATUS_WRITE_SUCCESS            BIT(2)
0049 #define STATUS_WRITE_FAIL           BIT(3)
0050 #define STATUS_COPY_SUCCESS         BIT(4)
0051 #define STATUS_COPY_FAIL            BIT(5)
0052 #define STATUS_IRQ_RAISED           BIT(6)
0053 #define STATUS_SRC_ADDR_INVALID         BIT(7)
0054 #define STATUS_DST_ADDR_INVALID         BIT(8)
0055 
0056 #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR    0x0c
0057 #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR    0x10
0058 
0059 #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR    0x14
0060 #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR    0x18
0061 
0062 #define PCI_ENDPOINT_TEST_SIZE          0x1c
0063 #define PCI_ENDPOINT_TEST_CHECKSUM      0x20
0064 
0065 #define PCI_ENDPOINT_TEST_IRQ_TYPE      0x24
0066 #define PCI_ENDPOINT_TEST_IRQ_NUMBER        0x28
0067 
0068 #define PCI_ENDPOINT_TEST_FLAGS         0x2c
0069 #define FLAG_USE_DMA                BIT(0)
0070 
0071 #define PCI_DEVICE_ID_TI_AM654          0xb00c
0072 #define PCI_DEVICE_ID_TI_J7200          0xb00f
0073 #define PCI_DEVICE_ID_TI_AM64           0xb010
0074 #define PCI_DEVICE_ID_LS1088A           0x80c0
0075 
0076 #define is_am654_pci_dev(pdev)      \
0077         ((pdev)->device == PCI_DEVICE_ID_TI_AM654)
0078 
0079 #define PCI_DEVICE_ID_RENESAS_R8A774A1      0x0028
0080 #define PCI_DEVICE_ID_RENESAS_R8A774B1      0x002b
0081 #define PCI_DEVICE_ID_RENESAS_R8A774C0      0x002d
0082 #define PCI_DEVICE_ID_RENESAS_R8A774E1      0x0025
0083 
0084 static DEFINE_IDA(pci_endpoint_test_ida);
0085 
0086 #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
0087                         miscdev)
0088 
0089 static bool no_msi;
0090 module_param(no_msi, bool, 0444);
0091 MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
0092 
0093 static int irq_type = IRQ_TYPE_MSI;
0094 module_param(irq_type, int, 0444);
0095 MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
0096 
0097 enum pci_barno {
0098     BAR_0,
0099     BAR_1,
0100     BAR_2,
0101     BAR_3,
0102     BAR_4,
0103     BAR_5,
0104 };
0105 
0106 struct pci_endpoint_test {
0107     struct pci_dev  *pdev;
0108     void __iomem    *base;
0109     void __iomem    *bar[PCI_STD_NUM_BARS];
0110     struct completion irq_raised;
0111     int     last_irq;
0112     int     num_irqs;
0113     int     irq_type;
0114     /* mutex to protect the ioctls */
0115     struct mutex    mutex;
0116     struct miscdevice miscdev;
0117     enum pci_barno test_reg_bar;
0118     size_t alignment;
0119     const char *name;
0120 };
0121 
0122 struct pci_endpoint_test_data {
0123     enum pci_barno test_reg_bar;
0124     size_t alignment;
0125     int irq_type;
0126 };
0127 
0128 static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
0129                       u32 offset)
0130 {
0131     return readl(test->base + offset);
0132 }
0133 
0134 static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
0135                         u32 offset, u32 value)
0136 {
0137     writel(value, test->base + offset);
0138 }
0139 
0140 static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
0141                           int bar, int offset)
0142 {
0143     return readl(test->bar[bar] + offset);
0144 }
0145 
0146 static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
0147                         int bar, u32 offset, u32 value)
0148 {
0149     writel(value, test->bar[bar] + offset);
0150 }
0151 
0152 static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
0153 {
0154     struct pci_endpoint_test *test = dev_id;
0155     u32 reg;
0156 
0157     reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
0158     if (reg & STATUS_IRQ_RAISED) {
0159         test->last_irq = irq;
0160         complete(&test->irq_raised);
0161         reg &= ~STATUS_IRQ_RAISED;
0162     }
0163     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_STATUS,
0164                  reg);
0165 
0166     return IRQ_HANDLED;
0167 }
0168 
0169 static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
0170 {
0171     struct pci_dev *pdev = test->pdev;
0172 
0173     pci_free_irq_vectors(pdev);
0174     test->irq_type = IRQ_TYPE_UNDEFINED;
0175 }
0176 
0177 static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
0178                         int type)
0179 {
0180     int irq = -1;
0181     struct pci_dev *pdev = test->pdev;
0182     struct device *dev = &pdev->dev;
0183     bool res = true;
0184 
0185     switch (type) {
0186     case IRQ_TYPE_LEGACY:
0187         irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
0188         if (irq < 0)
0189             dev_err(dev, "Failed to get Legacy interrupt\n");
0190         break;
0191     case IRQ_TYPE_MSI:
0192         irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
0193         if (irq < 0)
0194             dev_err(dev, "Failed to get MSI interrupts\n");
0195         break;
0196     case IRQ_TYPE_MSIX:
0197         irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
0198         if (irq < 0)
0199             dev_err(dev, "Failed to get MSI-X interrupts\n");
0200         break;
0201     default:
0202         dev_err(dev, "Invalid IRQ type selected\n");
0203     }
0204 
0205     if (irq < 0) {
0206         irq = 0;
0207         res = false;
0208     }
0209 
0210     test->irq_type = type;
0211     test->num_irqs = irq;
0212 
0213     return res;
0214 }
0215 
0216 static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
0217 {
0218     int i;
0219     struct pci_dev *pdev = test->pdev;
0220     struct device *dev = &pdev->dev;
0221 
0222     for (i = 0; i < test->num_irqs; i++)
0223         devm_free_irq(dev, pci_irq_vector(pdev, i), test);
0224 
0225     test->num_irqs = 0;
0226 }
0227 
0228 static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
0229 {
0230     int i;
0231     int err;
0232     struct pci_dev *pdev = test->pdev;
0233     struct device *dev = &pdev->dev;
0234 
0235     for (i = 0; i < test->num_irqs; i++) {
0236         err = devm_request_irq(dev, pci_irq_vector(pdev, i),
0237                        pci_endpoint_test_irqhandler,
0238                        IRQF_SHARED, test->name, test);
0239         if (err)
0240             goto fail;
0241     }
0242 
0243     return true;
0244 
0245 fail:
0246     switch (irq_type) {
0247     case IRQ_TYPE_LEGACY:
0248         dev_err(dev, "Failed to request IRQ %d for Legacy\n",
0249             pci_irq_vector(pdev, i));
0250         break;
0251     case IRQ_TYPE_MSI:
0252         dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
0253             pci_irq_vector(pdev, i),
0254             i + 1);
0255         break;
0256     case IRQ_TYPE_MSIX:
0257         dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
0258             pci_irq_vector(pdev, i),
0259             i + 1);
0260         break;
0261     }
0262 
0263     return false;
0264 }
0265 
0266 static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
0267                   enum pci_barno barno)
0268 {
0269     int j;
0270     u32 val;
0271     int size;
0272     struct pci_dev *pdev = test->pdev;
0273 
0274     if (!test->bar[barno])
0275         return false;
0276 
0277     size = pci_resource_len(pdev, barno);
0278 
0279     if (barno == test->test_reg_bar)
0280         size = 0x4;
0281 
0282     for (j = 0; j < size; j += 4)
0283         pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
0284 
0285     for (j = 0; j < size; j += 4) {
0286         val = pci_endpoint_test_bar_readl(test, barno, j);
0287         if (val != 0xA0A0A0A0)
0288             return false;
0289     }
0290 
0291     return true;
0292 }
0293 
0294 static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
0295 {
0296     u32 val;
0297 
0298     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
0299                  IRQ_TYPE_LEGACY);
0300     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
0301     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
0302                  COMMAND_RAISE_LEGACY_IRQ);
0303     val = wait_for_completion_timeout(&test->irq_raised,
0304                       msecs_to_jiffies(1000));
0305     if (!val)
0306         return false;
0307 
0308     return true;
0309 }
0310 
0311 static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
0312                        u16 msi_num, bool msix)
0313 {
0314     u32 val;
0315     struct pci_dev *pdev = test->pdev;
0316 
0317     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
0318                  msix == false ? IRQ_TYPE_MSI :
0319                  IRQ_TYPE_MSIX);
0320     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
0321     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
0322                  msix == false ? COMMAND_RAISE_MSI_IRQ :
0323                  COMMAND_RAISE_MSIX_IRQ);
0324     val = wait_for_completion_timeout(&test->irq_raised,
0325                       msecs_to_jiffies(1000));
0326     if (!val)
0327         return false;
0328 
0329     if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
0330         return true;
0331 
0332     return false;
0333 }
0334 
0335 static bool pci_endpoint_test_copy(struct pci_endpoint_test *test,
0336                    unsigned long arg)
0337 {
0338     struct pci_endpoint_test_xfer_param param;
0339     bool ret = false;
0340     void *src_addr;
0341     void *dst_addr;
0342     u32 flags = 0;
0343     bool use_dma;
0344     size_t size;
0345     dma_addr_t src_phys_addr;
0346     dma_addr_t dst_phys_addr;
0347     struct pci_dev *pdev = test->pdev;
0348     struct device *dev = &pdev->dev;
0349     void *orig_src_addr;
0350     dma_addr_t orig_src_phys_addr;
0351     void *orig_dst_addr;
0352     dma_addr_t orig_dst_phys_addr;
0353     size_t offset;
0354     size_t alignment = test->alignment;
0355     int irq_type = test->irq_type;
0356     u32 src_crc32;
0357     u32 dst_crc32;
0358     int err;
0359 
0360     err = copy_from_user(&param, (void __user *)arg, sizeof(param));
0361     if (err) {
0362         dev_err(dev, "Failed to get transfer param\n");
0363         return false;
0364     }
0365 
0366     size = param.size;
0367     if (size > SIZE_MAX - alignment)
0368         goto err;
0369 
0370     use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
0371     if (use_dma)
0372         flags |= FLAG_USE_DMA;
0373 
0374     if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
0375         dev_err(dev, "Invalid IRQ type option\n");
0376         goto err;
0377     }
0378 
0379     orig_src_addr = kzalloc(size + alignment, GFP_KERNEL);
0380     if (!orig_src_addr) {
0381         dev_err(dev, "Failed to allocate source buffer\n");
0382         ret = false;
0383         goto err;
0384     }
0385 
0386     get_random_bytes(orig_src_addr, size + alignment);
0387     orig_src_phys_addr = dma_map_single(dev, orig_src_addr,
0388                         size + alignment, DMA_TO_DEVICE);
0389     if (dma_mapping_error(dev, orig_src_phys_addr)) {
0390         dev_err(dev, "failed to map source buffer address\n");
0391         ret = false;
0392         goto err_src_phys_addr;
0393     }
0394 
0395     if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
0396         src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
0397         offset = src_phys_addr - orig_src_phys_addr;
0398         src_addr = orig_src_addr + offset;
0399     } else {
0400         src_phys_addr = orig_src_phys_addr;
0401         src_addr = orig_src_addr;
0402     }
0403 
0404     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
0405                  lower_32_bits(src_phys_addr));
0406 
0407     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
0408                  upper_32_bits(src_phys_addr));
0409 
0410     src_crc32 = crc32_le(~0, src_addr, size);
0411 
0412     orig_dst_addr = kzalloc(size + alignment, GFP_KERNEL);
0413     if (!orig_dst_addr) {
0414         dev_err(dev, "Failed to allocate destination address\n");
0415         ret = false;
0416         goto err_dst_addr;
0417     }
0418 
0419     orig_dst_phys_addr = dma_map_single(dev, orig_dst_addr,
0420                         size + alignment, DMA_FROM_DEVICE);
0421     if (dma_mapping_error(dev, orig_dst_phys_addr)) {
0422         dev_err(dev, "failed to map destination buffer address\n");
0423         ret = false;
0424         goto err_dst_phys_addr;
0425     }
0426 
0427     if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
0428         dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
0429         offset = dst_phys_addr - orig_dst_phys_addr;
0430         dst_addr = orig_dst_addr + offset;
0431     } else {
0432         dst_phys_addr = orig_dst_phys_addr;
0433         dst_addr = orig_dst_addr;
0434     }
0435 
0436     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
0437                  lower_32_bits(dst_phys_addr));
0438     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
0439                  upper_32_bits(dst_phys_addr));
0440 
0441     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
0442                  size);
0443 
0444     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
0445     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
0446     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
0447     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
0448                  COMMAND_COPY);
0449 
0450     wait_for_completion(&test->irq_raised);
0451 
0452     dma_unmap_single(dev, orig_dst_phys_addr, size + alignment,
0453              DMA_FROM_DEVICE);
0454 
0455     dst_crc32 = crc32_le(~0, dst_addr, size);
0456     if (dst_crc32 == src_crc32)
0457         ret = true;
0458 
0459 err_dst_phys_addr:
0460     kfree(orig_dst_addr);
0461 
0462 err_dst_addr:
0463     dma_unmap_single(dev, orig_src_phys_addr, size + alignment,
0464              DMA_TO_DEVICE);
0465 
0466 err_src_phys_addr:
0467     kfree(orig_src_addr);
0468 
0469 err:
0470     return ret;
0471 }
0472 
0473 static bool pci_endpoint_test_write(struct pci_endpoint_test *test,
0474                     unsigned long arg)
0475 {
0476     struct pci_endpoint_test_xfer_param param;
0477     bool ret = false;
0478     u32 flags = 0;
0479     bool use_dma;
0480     u32 reg;
0481     void *addr;
0482     dma_addr_t phys_addr;
0483     struct pci_dev *pdev = test->pdev;
0484     struct device *dev = &pdev->dev;
0485     void *orig_addr;
0486     dma_addr_t orig_phys_addr;
0487     size_t offset;
0488     size_t alignment = test->alignment;
0489     int irq_type = test->irq_type;
0490     size_t size;
0491     u32 crc32;
0492     int err;
0493 
0494     err = copy_from_user(&param, (void __user *)arg, sizeof(param));
0495     if (err != 0) {
0496         dev_err(dev, "Failed to get transfer param\n");
0497         return false;
0498     }
0499 
0500     size = param.size;
0501     if (size > SIZE_MAX - alignment)
0502         goto err;
0503 
0504     use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
0505     if (use_dma)
0506         flags |= FLAG_USE_DMA;
0507 
0508     if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
0509         dev_err(dev, "Invalid IRQ type option\n");
0510         goto err;
0511     }
0512 
0513     orig_addr = kzalloc(size + alignment, GFP_KERNEL);
0514     if (!orig_addr) {
0515         dev_err(dev, "Failed to allocate address\n");
0516         ret = false;
0517         goto err;
0518     }
0519 
0520     get_random_bytes(orig_addr, size + alignment);
0521 
0522     orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
0523                     DMA_TO_DEVICE);
0524     if (dma_mapping_error(dev, orig_phys_addr)) {
0525         dev_err(dev, "failed to map source buffer address\n");
0526         ret = false;
0527         goto err_phys_addr;
0528     }
0529 
0530     if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
0531         phys_addr =  PTR_ALIGN(orig_phys_addr, alignment);
0532         offset = phys_addr - orig_phys_addr;
0533         addr = orig_addr + offset;
0534     } else {
0535         phys_addr = orig_phys_addr;
0536         addr = orig_addr;
0537     }
0538 
0539     crc32 = crc32_le(~0, addr, size);
0540     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
0541                  crc32);
0542 
0543     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
0544                  lower_32_bits(phys_addr));
0545     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
0546                  upper_32_bits(phys_addr));
0547 
0548     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
0549 
0550     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
0551     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
0552     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
0553     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
0554                  COMMAND_READ);
0555 
0556     wait_for_completion(&test->irq_raised);
0557 
0558     reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
0559     if (reg & STATUS_READ_SUCCESS)
0560         ret = true;
0561 
0562     dma_unmap_single(dev, orig_phys_addr, size + alignment,
0563              DMA_TO_DEVICE);
0564 
0565 err_phys_addr:
0566     kfree(orig_addr);
0567 
0568 err:
0569     return ret;
0570 }
0571 
0572 static bool pci_endpoint_test_read(struct pci_endpoint_test *test,
0573                    unsigned long arg)
0574 {
0575     struct pci_endpoint_test_xfer_param param;
0576     bool ret = false;
0577     u32 flags = 0;
0578     bool use_dma;
0579     size_t size;
0580     void *addr;
0581     dma_addr_t phys_addr;
0582     struct pci_dev *pdev = test->pdev;
0583     struct device *dev = &pdev->dev;
0584     void *orig_addr;
0585     dma_addr_t orig_phys_addr;
0586     size_t offset;
0587     size_t alignment = test->alignment;
0588     int irq_type = test->irq_type;
0589     u32 crc32;
0590     int err;
0591 
0592     err = copy_from_user(&param, (void __user *)arg, sizeof(param));
0593     if (err) {
0594         dev_err(dev, "Failed to get transfer param\n");
0595         return false;
0596     }
0597 
0598     size = param.size;
0599     if (size > SIZE_MAX - alignment)
0600         goto err;
0601 
0602     use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
0603     if (use_dma)
0604         flags |= FLAG_USE_DMA;
0605 
0606     if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
0607         dev_err(dev, "Invalid IRQ type option\n");
0608         goto err;
0609     }
0610 
0611     orig_addr = kzalloc(size + alignment, GFP_KERNEL);
0612     if (!orig_addr) {
0613         dev_err(dev, "Failed to allocate destination address\n");
0614         ret = false;
0615         goto err;
0616     }
0617 
0618     orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
0619                     DMA_FROM_DEVICE);
0620     if (dma_mapping_error(dev, orig_phys_addr)) {
0621         dev_err(dev, "failed to map source buffer address\n");
0622         ret = false;
0623         goto err_phys_addr;
0624     }
0625 
0626     if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
0627         phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
0628         offset = phys_addr - orig_phys_addr;
0629         addr = orig_addr + offset;
0630     } else {
0631         phys_addr = orig_phys_addr;
0632         addr = orig_addr;
0633     }
0634 
0635     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
0636                  lower_32_bits(phys_addr));
0637     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
0638                  upper_32_bits(phys_addr));
0639 
0640     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
0641 
0642     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
0643     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
0644     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
0645     pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
0646                  COMMAND_WRITE);
0647 
0648     wait_for_completion(&test->irq_raised);
0649 
0650     dma_unmap_single(dev, orig_phys_addr, size + alignment,
0651              DMA_FROM_DEVICE);
0652 
0653     crc32 = crc32_le(~0, addr, size);
0654     if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
0655         ret = true;
0656 
0657 err_phys_addr:
0658     kfree(orig_addr);
0659 err:
0660     return ret;
0661 }
0662 
0663 static bool pci_endpoint_test_clear_irq(struct pci_endpoint_test *test)
0664 {
0665     pci_endpoint_test_release_irq(test);
0666     pci_endpoint_test_free_irq_vectors(test);
0667     return true;
0668 }
0669 
0670 static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
0671                       int req_irq_type)
0672 {
0673     struct pci_dev *pdev = test->pdev;
0674     struct device *dev = &pdev->dev;
0675 
0676     if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
0677         dev_err(dev, "Invalid IRQ type option\n");
0678         return false;
0679     }
0680 
0681     if (test->irq_type == req_irq_type)
0682         return true;
0683 
0684     pci_endpoint_test_release_irq(test);
0685     pci_endpoint_test_free_irq_vectors(test);
0686 
0687     if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
0688         goto err;
0689 
0690     if (!pci_endpoint_test_request_irq(test))
0691         goto err;
0692 
0693     return true;
0694 
0695 err:
0696     pci_endpoint_test_free_irq_vectors(test);
0697     return false;
0698 }
0699 
0700 static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
0701                     unsigned long arg)
0702 {
0703     int ret = -EINVAL;
0704     enum pci_barno bar;
0705     struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
0706     struct pci_dev *pdev = test->pdev;
0707 
0708     mutex_lock(&test->mutex);
0709     switch (cmd) {
0710     case PCITEST_BAR:
0711         bar = arg;
0712         if (bar > BAR_5)
0713             goto ret;
0714         if (is_am654_pci_dev(pdev) && bar == BAR_0)
0715             goto ret;
0716         ret = pci_endpoint_test_bar(test, bar);
0717         break;
0718     case PCITEST_LEGACY_IRQ:
0719         ret = pci_endpoint_test_legacy_irq(test);
0720         break;
0721     case PCITEST_MSI:
0722     case PCITEST_MSIX:
0723         ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
0724         break;
0725     case PCITEST_WRITE:
0726         ret = pci_endpoint_test_write(test, arg);
0727         break;
0728     case PCITEST_READ:
0729         ret = pci_endpoint_test_read(test, arg);
0730         break;
0731     case PCITEST_COPY:
0732         ret = pci_endpoint_test_copy(test, arg);
0733         break;
0734     case PCITEST_SET_IRQTYPE:
0735         ret = pci_endpoint_test_set_irq(test, arg);
0736         break;
0737     case PCITEST_GET_IRQTYPE:
0738         ret = irq_type;
0739         break;
0740     case PCITEST_CLEAR_IRQ:
0741         ret = pci_endpoint_test_clear_irq(test);
0742         break;
0743     }
0744 
0745 ret:
0746     mutex_unlock(&test->mutex);
0747     return ret;
0748 }
0749 
0750 static const struct file_operations pci_endpoint_test_fops = {
0751     .owner = THIS_MODULE,
0752     .unlocked_ioctl = pci_endpoint_test_ioctl,
0753 };
0754 
0755 static int pci_endpoint_test_probe(struct pci_dev *pdev,
0756                    const struct pci_device_id *ent)
0757 {
0758     int err;
0759     int id;
0760     char name[24];
0761     enum pci_barno bar;
0762     void __iomem *base;
0763     struct device *dev = &pdev->dev;
0764     struct pci_endpoint_test *test;
0765     struct pci_endpoint_test_data *data;
0766     enum pci_barno test_reg_bar = BAR_0;
0767     struct miscdevice *misc_device;
0768 
0769     if (pci_is_bridge(pdev))
0770         return -ENODEV;
0771 
0772     test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
0773     if (!test)
0774         return -ENOMEM;
0775 
0776     test->test_reg_bar = 0;
0777     test->alignment = 0;
0778     test->pdev = pdev;
0779     test->irq_type = IRQ_TYPE_UNDEFINED;
0780 
0781     if (no_msi)
0782         irq_type = IRQ_TYPE_LEGACY;
0783 
0784     data = (struct pci_endpoint_test_data *)ent->driver_data;
0785     if (data) {
0786         test_reg_bar = data->test_reg_bar;
0787         test->test_reg_bar = test_reg_bar;
0788         test->alignment = data->alignment;
0789         irq_type = data->irq_type;
0790     }
0791 
0792     init_completion(&test->irq_raised);
0793     mutex_init(&test->mutex);
0794 
0795     if ((dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)) != 0) &&
0796         dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
0797         dev_err(dev, "Cannot set DMA mask\n");
0798         return -EINVAL;
0799     }
0800 
0801     err = pci_enable_device(pdev);
0802     if (err) {
0803         dev_err(dev, "Cannot enable PCI device\n");
0804         return err;
0805     }
0806 
0807     err = pci_request_regions(pdev, DRV_MODULE_NAME);
0808     if (err) {
0809         dev_err(dev, "Cannot obtain PCI resources\n");
0810         goto err_disable_pdev;
0811     }
0812 
0813     pci_set_master(pdev);
0814 
0815     if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type)) {
0816         err = -EINVAL;
0817         goto err_disable_irq;
0818     }
0819 
0820     for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
0821         if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
0822             base = pci_ioremap_bar(pdev, bar);
0823             if (!base) {
0824                 dev_err(dev, "Failed to read BAR%d\n", bar);
0825                 WARN_ON(bar == test_reg_bar);
0826             }
0827             test->bar[bar] = base;
0828         }
0829     }
0830 
0831     test->base = test->bar[test_reg_bar];
0832     if (!test->base) {
0833         err = -ENOMEM;
0834         dev_err(dev, "Cannot perform PCI test without BAR%d\n",
0835             test_reg_bar);
0836         goto err_iounmap;
0837     }
0838 
0839     pci_set_drvdata(pdev, test);
0840 
0841     id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
0842     if (id < 0) {
0843         err = id;
0844         dev_err(dev, "Unable to get id\n");
0845         goto err_iounmap;
0846     }
0847 
0848     snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
0849     test->name = kstrdup(name, GFP_KERNEL);
0850     if (!test->name) {
0851         err = -ENOMEM;
0852         goto err_ida_remove;
0853     }
0854 
0855     if (!pci_endpoint_test_request_irq(test)) {
0856         err = -EINVAL;
0857         goto err_kfree_test_name;
0858     }
0859 
0860     misc_device = &test->miscdev;
0861     misc_device->minor = MISC_DYNAMIC_MINOR;
0862     misc_device->name = kstrdup(name, GFP_KERNEL);
0863     if (!misc_device->name) {
0864         err = -ENOMEM;
0865         goto err_release_irq;
0866     }
0867     misc_device->parent = &pdev->dev;
0868     misc_device->fops = &pci_endpoint_test_fops;
0869 
0870     err = misc_register(misc_device);
0871     if (err) {
0872         dev_err(dev, "Failed to register device\n");
0873         goto err_kfree_name;
0874     }
0875 
0876     return 0;
0877 
0878 err_kfree_name:
0879     kfree(misc_device->name);
0880 
0881 err_release_irq:
0882     pci_endpoint_test_release_irq(test);
0883 
0884 err_kfree_test_name:
0885     kfree(test->name);
0886 
0887 err_ida_remove:
0888     ida_simple_remove(&pci_endpoint_test_ida, id);
0889 
0890 err_iounmap:
0891     for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
0892         if (test->bar[bar])
0893             pci_iounmap(pdev, test->bar[bar]);
0894     }
0895 
0896 err_disable_irq:
0897     pci_endpoint_test_free_irq_vectors(test);
0898     pci_release_regions(pdev);
0899 
0900 err_disable_pdev:
0901     pci_disable_device(pdev);
0902 
0903     return err;
0904 }
0905 
0906 static void pci_endpoint_test_remove(struct pci_dev *pdev)
0907 {
0908     int id;
0909     enum pci_barno bar;
0910     struct pci_endpoint_test *test = pci_get_drvdata(pdev);
0911     struct miscdevice *misc_device = &test->miscdev;
0912 
0913     if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
0914         return;
0915     if (id < 0)
0916         return;
0917 
0918     misc_deregister(&test->miscdev);
0919     kfree(misc_device->name);
0920     kfree(test->name);
0921     ida_simple_remove(&pci_endpoint_test_ida, id);
0922     for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
0923         if (test->bar[bar])
0924             pci_iounmap(pdev, test->bar[bar]);
0925     }
0926 
0927     pci_endpoint_test_release_irq(test);
0928     pci_endpoint_test_free_irq_vectors(test);
0929 
0930     pci_release_regions(pdev);
0931     pci_disable_device(pdev);
0932 }
0933 
0934 static const struct pci_endpoint_test_data default_data = {
0935     .test_reg_bar = BAR_0,
0936     .alignment = SZ_4K,
0937     .irq_type = IRQ_TYPE_MSI,
0938 };
0939 
0940 static const struct pci_endpoint_test_data am654_data = {
0941     .test_reg_bar = BAR_2,
0942     .alignment = SZ_64K,
0943     .irq_type = IRQ_TYPE_MSI,
0944 };
0945 
0946 static const struct pci_endpoint_test_data j721e_data = {
0947     .alignment = 256,
0948     .irq_type = IRQ_TYPE_MSI,
0949 };
0950 
0951 static const struct pci_device_id pci_endpoint_test_tbl[] = {
0952     { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
0953       .driver_data = (kernel_ulong_t)&default_data,
0954     },
0955     { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x),
0956       .driver_data = (kernel_ulong_t)&default_data,
0957     },
0958     { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0),
0959       .driver_data = (kernel_ulong_t)&default_data,
0960     },
0961     { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A),
0962       .driver_data = (kernel_ulong_t)&default_data,
0963     },
0964     { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
0965     { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
0966       .driver_data = (kernel_ulong_t)&am654_data
0967     },
0968     { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
0969     { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
0970     { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
0971     { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
0972     { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
0973       .driver_data = (kernel_ulong_t)&j721e_data,
0974     },
0975     { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J7200),
0976       .driver_data = (kernel_ulong_t)&j721e_data,
0977     },
0978     { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM64),
0979       .driver_data = (kernel_ulong_t)&j721e_data,
0980     },
0981     { }
0982 };
0983 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
0984 
0985 static struct pci_driver pci_endpoint_test_driver = {
0986     .name       = DRV_MODULE_NAME,
0987     .id_table   = pci_endpoint_test_tbl,
0988     .probe      = pci_endpoint_test_probe,
0989     .remove     = pci_endpoint_test_remove,
0990     .sriov_configure = pci_sriov_configure_simple,
0991 };
0992 module_pci_driver(pci_endpoint_test_driver);
0993 
0994 MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
0995 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
0996 MODULE_LICENSE("GPL v2");
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