misc/mei/pci-me.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2003-2020, Intel Corporation. All rights reserved.
0004  * Intel Management Engine Interface (Intel MEI) Linux driver
0005  */
0006
0007 #include <linux/module.h>
0008 #include <linux/kernel.h>
0009 #include <linux/device.h>
0010 #include <linux/errno.h>
0011 #include <linux/types.h>
0012 #include <linux/pci.h>
0013 #include <linux/dma-mapping.h>
0014 #include <linux/sched.h>
0015 #include <linux/interrupt.h>
0016
0017 #include <linux/pm_domain.h>
0018 #include <linux/pm_runtime.h>
0019
0020 #include <linux/mei.h>
0021
0022 #include "mei_dev.h"
0023 #include "client.h"
0024 #include "hw-me-regs.h"
0025 #include "hw-me.h"
0026
0027 /* mei_pci_tbl - PCI Device ID Table */
0028 static const struct pci_device_id mei_me_pci_tbl[] = {
0029     {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
0030     {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
0031     {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
0032     {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
0033     {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
0034     {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
0035     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
0036     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
0037     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
0038     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
0039     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
0040
0041     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
0042     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
0043     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
0044     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
0045     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
0046     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
0047     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
0048     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
0049     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
0050
0051     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
0052     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
0053     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
0054     {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
0055
0056     {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH6_CFG)},
0057     {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH6_CFG)},
0058     {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
0059     {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
0060     {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH7_CFG)},
0061     {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH7_CFG)},
0062     {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH7_CFG)},
0063     {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_4_CFG)},
0064     {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_4_CFG)},
0065     {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
0066     {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_4_CFG)},
0067     {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
0068     {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
0069
0070     {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
0071     {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
0072     {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_3, MEI_ME_PCH8_ITOUCH_CFG)},
0073     {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_4_CFG)},
0074     {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_4_CFG)},
0075     {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH12_SPS_4_CFG)},
0076
0077     {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
0078     {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
0079
0080     {MEI_PCI_DEVICE(MEI_DEV_ID_DNV_IE, MEI_ME_PCH8_CFG)},
0081
0082     {MEI_PCI_DEVICE(MEI_DEV_ID_GLK, MEI_ME_PCH8_CFG)},
0083
0084     {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
0085     {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
0086     {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_3, MEI_ME_PCH8_CFG)},
0087
0088     {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP, MEI_ME_PCH12_CFG)},
0089     {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
0090     {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H, MEI_ME_PCH12_SPS_CFG)},
0091     {MEI_PCI_DEVICE(MEI_DEV_ID_CNP_H_3, MEI_ME_PCH12_SPS_ITOUCH_CFG)},
0092
0093     {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP, MEI_ME_PCH12_CFG)},
0094     {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_LP_3, MEI_ME_PCH8_ITOUCH_CFG)},
0095     {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_V, MEI_ME_PCH12_CFG)},
0096     {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H, MEI_ME_PCH12_CFG)},
0097     {MEI_PCI_DEVICE(MEI_DEV_ID_CMP_H_3, MEI_ME_PCH8_ITOUCH_CFG)},
0098
0099     {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_LP, MEI_ME_PCH12_CFG)},
0100     {MEI_PCI_DEVICE(MEI_DEV_ID_ICP_N, MEI_ME_PCH12_CFG)},
0101
0102     {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_LP, MEI_ME_PCH15_CFG)},
0103     {MEI_PCI_DEVICE(MEI_DEV_ID_TGP_H, MEI_ME_PCH15_SPS_CFG)},
0104
0105     {MEI_PCI_DEVICE(MEI_DEV_ID_JSP_N, MEI_ME_PCH15_CFG)},
0106
0107     {MEI_PCI_DEVICE(MEI_DEV_ID_MCC, MEI_ME_PCH15_CFG)},
0108     {MEI_PCI_DEVICE(MEI_DEV_ID_MCC_4, MEI_ME_PCH8_CFG)},
0109
0110     {MEI_PCI_DEVICE(MEI_DEV_ID_CDF, MEI_ME_PCH8_CFG)},
0111
0112     {MEI_PCI_DEVICE(MEI_DEV_ID_EBG, MEI_ME_PCH15_SPS_CFG)},
0113
0114     {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_S, MEI_ME_PCH15_CFG)},
0115     {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_LP, MEI_ME_PCH15_CFG)},
0116     {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_P, MEI_ME_PCH15_CFG)},
0117     {MEI_PCI_DEVICE(MEI_DEV_ID_ADP_N, MEI_ME_PCH15_CFG)},
0118
0119     {MEI_PCI_DEVICE(MEI_DEV_ID_RPL_S, MEI_ME_PCH15_CFG)},
0120
0121     /* required last entry */
0122     {0, }
0123 };
0124
0125 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
0126
0127 #ifdef CONFIG_PM
0128 static inline void mei_me_set_pm_domain(struct mei_device *dev);
0129 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
0130 #else
0131 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
0132 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
0133 #endif /* CONFIG_PM */
0134
0135 static int mei_me_read_fws(const struct mei_device *dev, int where, u32 *val)
0136 {
0137     struct pci_dev *pdev = to_pci_dev(dev->dev);
0138
0139     return pci_read_config_dword(pdev, where, val);
0140 }
0141
0142 /**
0143  * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
0144  *
0145  * @pdev: PCI device structure
0146  * @cfg: per generation config
0147  *
0148  * Return: true if ME Interface is valid, false otherwise
0149  */
0150 static bool mei_me_quirk_probe(struct pci_dev *pdev,
0151                 const struct mei_cfg *cfg)
0152 {
0153     if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
0154         dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
0155         return false;
0156     }
0157
0158     return true;
0159 }
0160
0161 /**
0162  * mei_me_probe - Device Initialization Routine
0163  *
0164  * @pdev: PCI device structure
0165  * @ent: entry in kcs_pci_tbl
0166  *
0167  * Return: 0 on success, <0 on failure.
0168  */
0169 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
0170 {
0171     const struct mei_cfg *cfg;
0172     struct mei_device *dev;
0173     struct mei_me_hw *hw;
0174     unsigned int irqflags;
0175     int err;
0176
0177     cfg = mei_me_get_cfg(ent->driver_data);
0178     if (!cfg)
0179         return -ENODEV;
0180
0181     if (!mei_me_quirk_probe(pdev, cfg))
0182         return -ENODEV;
0183
0184     /* enable pci dev */
0185     err = pcim_enable_device(pdev);
0186     if (err) {
0187         dev_err(&pdev->dev, "failed to enable pci device.\n");
0188         goto end;
0189     }
0190     /* set PCI host mastering  */
0191     pci_set_master(pdev);
0192     /* pci request regions and mapping IO device memory for mei driver */
0193     err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
0194     if (err) {
0195         dev_err(&pdev->dev, "failed to get pci regions.\n");
0196         goto end;
0197     }
0198
0199     err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
0200     if (err) {
0201         dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
0202         goto end;
0203     }
0204
0205     /* allocates and initializes the mei dev structure */
0206     dev = mei_me_dev_init(&pdev->dev, cfg);
0207     if (!dev) {
0208         err = -ENOMEM;
0209         goto end;
0210     }
0211     hw = to_me_hw(dev);
0212     hw->mem_addr = pcim_iomap_table(pdev)[0];
0213     hw->read_fws = mei_me_read_fws;
0214
0215     pci_enable_msi(pdev);
0216
0217     hw->irq = pdev->irq;
0218
0219      /* request and enable interrupt */
0220     irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
0221
0222     err = request_threaded_irq(pdev->irq,
0223             mei_me_irq_quick_handler,
0224             mei_me_irq_thread_handler,
0225             irqflags, KBUILD_MODNAME, dev);
0226     if (err) {
0227         dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
0228                pdev->irq);
0229         goto end;
0230     }
0231
0232     if (mei_start(dev)) {
0233         dev_err(&pdev->dev, "init hw failure.\n");
0234         err = -ENODEV;
0235         goto release_irq;
0236     }
0237
0238     pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
0239     pm_runtime_use_autosuspend(&pdev->dev);
0240
0241     err = mei_register(dev, &pdev->dev);
0242     if (err)
0243         goto stop;
0244
0245     pci_set_drvdata(pdev, dev);
0246
0247     /*
0248      * MEI requires to resume from runtime suspend mode
0249      * in order to perform link reset flow upon system suspend.
0250      */
0251     dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
0252
0253     /*
0254      * ME maps runtime suspend/resume to D0i states,
0255      * hence we need to go around native PCI runtime service which
0256      * eventually brings the device into D3cold/hot state,
0257      * but the mei device cannot wake up from D3 unlike from D0i3.
0258      * To get around the PCI device native runtime pm,
0259      * ME uses runtime pm domain handlers which take precedence
0260      * over the driver's pm handlers.
0261      */
0262     mei_me_set_pm_domain(dev);
0263
0264     if (mei_pg_is_enabled(dev)) {
0265         pm_runtime_put_noidle(&pdev->dev);
0266         if (hw->d0i3_supported)
0267             pm_runtime_allow(&pdev->dev);
0268     }
0269
0270     dev_dbg(&pdev->dev, "initialization successful.\n");
0271
0272     return 0;
0273
0274 stop:
0275     mei_stop(dev);
0276 release_irq:
0277     mei_cancel_work(dev);
0278     mei_disable_interrupts(dev);
0279     free_irq(pdev->irq, dev);
0280 end:
0281     dev_err(&pdev->dev, "initialization failed.\n");
0282     return err;
0283 }
0284
0285 /**
0286  * mei_me_shutdown - Device Removal Routine
0287  *
0288  * @pdev: PCI device structure
0289  *
0290  * mei_me_shutdown is called from the reboot notifier
0291  * it's a simplified version of remove so we go down
0292  * faster.
0293  */
0294 static void mei_me_shutdown(struct pci_dev *pdev)
0295 {
0296     struct mei_device *dev;
0297
0298     dev = pci_get_drvdata(pdev);
0299     if (!dev)
0300         return;
0301
0302     dev_dbg(&pdev->dev, "shutdown\n");
0303     mei_stop(dev);
0304
0305     mei_me_unset_pm_domain(dev);
0306
0307     mei_disable_interrupts(dev);
0308     free_irq(pdev->irq, dev);
0309 }
0310
0311 /**
0312  * mei_me_remove - Device Removal Routine
0313  *
0314  * @pdev: PCI device structure
0315  *
0316  * mei_me_remove is called by the PCI subsystem to alert the driver
0317  * that it should release a PCI device.
0318  */
0319 static void mei_me_remove(struct pci_dev *pdev)
0320 {
0321     struct mei_device *dev;
0322
0323     dev = pci_get_drvdata(pdev);
0324     if (!dev)
0325         return;
0326
0327     if (mei_pg_is_enabled(dev))
0328         pm_runtime_get_noresume(&pdev->dev);
0329
0330     dev_dbg(&pdev->dev, "stop\n");
0331     mei_stop(dev);
0332
0333     mei_me_unset_pm_domain(dev);
0334
0335     mei_disable_interrupts(dev);
0336
0337     free_irq(pdev->irq, dev);
0338
0339     mei_deregister(dev);
0340 }
0341
0342 #ifdef CONFIG_PM_SLEEP
0343 static int mei_me_pci_suspend(struct device *device)
0344 {
0345     struct pci_dev *pdev = to_pci_dev(device);
0346     struct mei_device *dev = pci_get_drvdata(pdev);
0347
0348     if (!dev)
0349         return -ENODEV;
0350
0351     dev_dbg(&pdev->dev, "suspend\n");
0352
0353     mei_stop(dev);
0354
0355     mei_disable_interrupts(dev);
0356
0357     free_irq(pdev->irq, dev);
0358     pci_disable_msi(pdev);
0359
0360     return 0;
0361 }
0362
0363 static int mei_me_pci_resume(struct device *device)
0364 {
0365     struct pci_dev *pdev = to_pci_dev(device);
0366     struct mei_device *dev;
0367     unsigned int irqflags;
0368     int err;
0369
0370     dev = pci_get_drvdata(pdev);
0371     if (!dev)
0372         return -ENODEV;
0373
0374     pci_enable_msi(pdev);
0375
0376     irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
0377
0378     /* request and enable interrupt */
0379     err = request_threaded_irq(pdev->irq,
0380             mei_me_irq_quick_handler,
0381             mei_me_irq_thread_handler,
0382             irqflags, KBUILD_MODNAME, dev);
0383
0384     if (err) {
0385         dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
0386                 pdev->irq);
0387         return err;
0388     }
0389
0390     err = mei_restart(dev);
0391     if (err)
0392         return err;
0393
0394     /* Start timer if stopped in suspend */
0395     schedule_delayed_work(&dev->timer_work, HZ);
0396
0397     return 0;
0398 }
0399 #endif /* CONFIG_PM_SLEEP */
0400
0401 #ifdef CONFIG_PM
0402 static int mei_me_pm_runtime_idle(struct device *device)
0403 {
0404     struct mei_device *dev;
0405
0406     dev_dbg(device, "rpm: me: runtime_idle\n");
0407
0408     dev = dev_get_drvdata(device);
0409     if (!dev)
0410         return -ENODEV;
0411     if (mei_write_is_idle(dev))
0412         pm_runtime_autosuspend(device);
0413
0414     return -EBUSY;
0415 }
0416
0417 static int mei_me_pm_runtime_suspend(struct device *device)
0418 {
0419     struct mei_device *dev;
0420     int ret;
0421
0422     dev_dbg(device, "rpm: me: runtime suspend\n");
0423
0424     dev = dev_get_drvdata(device);
0425     if (!dev)
0426         return -ENODEV;
0427
0428     mutex_lock(&dev->device_lock);
0429
0430     if (mei_write_is_idle(dev))
0431         ret = mei_me_pg_enter_sync(dev);
0432     else
0433         ret = -EAGAIN;
0434
0435     mutex_unlock(&dev->device_lock);
0436
0437     dev_dbg(device, "rpm: me: runtime suspend ret=%d\n", ret);
0438
0439     if (ret && ret != -EAGAIN)
0440         schedule_work(&dev->reset_work);
0441
0442     return ret;
0443 }
0444
0445 static int mei_me_pm_runtime_resume(struct device *device)
0446 {
0447     struct mei_device *dev;
0448     int ret;
0449
0450     dev_dbg(device, "rpm: me: runtime resume\n");
0451
0452     dev = dev_get_drvdata(device);
0453     if (!dev)
0454         return -ENODEV;
0455
0456     mutex_lock(&dev->device_lock);
0457
0458     ret = mei_me_pg_exit_sync(dev);
0459
0460     mutex_unlock(&dev->device_lock);
0461
0462     dev_dbg(device, "rpm: me: runtime resume ret = %d\n", ret);
0463
0464     if (ret)
0465         schedule_work(&dev->reset_work);
0466
0467     return ret;
0468 }
0469
0470 /**
0471  * mei_me_set_pm_domain - fill and set pm domain structure for device
0472  *
0473  * @dev: mei_device
0474  */
0475 static inline void mei_me_set_pm_domain(struct mei_device *dev)
0476 {
0477     struct pci_dev *pdev  = to_pci_dev(dev->dev);
0478
0479     if (pdev->dev.bus && pdev->dev.bus->pm) {
0480         dev->pg_domain.ops = *pdev->dev.bus->pm;
0481
0482         dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
0483         dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
0484         dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
0485
0486         dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
0487     }
0488 }
0489
0490 /**
0491  * mei_me_unset_pm_domain - clean pm domain structure for device
0492  *
0493  * @dev: mei_device
0494  */
0495 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
0496 {
0497     /* stop using pm callbacks if any */
0498     dev_pm_domain_set(dev->dev, NULL);
0499 }
0500
0501 static const struct dev_pm_ops mei_me_pm_ops = {
0502     SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
0503                 mei_me_pci_resume)
0504     SET_RUNTIME_PM_OPS(
0505         mei_me_pm_runtime_suspend,
0506         mei_me_pm_runtime_resume,
0507         mei_me_pm_runtime_idle)
0508 };
0509
0510 #define MEI_ME_PM_OPS   (&mei_me_pm_ops)
0511 #else
0512 #define MEI_ME_PM_OPS   NULL
0513 #endif /* CONFIG_PM */
0514 /*
0515  *  PCI driver structure
0516  */
0517 static struct pci_driver mei_me_driver = {
0518     .name = KBUILD_MODNAME,
0519     .id_table = mei_me_pci_tbl,
0520     .probe = mei_me_probe,
0521     .remove = mei_me_remove,
0522     .shutdown = mei_me_shutdown,
0523     .driver.pm = MEI_ME_PM_OPS,
0524     .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
0525 };
0526
0527 module_pci_driver(mei_me_driver);
0528
0529 MODULE_AUTHOR("Intel Corporation");
0530 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
0531 MODULE_LICENSE("GPL v2");