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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2013-2020, Intel Corporation. All rights reserved.
0004  * Intel Management Engine Interface (Intel MEI) Linux driver
0005  */
0006 
0007 #include <linux/pci.h>
0008 #include <linux/jiffies.h>
0009 #include <linux/ktime.h>
0010 #include <linux/delay.h>
0011 #include <linux/kthread.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/pm_runtime.h>
0014 
0015 #include <linux/mei.h>
0016 
0017 #include "mei_dev.h"
0018 #include "hw-txe.h"
0019 #include "client.h"
0020 #include "hbm.h"
0021 
0022 #include "mei-trace.h"
0023 
0024 #define TXE_HBUF_DEPTH (PAYLOAD_SIZE / MEI_SLOT_SIZE)
0025 
0026 /**
0027  * mei_txe_reg_read - Reads 32bit data from the txe device
0028  *
0029  * @base_addr: registers base address
0030  * @offset: register offset
0031  *
0032  * Return: register value
0033  */
0034 static inline u32 mei_txe_reg_read(void __iomem *base_addr,
0035                     unsigned long offset)
0036 {
0037     return ioread32(base_addr + offset);
0038 }
0039 
0040 /**
0041  * mei_txe_reg_write - Writes 32bit data to the txe device
0042  *
0043  * @base_addr: registers base address
0044  * @offset: register offset
0045  * @value: the value to write
0046  */
0047 static inline void mei_txe_reg_write(void __iomem *base_addr,
0048                 unsigned long offset, u32 value)
0049 {
0050     iowrite32(value, base_addr + offset);
0051 }
0052 
0053 /**
0054  * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR
0055  *
0056  * @hw: the txe hardware structure
0057  * @offset: register offset
0058  *
0059  * Doesn't check for aliveness while Reads 32bit data from the SeC BAR
0060  *
0061  * Return: register value
0062  */
0063 static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw,
0064                 unsigned long offset)
0065 {
0066     return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset);
0067 }
0068 
0069 /**
0070  * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR
0071  *
0072  * @hw: the txe hardware structure
0073  * @offset: register offset
0074  *
0075  * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set
0076  *
0077  * Return: register value
0078  */
0079 static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw,
0080                 unsigned long offset)
0081 {
0082     WARN(!hw->aliveness, "sec read: aliveness not asserted\n");
0083     return mei_txe_sec_reg_read_silent(hw, offset);
0084 }
0085 /**
0086  * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR
0087  *   doesn't check for aliveness
0088  *
0089  * @hw: the txe hardware structure
0090  * @offset: register offset
0091  * @value: value to write
0092  *
0093  * Doesn't check for aliveness while writes 32bit data from to the SeC BAR
0094  */
0095 static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw,
0096                 unsigned long offset, u32 value)
0097 {
0098     mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value);
0099 }
0100 
0101 /**
0102  * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR
0103  *
0104  * @hw: the txe hardware structure
0105  * @offset: register offset
0106  * @value: value to write
0107  *
0108  * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set
0109  */
0110 static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw,
0111                 unsigned long offset, u32 value)
0112 {
0113     WARN(!hw->aliveness, "sec write: aliveness not asserted\n");
0114     mei_txe_sec_reg_write_silent(hw, offset, value);
0115 }
0116 /**
0117  * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR
0118  *
0119  * @hw: the txe hardware structure
0120  * @offset: offset from which to read the data
0121  *
0122  * Return: the byte read.
0123  */
0124 static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw,
0125                 unsigned long offset)
0126 {
0127     return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset);
0128 }
0129 
0130 /**
0131  * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR
0132  *
0133  * @hw: the txe hardware structure
0134  * @offset: offset from which to write the data
0135  * @value: the byte to write
0136  */
0137 static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw,
0138                 unsigned long offset, u32 value)
0139 {
0140     mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value);
0141 }
0142 
0143 /**
0144  * mei_txe_aliveness_set - request for aliveness change
0145  *
0146  * @dev: the device structure
0147  * @req: requested aliveness value
0148  *
0149  * Request for aliveness change and returns true if the change is
0150  *   really needed and false if aliveness is already
0151  *   in the requested state
0152  *
0153  * Locking: called under "dev->device_lock" lock
0154  *
0155  * Return: true if request was send
0156  */
0157 static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req)
0158 {
0159 
0160     struct mei_txe_hw *hw = to_txe_hw(dev);
0161     bool do_req = hw->aliveness != req;
0162 
0163     dev_dbg(dev->dev, "Aliveness current=%d request=%d\n",
0164                 hw->aliveness, req);
0165     if (do_req) {
0166         dev->pg_event = MEI_PG_EVENT_WAIT;
0167         mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req);
0168     }
0169     return do_req;
0170 }
0171 
0172 
0173 /**
0174  * mei_txe_aliveness_req_get - get aliveness requested register value
0175  *
0176  * @dev: the device structure
0177  *
0178  * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from
0179  * from HICR_HOST_ALIVENESS_REQ register value
0180  *
0181  * Return: SICR_HOST_ALIVENESS_REQ_REQUESTED bit value
0182  */
0183 static u32 mei_txe_aliveness_req_get(struct mei_device *dev)
0184 {
0185     struct mei_txe_hw *hw = to_txe_hw(dev);
0186     u32 reg;
0187 
0188     reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG);
0189     return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED;
0190 }
0191 
0192 /**
0193  * mei_txe_aliveness_get - get aliveness response register value
0194  *
0195  * @dev: the device structure
0196  *
0197  * Return: HICR_HOST_ALIVENESS_RESP_ACK bit from HICR_HOST_ALIVENESS_RESP
0198  *         register
0199  */
0200 static u32 mei_txe_aliveness_get(struct mei_device *dev)
0201 {
0202     struct mei_txe_hw *hw = to_txe_hw(dev);
0203     u32 reg;
0204 
0205     reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG);
0206     return reg & HICR_HOST_ALIVENESS_RESP_ACK;
0207 }
0208 
0209 /**
0210  * mei_txe_aliveness_poll - waits for aliveness to settle
0211  *
0212  * @dev: the device structure
0213  * @expected: expected aliveness value
0214  *
0215  * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
0216  *
0217  * Return: 0 if the expected value was received, -ETIME otherwise
0218  */
0219 static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected)
0220 {
0221     struct mei_txe_hw *hw = to_txe_hw(dev);
0222     ktime_t stop, start;
0223 
0224     start = ktime_get();
0225     stop = ktime_add(start, ms_to_ktime(SEC_ALIVENESS_WAIT_TIMEOUT));
0226     do {
0227         hw->aliveness = mei_txe_aliveness_get(dev);
0228         if (hw->aliveness == expected) {
0229             dev->pg_event = MEI_PG_EVENT_IDLE;
0230             dev_dbg(dev->dev, "aliveness settled after %lld usecs\n",
0231                 ktime_to_us(ktime_sub(ktime_get(), start)));
0232             return 0;
0233         }
0234         usleep_range(20, 50);
0235     } while (ktime_before(ktime_get(), stop));
0236 
0237     dev->pg_event = MEI_PG_EVENT_IDLE;
0238     dev_err(dev->dev, "aliveness timed out\n");
0239     return -ETIME;
0240 }
0241 
0242 /**
0243  * mei_txe_aliveness_wait - waits for aliveness to settle
0244  *
0245  * @dev: the device structure
0246  * @expected: expected aliveness value
0247  *
0248  * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
0249  *
0250  * Return: 0 on success and < 0 otherwise
0251  */
0252 static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected)
0253 {
0254     struct mei_txe_hw *hw = to_txe_hw(dev);
0255     const unsigned long timeout =
0256             msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT);
0257     long err;
0258     int ret;
0259 
0260     hw->aliveness = mei_txe_aliveness_get(dev);
0261     if (hw->aliveness == expected)
0262         return 0;
0263 
0264     mutex_unlock(&dev->device_lock);
0265     err = wait_event_timeout(hw->wait_aliveness_resp,
0266             dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
0267     mutex_lock(&dev->device_lock);
0268 
0269     hw->aliveness = mei_txe_aliveness_get(dev);
0270     ret = hw->aliveness == expected ? 0 : -ETIME;
0271 
0272     if (ret)
0273         dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n",
0274             err, hw->aliveness, dev->pg_event);
0275     else
0276         dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n",
0277             jiffies_to_msecs(timeout - err),
0278             hw->aliveness, dev->pg_event);
0279 
0280     dev->pg_event = MEI_PG_EVENT_IDLE;
0281     return ret;
0282 }
0283 
0284 /**
0285  * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete
0286  *
0287  * @dev: the device structure
0288  * @req: requested aliveness value
0289  *
0290  * Return: 0 on success and < 0 otherwise
0291  */
0292 int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req)
0293 {
0294     if (mei_txe_aliveness_set(dev, req))
0295         return mei_txe_aliveness_wait(dev, req);
0296     return 0;
0297 }
0298 
0299 /**
0300  * mei_txe_pg_in_transition - is device now in pg transition
0301  *
0302  * @dev: the device structure
0303  *
0304  * Return: true if in pg transition, false otherwise
0305  */
0306 static bool mei_txe_pg_in_transition(struct mei_device *dev)
0307 {
0308     return dev->pg_event == MEI_PG_EVENT_WAIT;
0309 }
0310 
0311 /**
0312  * mei_txe_pg_is_enabled - detect if PG is supported by HW
0313  *
0314  * @dev: the device structure
0315  *
0316  * Return: true is pg supported, false otherwise
0317  */
0318 static bool mei_txe_pg_is_enabled(struct mei_device *dev)
0319 {
0320     return true;
0321 }
0322 
0323 /**
0324  * mei_txe_pg_state  - translate aliveness register value
0325  *   to the mei power gating state
0326  *
0327  * @dev: the device structure
0328  *
0329  * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
0330  */
0331 static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev)
0332 {
0333     struct mei_txe_hw *hw = to_txe_hw(dev);
0334 
0335     return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON;
0336 }
0337 
0338 /**
0339  * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt
0340  *
0341  * @dev: the device structure
0342  */
0343 static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev)
0344 {
0345     struct mei_txe_hw *hw = to_txe_hw(dev);
0346     u32 hintmsk;
0347     /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */
0348     hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG);
0349     hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY;
0350     mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk);
0351 }
0352 
0353 /**
0354  * mei_txe_input_doorbell_set - sets bit 0 in
0355  *    SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL.
0356  *
0357  * @hw: the txe hardware structure
0358  */
0359 static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw)
0360 {
0361     /* Clear the interrupt cause */
0362     clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause);
0363     mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1);
0364 }
0365 
0366 /**
0367  * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1
0368  *
0369  * @hw: the txe hardware structure
0370  */
0371 static void mei_txe_output_ready_set(struct mei_txe_hw *hw)
0372 {
0373     mei_txe_br_reg_write(hw,
0374             SICR_SEC_IPC_OUTPUT_STATUS_REG,
0375             SEC_IPC_OUTPUT_STATUS_RDY);
0376 }
0377 
0378 /**
0379  * mei_txe_is_input_ready - check if TXE is ready for receiving data
0380  *
0381  * @dev: the device structure
0382  *
0383  * Return: true if INPUT STATUS READY bit is set
0384  */
0385 static bool mei_txe_is_input_ready(struct mei_device *dev)
0386 {
0387     struct mei_txe_hw *hw = to_txe_hw(dev);
0388     u32 status;
0389 
0390     status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG);
0391     return !!(SEC_IPC_INPUT_STATUS_RDY & status);
0392 }
0393 
0394 /**
0395  * mei_txe_intr_clear - clear all interrupts
0396  *
0397  * @dev: the device structure
0398  */
0399 static inline void mei_txe_intr_clear(struct mei_device *dev)
0400 {
0401     struct mei_txe_hw *hw = to_txe_hw(dev);
0402 
0403     mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG,
0404         SEC_IPC_HOST_INT_STATUS_PENDING);
0405     mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK);
0406     mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK);
0407 }
0408 
0409 /**
0410  * mei_txe_intr_disable - disable all interrupts
0411  *
0412  * @dev: the device structure
0413  */
0414 static void mei_txe_intr_disable(struct mei_device *dev)
0415 {
0416     struct mei_txe_hw *hw = to_txe_hw(dev);
0417 
0418     mei_txe_br_reg_write(hw, HHIER_REG, 0);
0419     mei_txe_br_reg_write(hw, HIER_REG, 0);
0420 }
0421 /**
0422  * mei_txe_intr_enable - enable all interrupts
0423  *
0424  * @dev: the device structure
0425  */
0426 static void mei_txe_intr_enable(struct mei_device *dev)
0427 {
0428     struct mei_txe_hw *hw = to_txe_hw(dev);
0429 
0430     mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK);
0431     mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK);
0432 }
0433 
0434 /**
0435  * mei_txe_synchronize_irq - wait for pending IRQ handlers
0436  *
0437  * @dev: the device structure
0438  */
0439 static void mei_txe_synchronize_irq(struct mei_device *dev)
0440 {
0441     struct pci_dev *pdev = to_pci_dev(dev->dev);
0442 
0443     synchronize_irq(pdev->irq);
0444 }
0445 
0446 /**
0447  * mei_txe_pending_interrupts - check if there are pending interrupts
0448  *  only Aliveness, Input ready, and output doorbell are of relevance
0449  *
0450  * @dev: the device structure
0451  *
0452  * Checks if there are pending interrupts
0453  * only Aliveness, Readiness, Input ready, and Output doorbell are relevant
0454  *
0455  * Return: true if there are pending interrupts
0456  */
0457 static bool mei_txe_pending_interrupts(struct mei_device *dev)
0458 {
0459 
0460     struct mei_txe_hw *hw = to_txe_hw(dev);
0461     bool ret = (hw->intr_cause & (TXE_INTR_READINESS |
0462                       TXE_INTR_ALIVENESS |
0463                       TXE_INTR_IN_READY  |
0464                       TXE_INTR_OUT_DB));
0465 
0466     if (ret) {
0467         dev_dbg(dev->dev,
0468             "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n",
0469             !!(hw->intr_cause & TXE_INTR_IN_READY),
0470             !!(hw->intr_cause & TXE_INTR_READINESS),
0471             !!(hw->intr_cause & TXE_INTR_ALIVENESS),
0472             !!(hw->intr_cause & TXE_INTR_OUT_DB));
0473     }
0474     return ret;
0475 }
0476 
0477 /**
0478  * mei_txe_input_payload_write - write a dword to the host buffer
0479  *  at offset idx
0480  *
0481  * @dev: the device structure
0482  * @idx: index in the host buffer
0483  * @value: value
0484  */
0485 static void mei_txe_input_payload_write(struct mei_device *dev,
0486             unsigned long idx, u32 value)
0487 {
0488     struct mei_txe_hw *hw = to_txe_hw(dev);
0489 
0490     mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG +
0491             (idx * sizeof(u32)), value);
0492 }
0493 
0494 /**
0495  * mei_txe_out_data_read - read dword from the device buffer
0496  *  at offset idx
0497  *
0498  * @dev: the device structure
0499  * @idx: index in the device buffer
0500  *
0501  * Return: register value at index
0502  */
0503 static u32 mei_txe_out_data_read(const struct mei_device *dev,
0504                     unsigned long idx)
0505 {
0506     struct mei_txe_hw *hw = to_txe_hw(dev);
0507 
0508     return mei_txe_br_reg_read(hw,
0509         BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32)));
0510 }
0511 
0512 /* Readiness */
0513 
0514 /**
0515  * mei_txe_readiness_set_host_rdy - set host readiness bit
0516  *
0517  * @dev: the device structure
0518  */
0519 static void mei_txe_readiness_set_host_rdy(struct mei_device *dev)
0520 {
0521     struct mei_txe_hw *hw = to_txe_hw(dev);
0522 
0523     mei_txe_br_reg_write(hw,
0524         SICR_HOST_IPC_READINESS_REQ_REG,
0525         SICR_HOST_IPC_READINESS_HOST_RDY);
0526 }
0527 
0528 /**
0529  * mei_txe_readiness_clear - clear host readiness bit
0530  *
0531  * @dev: the device structure
0532  */
0533 static void mei_txe_readiness_clear(struct mei_device *dev)
0534 {
0535     struct mei_txe_hw *hw = to_txe_hw(dev);
0536 
0537     mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG,
0538                 SICR_HOST_IPC_READINESS_RDY_CLR);
0539 }
0540 /**
0541  * mei_txe_readiness_get - Reads and returns
0542  *  the HICR_SEC_IPC_READINESS register value
0543  *
0544  * @dev: the device structure
0545  *
0546  * Return: the HICR_SEC_IPC_READINESS register value
0547  */
0548 static u32 mei_txe_readiness_get(struct mei_device *dev)
0549 {
0550     struct mei_txe_hw *hw = to_txe_hw(dev);
0551 
0552     return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
0553 }
0554 
0555 
0556 /**
0557  * mei_txe_readiness_is_sec_rdy - check readiness
0558  *  for HICR_SEC_IPC_READINESS_SEC_RDY
0559  *
0560  * @readiness: cached readiness state
0561  *
0562  * Return: true if readiness bit is set
0563  */
0564 static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness)
0565 {
0566     return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY);
0567 }
0568 
0569 /**
0570  * mei_txe_hw_is_ready - check if the hw is ready
0571  *
0572  * @dev: the device structure
0573  *
0574  * Return: true if sec is ready
0575  */
0576 static bool mei_txe_hw_is_ready(struct mei_device *dev)
0577 {
0578     u32 readiness =  mei_txe_readiness_get(dev);
0579 
0580     return mei_txe_readiness_is_sec_rdy(readiness);
0581 }
0582 
0583 /**
0584  * mei_txe_host_is_ready - check if the host is ready
0585  *
0586  * @dev: the device structure
0587  *
0588  * Return: true if host is ready
0589  */
0590 static inline bool mei_txe_host_is_ready(struct mei_device *dev)
0591 {
0592     struct mei_txe_hw *hw = to_txe_hw(dev);
0593     u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
0594 
0595     return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY);
0596 }
0597 
0598 /**
0599  * mei_txe_readiness_wait - wait till readiness settles
0600  *
0601  * @dev: the device structure
0602  *
0603  * Return: 0 on success and -ETIME on timeout
0604  */
0605 static int mei_txe_readiness_wait(struct mei_device *dev)
0606 {
0607     if (mei_txe_hw_is_ready(dev))
0608         return 0;
0609 
0610     mutex_unlock(&dev->device_lock);
0611     wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready,
0612             msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT));
0613     mutex_lock(&dev->device_lock);
0614     if (!dev->recvd_hw_ready) {
0615         dev_err(dev->dev, "wait for readiness failed\n");
0616         return -ETIME;
0617     }
0618 
0619     dev->recvd_hw_ready = false;
0620     return 0;
0621 }
0622 
0623 static const struct mei_fw_status mei_txe_fw_sts = {
0624     .count = 2,
0625     .status[0] = PCI_CFG_TXE_FW_STS0,
0626     .status[1] = PCI_CFG_TXE_FW_STS1
0627 };
0628 
0629 /**
0630  * mei_txe_fw_status - read fw status register from pci config space
0631  *
0632  * @dev: mei device
0633  * @fw_status: fw status register values
0634  *
0635  * Return: 0 on success, error otherwise
0636  */
0637 static int mei_txe_fw_status(struct mei_device *dev,
0638                  struct mei_fw_status *fw_status)
0639 {
0640     const struct mei_fw_status *fw_src = &mei_txe_fw_sts;
0641     struct pci_dev *pdev = to_pci_dev(dev->dev);
0642     int ret;
0643     int i;
0644 
0645     if (!fw_status)
0646         return -EINVAL;
0647 
0648     fw_status->count = fw_src->count;
0649     for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
0650         ret = pci_read_config_dword(pdev, fw_src->status[i],
0651                         &fw_status->status[i]);
0652         trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X",
0653                        fw_src->status[i],
0654                        fw_status->status[i]);
0655         if (ret)
0656             return ret;
0657     }
0658 
0659     return 0;
0660 }
0661 
0662 /**
0663  * mei_txe_hw_config - configure hardware at the start of the devices
0664  *
0665  * @dev: the device structure
0666  *
0667  * Configure hardware at the start of the device should be done only
0668  *   once at the device probe time
0669  *
0670  * Return: always 0
0671  */
0672 static int mei_txe_hw_config(struct mei_device *dev)
0673 {
0674 
0675     struct mei_txe_hw *hw = to_txe_hw(dev);
0676 
0677     hw->aliveness = mei_txe_aliveness_get(dev);
0678     hw->readiness = mei_txe_readiness_get(dev);
0679 
0680     dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n",
0681         hw->aliveness, hw->readiness);
0682 
0683     return 0;
0684 }
0685 
0686 /**
0687  * mei_txe_write - writes a message to device.
0688  *
0689  * @dev: the device structure
0690  * @hdr: header of message
0691  * @hdr_len: header length in bytes - must multiplication of a slot (4bytes)
0692  * @data: payload
0693  * @data_len: paylead length in bytes
0694  *
0695  * Return: 0 if success, < 0 - otherwise.
0696  */
0697 static int mei_txe_write(struct mei_device *dev,
0698              const void *hdr, size_t hdr_len,
0699              const void *data, size_t data_len)
0700 {
0701     struct mei_txe_hw *hw = to_txe_hw(dev);
0702     unsigned long rem;
0703     const u32 *reg_buf;
0704     u32 slots = TXE_HBUF_DEPTH;
0705     u32 dw_cnt;
0706     unsigned long i, j;
0707 
0708     if (WARN_ON(!hdr || !data || hdr_len & 0x3))
0709         return -EINVAL;
0710 
0711     dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr));
0712 
0713     dw_cnt = mei_data2slots(hdr_len + data_len);
0714     if (dw_cnt > slots)
0715         return -EMSGSIZE;
0716 
0717     if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n"))
0718         return -EAGAIN;
0719 
0720     /* Enable Input Ready Interrupt. */
0721     mei_txe_input_ready_interrupt_enable(dev);
0722 
0723     if (!mei_txe_is_input_ready(dev)) {
0724         char fw_sts_str[MEI_FW_STATUS_STR_SZ];
0725 
0726         mei_fw_status_str(dev, fw_sts_str, MEI_FW_STATUS_STR_SZ);
0727         dev_err(dev->dev, "Input is not ready %s\n", fw_sts_str);
0728         return -EAGAIN;
0729     }
0730 
0731     reg_buf = hdr;
0732     for (i = 0; i < hdr_len / MEI_SLOT_SIZE; i++)
0733         mei_txe_input_payload_write(dev, i, reg_buf[i]);
0734 
0735     reg_buf = data;
0736     for (j = 0; j < data_len / MEI_SLOT_SIZE; j++)
0737         mei_txe_input_payload_write(dev, i + j, reg_buf[j]);
0738 
0739     rem = data_len & 0x3;
0740     if (rem > 0) {
0741         u32 reg = 0;
0742 
0743         memcpy(&reg, (const u8 *)data + data_len - rem, rem);
0744         mei_txe_input_payload_write(dev, i + j, reg);
0745     }
0746 
0747     /* after each write the whole buffer is consumed */
0748     hw->slots = 0;
0749 
0750     /* Set Input-Doorbell */
0751     mei_txe_input_doorbell_set(hw);
0752 
0753     return 0;
0754 }
0755 
0756 /**
0757  * mei_txe_hbuf_depth - mimics the me hbuf circular buffer
0758  *
0759  * @dev: the device structure
0760  *
0761  * Return: the TXE_HBUF_DEPTH
0762  */
0763 static u32 mei_txe_hbuf_depth(const struct mei_device *dev)
0764 {
0765     return TXE_HBUF_DEPTH;
0766 }
0767 
0768 /**
0769  * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer
0770  *
0771  * @dev: the device structure
0772  *
0773  * Return: always TXE_HBUF_DEPTH
0774  */
0775 static int mei_txe_hbuf_empty_slots(struct mei_device *dev)
0776 {
0777     struct mei_txe_hw *hw = to_txe_hw(dev);
0778 
0779     return hw->slots;
0780 }
0781 
0782 /**
0783  * mei_txe_count_full_read_slots - mimics the me device circular buffer
0784  *
0785  * @dev: the device structure
0786  *
0787  * Return: always buffer size in dwords count
0788  */
0789 static int mei_txe_count_full_read_slots(struct mei_device *dev)
0790 {
0791     /* read buffers has static size */
0792     return TXE_HBUF_DEPTH;
0793 }
0794 
0795 /**
0796  * mei_txe_read_hdr - read message header which is always in 4 first bytes
0797  *
0798  * @dev: the device structure
0799  *
0800  * Return: mei message header
0801  */
0802 
0803 static u32 mei_txe_read_hdr(const struct mei_device *dev)
0804 {
0805     return mei_txe_out_data_read(dev, 0);
0806 }
0807 /**
0808  * mei_txe_read - reads a message from the txe device.
0809  *
0810  * @dev: the device structure
0811  * @buf: message buffer will be written
0812  * @len: message size will be read
0813  *
0814  * Return: -EINVAL on error wrong argument and 0 on success
0815  */
0816 static int mei_txe_read(struct mei_device *dev,
0817         unsigned char *buf, unsigned long len)
0818 {
0819 
0820     struct mei_txe_hw *hw = to_txe_hw(dev);
0821     u32 *reg_buf, reg;
0822     u32 rem;
0823     u32 i;
0824 
0825     if (WARN_ON(!buf || !len))
0826         return -EINVAL;
0827 
0828     reg_buf = (u32 *)buf;
0829     rem = len & 0x3;
0830 
0831     dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n",
0832         len, mei_txe_out_data_read(dev, 0));
0833 
0834     for (i = 0; i < len / MEI_SLOT_SIZE; i++) {
0835         /* skip header: index starts from 1 */
0836         reg = mei_txe_out_data_read(dev, i + 1);
0837         dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg);
0838         *reg_buf++ = reg;
0839     }
0840 
0841     if (rem) {
0842         reg = mei_txe_out_data_read(dev, i + 1);
0843         memcpy(reg_buf, &reg, rem);
0844     }
0845 
0846     mei_txe_output_ready_set(hw);
0847     return 0;
0848 }
0849 
0850 /**
0851  * mei_txe_hw_reset - resets host and fw.
0852  *
0853  * @dev: the device structure
0854  * @intr_enable: if interrupt should be enabled after reset.
0855  *
0856  * Return: 0 on success and < 0 in case of error
0857  */
0858 static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable)
0859 {
0860     struct mei_txe_hw *hw = to_txe_hw(dev);
0861 
0862     u32 aliveness_req;
0863     /*
0864      * read input doorbell to ensure consistency between  Bridge and SeC
0865      * return value might be garbage return
0866      */
0867     (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG);
0868 
0869     aliveness_req = mei_txe_aliveness_req_get(dev);
0870     hw->aliveness = mei_txe_aliveness_get(dev);
0871 
0872     /* Disable interrupts in this stage we will poll */
0873     mei_txe_intr_disable(dev);
0874 
0875     /*
0876      * If Aliveness Request and Aliveness Response are not equal then
0877      * wait for them to be equal
0878      * Since we might have interrupts disabled - poll for it
0879      */
0880     if (aliveness_req != hw->aliveness)
0881         if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) {
0882             dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n");
0883             return -EIO;
0884         }
0885 
0886     /*
0887      * If Aliveness Request and Aliveness Response are set then clear them
0888      */
0889     if (aliveness_req) {
0890         mei_txe_aliveness_set(dev, 0);
0891         if (mei_txe_aliveness_poll(dev, 0) < 0) {
0892             dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
0893             return -EIO;
0894         }
0895     }
0896 
0897     /*
0898      * Set readiness RDY_CLR bit
0899      */
0900     mei_txe_readiness_clear(dev);
0901 
0902     return 0;
0903 }
0904 
0905 /**
0906  * mei_txe_hw_start - start the hardware after reset
0907  *
0908  * @dev: the device structure
0909  *
0910  * Return: 0 on success an error code otherwise
0911  */
0912 static int mei_txe_hw_start(struct mei_device *dev)
0913 {
0914     struct mei_txe_hw *hw = to_txe_hw(dev);
0915     int ret;
0916 
0917     u32 hisr;
0918 
0919     /* bring back interrupts */
0920     mei_txe_intr_enable(dev);
0921 
0922     ret = mei_txe_readiness_wait(dev);
0923     if (ret < 0) {
0924         dev_err(dev->dev, "waiting for readiness failed\n");
0925         return ret;
0926     }
0927 
0928     /*
0929      * If HISR.INT2_STS interrupt status bit is set then clear it.
0930      */
0931     hisr = mei_txe_br_reg_read(hw, HISR_REG);
0932     if (hisr & HISR_INT_2_STS)
0933         mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS);
0934 
0935     /* Clear the interrupt cause of OutputDoorbell */
0936     clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause);
0937 
0938     ret = mei_txe_aliveness_set_sync(dev, 1);
0939     if (ret < 0) {
0940         dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
0941         return ret;
0942     }
0943 
0944     pm_runtime_set_active(dev->dev);
0945 
0946     /* enable input ready interrupts:
0947      * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK
0948      */
0949     mei_txe_input_ready_interrupt_enable(dev);
0950 
0951 
0952     /*  Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */
0953     mei_txe_output_ready_set(hw);
0954 
0955     /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY
0956      */
0957     mei_txe_readiness_set_host_rdy(dev);
0958 
0959     return 0;
0960 }
0961 
0962 /**
0963  * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into
0964  *  single bit mask and acknowledge the interrupts
0965  *
0966  * @dev: the device structure
0967  * @do_ack: acknowledge interrupts
0968  *
0969  * Return: true if found interrupts to process.
0970  */
0971 static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack)
0972 {
0973     struct mei_txe_hw *hw = to_txe_hw(dev);
0974     u32 hisr;
0975     u32 hhisr;
0976     u32 ipc_isr;
0977     u32 aliveness;
0978     bool generated;
0979 
0980     /* read interrupt registers */
0981     hhisr = mei_txe_br_reg_read(hw, HHISR_REG);
0982     generated = (hhisr & IPC_HHIER_MSK);
0983     if (!generated)
0984         goto out;
0985 
0986     hisr = mei_txe_br_reg_read(hw, HISR_REG);
0987 
0988     aliveness = mei_txe_aliveness_get(dev);
0989     if (hhisr & IPC_HHIER_SEC && aliveness) {
0990         ipc_isr = mei_txe_sec_reg_read_silent(hw,
0991                 SEC_IPC_HOST_INT_STATUS_REG);
0992     } else {
0993         ipc_isr = 0;
0994         hhisr &= ~IPC_HHIER_SEC;
0995     }
0996 
0997     if (do_ack) {
0998         /* Save the interrupt causes */
0999         hw->intr_cause |= hisr & HISR_INT_STS_MSK;
1000         if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY)
1001             hw->intr_cause |= TXE_INTR_IN_READY;
1002 
1003 
1004         mei_txe_intr_disable(dev);
1005         /* Clear the interrupts in hierarchy:
1006          * IPC and Bridge, than the High Level */
1007         mei_txe_sec_reg_write_silent(hw,
1008             SEC_IPC_HOST_INT_STATUS_REG, ipc_isr);
1009         mei_txe_br_reg_write(hw, HISR_REG, hisr);
1010         mei_txe_br_reg_write(hw, HHISR_REG, hhisr);
1011     }
1012 
1013 out:
1014     return generated;
1015 }
1016 
1017 /**
1018  * mei_txe_irq_quick_handler - The ISR of the MEI device
1019  *
1020  * @irq: The irq number
1021  * @dev_id: pointer to the device structure
1022  *
1023  * Return: IRQ_WAKE_THREAD if interrupt is designed for the device
1024  *         IRQ_NONE otherwise
1025  */
1026 irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id)
1027 {
1028     struct mei_device *dev = dev_id;
1029 
1030     if (mei_txe_check_and_ack_intrs(dev, true))
1031         return IRQ_WAKE_THREAD;
1032     return IRQ_NONE;
1033 }
1034 
1035 
1036 /**
1037  * mei_txe_irq_thread_handler - txe interrupt thread
1038  *
1039  * @irq: The irq number
1040  * @dev_id: pointer to the device structure
1041  *
1042  * Return: IRQ_HANDLED
1043  */
1044 irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id)
1045 {
1046     struct mei_device *dev = (struct mei_device *) dev_id;
1047     struct mei_txe_hw *hw = to_txe_hw(dev);
1048     struct list_head cmpl_list;
1049     s32 slots;
1050     int rets = 0;
1051 
1052     dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n",
1053         mei_txe_br_reg_read(hw, HHISR_REG),
1054         mei_txe_br_reg_read(hw, HISR_REG),
1055         mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG));
1056 
1057 
1058     /* initialize our complete list */
1059     mutex_lock(&dev->device_lock);
1060     INIT_LIST_HEAD(&cmpl_list);
1061 
1062     if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))
1063         mei_txe_check_and_ack_intrs(dev, true);
1064 
1065     /* show irq events */
1066     mei_txe_pending_interrupts(dev);
1067 
1068     hw->aliveness = mei_txe_aliveness_get(dev);
1069     hw->readiness = mei_txe_readiness_get(dev);
1070 
1071     /* Readiness:
1072      * Detection of TXE driver going through reset
1073      * or TXE driver resetting the HECI interface.
1074      */
1075     if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) {
1076         dev_dbg(dev->dev, "Readiness Interrupt was received...\n");
1077 
1078         /* Check if SeC is going through reset */
1079         if (mei_txe_readiness_is_sec_rdy(hw->readiness)) {
1080             dev_dbg(dev->dev, "we need to start the dev.\n");
1081             dev->recvd_hw_ready = true;
1082         } else {
1083             dev->recvd_hw_ready = false;
1084             if (dev->dev_state != MEI_DEV_RESETTING) {
1085 
1086                 dev_warn(dev->dev, "FW not ready: resetting.\n");
1087                 schedule_work(&dev->reset_work);
1088                 goto end;
1089 
1090             }
1091         }
1092         wake_up(&dev->wait_hw_ready);
1093     }
1094 
1095     /************************************************************/
1096     /* Check interrupt cause:
1097      * Aliveness: Detection of SeC acknowledge of host request that
1098      * it remain alive or host cancellation of that request.
1099      */
1100 
1101     if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) {
1102         /* Clear the interrupt cause */
1103         dev_dbg(dev->dev,
1104             "Aliveness Interrupt: Status: %d\n", hw->aliveness);
1105         dev->pg_event = MEI_PG_EVENT_RECEIVED;
1106         if (waitqueue_active(&hw->wait_aliveness_resp))
1107             wake_up(&hw->wait_aliveness_resp);
1108     }
1109 
1110 
1111     /* Output Doorbell:
1112      * Detection of SeC having sent output to host
1113      */
1114     slots = mei_count_full_read_slots(dev);
1115     if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) {
1116         /* Read from TXE */
1117         rets = mei_irq_read_handler(dev, &cmpl_list, &slots);
1118         if (rets &&
1119             (dev->dev_state != MEI_DEV_RESETTING &&
1120              dev->dev_state != MEI_DEV_POWER_DOWN)) {
1121             dev_err(dev->dev,
1122                 "mei_irq_read_handler ret = %d.\n", rets);
1123 
1124             schedule_work(&dev->reset_work);
1125             goto end;
1126         }
1127     }
1128     /* Input Ready: Detection if host can write to SeC */
1129     if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) {
1130         dev->hbuf_is_ready = true;
1131         hw->slots = TXE_HBUF_DEPTH;
1132     }
1133 
1134     if (hw->aliveness && dev->hbuf_is_ready) {
1135         /* get the real register value */
1136         dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1137         rets = mei_irq_write_handler(dev, &cmpl_list);
1138         if (rets && rets != -EMSGSIZE)
1139             dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n",
1140                 rets);
1141         dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1142     }
1143 
1144     mei_irq_compl_handler(dev, &cmpl_list);
1145 
1146 end:
1147     dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1148 
1149     mutex_unlock(&dev->device_lock);
1150 
1151     mei_enable_interrupts(dev);
1152     return IRQ_HANDLED;
1153 }
1154 
1155 static const struct mei_hw_ops mei_txe_hw_ops = {
1156 
1157     .host_is_ready = mei_txe_host_is_ready,
1158 
1159     .fw_status = mei_txe_fw_status,
1160     .pg_state = mei_txe_pg_state,
1161 
1162     .hw_is_ready = mei_txe_hw_is_ready,
1163     .hw_reset = mei_txe_hw_reset,
1164     .hw_config = mei_txe_hw_config,
1165     .hw_start = mei_txe_hw_start,
1166 
1167     .pg_in_transition = mei_txe_pg_in_transition,
1168     .pg_is_enabled = mei_txe_pg_is_enabled,
1169 
1170     .intr_clear = mei_txe_intr_clear,
1171     .intr_enable = mei_txe_intr_enable,
1172     .intr_disable = mei_txe_intr_disable,
1173     .synchronize_irq = mei_txe_synchronize_irq,
1174 
1175     .hbuf_free_slots = mei_txe_hbuf_empty_slots,
1176     .hbuf_is_ready = mei_txe_is_input_ready,
1177     .hbuf_depth = mei_txe_hbuf_depth,
1178 
1179     .write = mei_txe_write,
1180 
1181     .rdbuf_full_slots = mei_txe_count_full_read_slots,
1182     .read_hdr = mei_txe_read_hdr,
1183 
1184     .read = mei_txe_read,
1185 
1186 };
1187 
1188 /**
1189  * mei_txe_dev_init - allocates and initializes txe hardware specific structure
1190  *
1191  * @pdev: pci device
1192  *
1193  * Return: struct mei_device * on success or NULL
1194  */
1195 struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
1196 {
1197     struct mei_device *dev;
1198     struct mei_txe_hw *hw;
1199 
1200     dev = devm_kzalloc(&pdev->dev, sizeof(*dev) + sizeof(*hw), GFP_KERNEL);
1201     if (!dev)
1202         return NULL;
1203 
1204     mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops);
1205 
1206     hw = to_txe_hw(dev);
1207 
1208     init_waitqueue_head(&hw->wait_aliveness_resp);
1209 
1210     return dev;
1211 }
1212 
1213 /**
1214  * mei_txe_setup_satt2 - SATT2 configuration for DMA support.
1215  *
1216  * @dev:   the device structure
1217  * @addr:  physical address start of the range
1218  * @range: physical range size
1219  *
1220  * Return: 0 on success an error code otherwise
1221  */
1222 int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range)
1223 {
1224     struct mei_txe_hw *hw = to_txe_hw(dev);
1225 
1226     u32 lo32 = lower_32_bits(addr);
1227     u32 hi32 = upper_32_bits(addr);
1228     u32 ctrl;
1229 
1230     /* SATT is limited to 36 Bits */
1231     if (hi32 & ~0xF)
1232         return -EINVAL;
1233 
1234     /* SATT has to be 16Byte aligned */
1235     if (lo32 & 0xF)
1236         return -EINVAL;
1237 
1238     /* SATT range has to be 4Bytes aligned */
1239     if (range & 0x4)
1240         return -EINVAL;
1241 
1242     /* SATT is limited to 32 MB range*/
1243     if (range > SATT_RANGE_MAX)
1244         return -EINVAL;
1245 
1246     ctrl = SATT2_CTRL_VALID_MSK;
1247     ctrl |= hi32  << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT;
1248 
1249     mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range);
1250     mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32);
1251     mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl);
1252     dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n",
1253         range, lo32, ctrl);
1254 
1255     return 0;
1256 }
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