misc/mei/hw-txe-regs.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
0002 /*
0003  * Copyright (c) 2013-2014, Intel Corporation. All rights reserved.
0004  * Intel Management Engine Interface (Intel MEI) Linux driver
0005  */
0006 #ifndef _MEI_HW_TXE_REGS_H_
0007 #define _MEI_HW_TXE_REGS_H_
0008
0009 #include "hw.h"
0010
0011 #define SEC_ALIVENESS_TIMER_TIMEOUT        (5 * MSEC_PER_SEC)
0012 #define SEC_ALIVENESS_WAIT_TIMEOUT         (1 * MSEC_PER_SEC)
0013 #define SEC_RESET_WAIT_TIMEOUT             (1 * MSEC_PER_SEC)
0014 #define SEC_READY_WAIT_TIMEOUT             (5 * MSEC_PER_SEC)
0015 #define START_MESSAGE_RESPONSE_WAIT_TIMEOUT (5 * MSEC_PER_SEC)
0016 #define RESET_CANCEL_WAIT_TIMEOUT          (1 * MSEC_PER_SEC)
0017
0018 enum {
0019     SEC_BAR,
0020     BRIDGE_BAR,
0021
0022     NUM_OF_MEM_BARS
0023 };
0024
0025 /* SeC FW Status Register
0026  *
0027  * FW uses this register in order to report its status to host.
0028  * This register resides in PCI-E config space.
0029  */
0030 #define PCI_CFG_TXE_FW_STS0   0x40
0031 #  define PCI_CFG_TXE_FW_STS0_WRK_ST_MSK    0x0000000F
0032 #  define PCI_CFG_TXE_FW_STS0_OP_ST_MSK     0x000001C0
0033 #  define PCI_CFG_TXE_FW_STS0_FW_INIT_CMPLT 0x00000200
0034 #  define PCI_CFG_TXE_FW_STS0_ERR_CODE_MSK  0x0000F000
0035 #  define PCI_CFG_TXE_FW_STS0_OP_MODE_MSK   0x000F0000
0036 #  define PCI_CFG_TXE_FW_STS0_RST_CNT_MSK   0x00F00000
0037 #define PCI_CFG_TXE_FW_STS1   0x48
0038
0039 #define IPC_BASE_ADDR   0x80400 /* SeC IPC Base Address */
0040
0041 /* IPC Input Doorbell Register */
0042 #define SEC_IPC_INPUT_DOORBELL_REG       (0x0000 + IPC_BASE_ADDR)
0043
0044 /* IPC Input Status Register
0045  * This register indicates whether or not processing of
0046  * the most recent command has been completed by the SEC
0047  * New commands and payloads should not be written by the Host
0048  * until this indicates that the previous command has been processed.
0049  */
0050 #define SEC_IPC_INPUT_STATUS_REG         (0x0008 + IPC_BASE_ADDR)
0051 #  define SEC_IPC_INPUT_STATUS_RDY    BIT(0)
0052
0053 /* IPC Host Interrupt Status Register */
0054 #define SEC_IPC_HOST_INT_STATUS_REG      (0x0010 + IPC_BASE_ADDR)
0055 #define   SEC_IPC_HOST_INT_STATUS_OUT_DB             BIT(0)
0056 #define   SEC_IPC_HOST_INT_STATUS_IN_RDY             BIT(1)
0057 #define   SEC_IPC_HOST_INT_STATUS_HDCP_M0_RCVD       BIT(5)
0058 #define   SEC_IPC_HOST_INT_STATUS_ILL_MEM_ACCESS     BIT(17)
0059 #define   SEC_IPC_HOST_INT_STATUS_AES_HKEY_ERR       BIT(18)
0060 #define   SEC_IPC_HOST_INT_STATUS_DES_HKEY_ERR       BIT(19)
0061 #define   SEC_IPC_HOST_INT_STATUS_TMRMTB_OVERFLOW    BIT(21)
0062
0063 /* Convenient mask for pending interrupts */
0064 #define   SEC_IPC_HOST_INT_STATUS_PENDING \
0065         (SEC_IPC_HOST_INT_STATUS_OUT_DB| \
0066         SEC_IPC_HOST_INT_STATUS_IN_RDY)
0067
0068 /* IPC Host Interrupt Mask Register */
0069 #define SEC_IPC_HOST_INT_MASK_REG        (0x0014 + IPC_BASE_ADDR)
0070
0071 #  define SEC_IPC_HOST_INT_MASK_OUT_DB  BIT(0) /* Output Doorbell Int Mask */
0072 #  define SEC_IPC_HOST_INT_MASK_IN_RDY  BIT(1) /* Input Ready Int Mask */
0073
0074 /* IPC Input Payload RAM */
0075 #define SEC_IPC_INPUT_PAYLOAD_REG        (0x0100 + IPC_BASE_ADDR)
0076 /* IPC Shared Payload RAM */
0077 #define IPC_SHARED_PAYLOAD_REG           (0x0200 + IPC_BASE_ADDR)
0078
0079 /* SeC Address Translation Table Entry 2 - Ctrl
0080  *
0081  * This register resides also in SeC's PCI-E Memory space.
0082  */
0083 #define SATT2_CTRL_REG                   0x1040
0084 #  define SATT2_CTRL_VALID_MSK            BIT(0)
0085 #  define SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT 8
0086 #  define SATT2_CTRL_BRIDGE_HOST_EN_MSK   BIT(12)
0087
0088 /* SATT Table Entry 2 SAP Base Address Register */
0089 #define SATT2_SAP_BA_REG                 0x1044
0090 /* SATT Table Entry 2 SAP Size Register. */
0091 #define SATT2_SAP_SIZE_REG               0x1048
0092  /* SATT Table Entry 2 SAP Bridge Address - LSB Register */
0093 #define SATT2_BRG_BA_LSB_REG             0x104C
0094
0095 /* Host High-level Interrupt Status Register */
0096 #define HHISR_REG                        0x2020
0097 /* Host High-level Interrupt Enable Register
0098  *
0099  * Resides in PCI memory space. This is the top hierarchy for
0100  * interrupts from SeC to host, aggregating both interrupts that
0101  * arrive through HICR registers as well as interrupts
0102  * that arrive via IPC.
0103  */
0104 #define HHIER_REG                        0x2024
0105 #define   IPC_HHIER_SEC BIT(0)
0106 #define   IPC_HHIER_BRIDGE  BIT(1)
0107 #define   IPC_HHIER_MSK (IPC_HHIER_SEC | IPC_HHIER_BRIDGE)
0108
0109 /* Host High-level Interrupt Mask Register.
0110  *
0111  * Resides in PCI memory space.
0112  * This is the top hierarchy for masking interrupts from SeC to host.
0113  */
0114 #define HHIMR_REG                        0x2028
0115 #define   IPC_HHIMR_SEC       BIT(0)
0116 #define   IPC_HHIMR_BRIDGE    BIT(1)
0117
0118 /* Host High-level IRQ Status Register */
0119 #define HHIRQSR_REG                      0x202C
0120
0121 /* Host Interrupt Cause Register 0 - SeC IPC Readiness
0122  *
0123  * This register is both an ICR to Host from PCI Memory Space
0124  * and it is also exposed in the SeC memory space.
0125  * This register is used by SeC's IPC driver in order
0126  * to synchronize with host about IPC interface state.
0127  */
0128 #define HICR_SEC_IPC_READINESS_REG       0x2040
0129 #define   HICR_SEC_IPC_READINESS_HOST_RDY  BIT(0)
0130 #define   HICR_SEC_IPC_READINESS_SEC_RDY   BIT(1)
0131 #define   HICR_SEC_IPC_READINESS_SYS_RDY     \
0132       (HICR_SEC_IPC_READINESS_HOST_RDY | \
0133        HICR_SEC_IPC_READINESS_SEC_RDY)
0134 #define   HICR_SEC_IPC_READINESS_RDY_CLR   BIT(2)
0135
0136 /* Host Interrupt Cause Register 1 - Aliveness Response */
0137 /* This register is both an ICR to Host from PCI Memory Space
0138  * and it is also exposed in the SeC memory space.
0139  * The register may be used by SeC to ACK a host request for aliveness.
0140  */
0141 #define HICR_HOST_ALIVENESS_RESP_REG     0x2044
0142 #define   HICR_HOST_ALIVENESS_RESP_ACK    BIT(0)
0143
0144 /* Host Interrupt Cause Register 2 - SeC IPC Output Doorbell */
0145 #define HICR_SEC_IPC_OUTPUT_DOORBELL_REG 0x2048
0146
0147 /* Host Interrupt Status Register.
0148  *
0149  * Resides in PCI memory space.
0150  * This is the main register involved in generating interrupts
0151  * from SeC to host via HICRs.
0152  * The interrupt generation rules are as follows:
0153  * An interrupt will be generated whenever for any i,
0154  * there is a transition from a state where at least one of
0155  * the following conditions did not hold, to a state where
0156  * ALL the following conditions hold:
0157  * A) HISR.INT[i]_STS == 1.
0158  * B) HIER.INT[i]_EN == 1.
0159  */
0160 #define HISR_REG                         0x2060
0161 #define   HISR_INT_0_STS      BIT(0)
0162 #define   HISR_INT_1_STS      BIT(1)
0163 #define   HISR_INT_2_STS      BIT(2)
0164 #define   HISR_INT_3_STS      BIT(3)
0165 #define   HISR_INT_4_STS      BIT(4)
0166 #define   HISR_INT_5_STS      BIT(5)
0167 #define   HISR_INT_6_STS      BIT(6)
0168 #define   HISR_INT_7_STS      BIT(7)
0169 #define   HISR_INT_STS_MSK \
0170     (HISR_INT_0_STS | HISR_INT_1_STS | HISR_INT_2_STS)
0171
0172 /* Host Interrupt Enable Register. Resides in PCI memory space. */
0173 #define HIER_REG                         0x2064
0174 #define   HIER_INT_0_EN      BIT(0)
0175 #define   HIER_INT_1_EN      BIT(1)
0176 #define   HIER_INT_2_EN      BIT(2)
0177 #define   HIER_INT_3_EN      BIT(3)
0178 #define   HIER_INT_4_EN      BIT(4)
0179 #define   HIER_INT_5_EN      BIT(5)
0180 #define   HIER_INT_6_EN      BIT(6)
0181 #define   HIER_INT_7_EN      BIT(7)
0182
0183 #define   HIER_INT_EN_MSK \
0184      (HIER_INT_0_EN | HIER_INT_1_EN | HIER_INT_2_EN)
0185
0186
0187 /* SEC Memory Space IPC output payload.
0188  *
0189  * This register is part of the output payload which SEC provides to host.
0190  */
0191 #define BRIDGE_IPC_OUTPUT_PAYLOAD_REG    0x20C0
0192
0193 /* SeC Interrupt Cause Register - Host Aliveness Request
0194  * This register is both an ICR to SeC and it is also exposed
0195  * in the host-visible PCI memory space.
0196  * The register is used by host to request SeC aliveness.
0197  */
0198 #define SICR_HOST_ALIVENESS_REQ_REG      0x214C
0199 #define   SICR_HOST_ALIVENESS_REQ_REQUESTED    BIT(0)
0200
0201
0202 /* SeC Interrupt Cause Register - Host IPC Readiness
0203  *
0204  * This register is both an ICR to SeC and it is also exposed
0205  * in the host-visible PCI memory space.
0206  * This register is used by the host's SeC driver uses in order
0207  * to synchronize with SeC about IPC interface state.
0208  */
0209 #define SICR_HOST_IPC_READINESS_REQ_REG  0x2150
0210
0211
0212 #define SICR_HOST_IPC_READINESS_HOST_RDY  BIT(0)
0213 #define SICR_HOST_IPC_READINESS_SEC_RDY   BIT(1)
0214 #define SICR_HOST_IPC_READINESS_SYS_RDY     \
0215     (SICR_HOST_IPC_READINESS_HOST_RDY | \
0216      SICR_HOST_IPC_READINESS_SEC_RDY)
0217 #define SICR_HOST_IPC_READINESS_RDY_CLR   BIT(2)
0218
0219 /* SeC Interrupt Cause Register - SeC IPC Output Status
0220  *
0221  * This register indicates whether or not processing of the most recent
0222  * command has been completed by the Host.
0223  * New commands and payloads should not be written by SeC until this
0224  * register indicates that the previous command has been processed.
0225  */
0226 #define SICR_SEC_IPC_OUTPUT_STATUS_REG   0x2154
0227 #  define SEC_IPC_OUTPUT_STATUS_RDY BIT(0)
0228
0229
0230
0231 /*  MEI IPC Message payload size 64 bytes */
0232 #define PAYLOAD_SIZE        64
0233
0234 /* MAX size for SATT range 32MB */
0235 #define SATT_RANGE_MAX     (32 << 20)
0236
0237
0238 #endif /* _MEI_HW_TXE_REGS_H_ */
0239