misc/mei/hw-me.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2012-2020, Intel Corporation. All rights reserved.
0004  * Intel Management Engine Interface (Intel MEI) Linux driver
0005  */
0006
0007 #ifndef _MEI_INTERFACE_H_
0008 #define _MEI_INTERFACE_H_
0009
0010 #include <linux/irqreturn.h>
0011 #include <linux/pci.h>
0012 #include <linux/mei.h>
0013
0014 #include "mei_dev.h"
0015 #include "client.h"
0016
0017 /*
0018  * mei_cfg - mei device configuration
0019  *
0020  * @fw_status: FW status
0021  * @quirk_probe: device exclusion quirk
0022  * @kind: MEI head kind
0023  * @dma_size: device DMA buffers size
0024  * @fw_ver_supported: is fw version retrievable from FW
0025  * @hw_trc_supported: does the hw support trc register
0026  */
0027 struct mei_cfg {
0028     const struct mei_fw_status fw_status;
0029     bool (*quirk_probe)(const struct pci_dev *pdev);
0030     const char *kind;
0031     size_t dma_size[DMA_DSCR_NUM];
0032     u32 fw_ver_supported:1;
0033     u32 hw_trc_supported:1;
0034 };
0035
0036
0037 #define MEI_PCI_DEVICE(dev, cfg) \
0038     .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
0039     .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
0040     .driver_data = (kernel_ulong_t)(cfg),
0041
0042 #define MEI_ME_RPM_TIMEOUT    500 /* ms */
0043
0044 /**
0045  * struct mei_me_hw - me hw specific data
0046  *
0047  * @cfg: per device generation config and ops
0048  * @mem_addr: io memory address
0049  * @irq: irq number
0050  * @pg_state: power gating state
0051  * @d0i3_supported: di03 support
0052  * @hbuf_depth: depth of hardware host/write buffer in slots
0053  * @read_fws: read FW status register handler
0054  */
0055 struct mei_me_hw {
0056     const struct mei_cfg *cfg;
0057     void __iomem *mem_addr;
0058     int irq;
0059     enum mei_pg_state pg_state;
0060     bool d0i3_supported;
0061     u8 hbuf_depth;
0062     int (*read_fws)(const struct mei_device *dev, int where, u32 *val);
0063 };
0064
0065 #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
0066
0067 /**
0068  * enum mei_cfg_idx - indices to platform specific configurations.
0069  *
0070  * Note: has to be synchronized with mei_cfg_list[]
0071  *
0072  * @MEI_ME_UNDEF_CFG:      Lower sentinel.
0073  * @MEI_ME_ICH_CFG:        I/O Controller Hub legacy devices.
0074  * @MEI_ME_ICH10_CFG:      I/O Controller Hub platforms Gen10
0075  * @MEI_ME_PCH6_CFG:       Platform Controller Hub platforms (Gen6).
0076  * @MEI_ME_PCH7_CFG:       Platform Controller Hub platforms (Gen7).
0077  * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations
0078  *                         with quirk for Node Manager exclusion.
0079  * @MEI_ME_PCH8_CFG:       Platform Controller Hub Gen8 and newer
0080  *                         client platforms.
0081  * @MEI_ME_PCH8_ITOUCH_CFG:Platform Controller Hub Gen8 and newer
0082  *                         client platforms (iTouch).
0083  * @MEI_ME_PCH8_SPS_4_CFG: Platform Controller Hub Gen8 and newer
0084  *                         servers platforms with quirk for
0085  *                         SPS firmware exclusion.
0086  * @MEI_ME_PCH12_CFG:      Platform Controller Hub Gen12 and newer
0087  * @MEI_ME_PCH12_SPS_4_CFG:Platform Controller Hub Gen12 up to 4.0
0088  *                         servers platforms with quirk for
0089  *                         SPS firmware exclusion.
0090  * @MEI_ME_PCH12_SPS_CFG:  Platform Controller Hub Gen12 5.0 and newer
0091  *                         servers platforms with quirk for
0092  *                         SPS firmware exclusion.
0093  * @MEI_ME_PCH15_CFG:      Platform Controller Hub Gen15 and newer
0094  * @MEI_ME_PCH15_SPS_CFG:  Platform Controller Hub Gen15 and newer
0095  *                         servers platforms with quirk for
0096  *                         SPS firmware exclusion.
0097  * @MEI_ME_NUM_CFG:        Upper Sentinel.
0098  */
0099 enum mei_cfg_idx {
0100     MEI_ME_UNDEF_CFG,
0101     MEI_ME_ICH_CFG,
0102     MEI_ME_ICH10_CFG,
0103     MEI_ME_PCH6_CFG,
0104     MEI_ME_PCH7_CFG,
0105     MEI_ME_PCH_CPT_PBG_CFG,
0106     MEI_ME_PCH8_CFG,
0107     MEI_ME_PCH8_ITOUCH_CFG,
0108     MEI_ME_PCH8_SPS_4_CFG,
0109     MEI_ME_PCH12_CFG,
0110     MEI_ME_PCH12_SPS_4_CFG,
0111     MEI_ME_PCH12_SPS_CFG,
0112     MEI_ME_PCH12_SPS_ITOUCH_CFG,
0113     MEI_ME_PCH15_CFG,
0114     MEI_ME_PCH15_SPS_CFG,
0115     MEI_ME_GSC_CFG,
0116     MEI_ME_GSCFI_CFG,
0117     MEI_ME_NUM_CFG,
0118 };
0119
0120 const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx);
0121
0122 struct mei_device *mei_me_dev_init(struct device *parent,
0123                    const struct mei_cfg *cfg);
0124
0125 int mei_me_pg_enter_sync(struct mei_device *dev);
0126 int mei_me_pg_exit_sync(struct mei_device *dev);
0127
0128 irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id);
0129 irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id);
0130
0131 #endif /* _MEI_INTERFACE_H_ */