drivers/misc/lattice-ecp3-config.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2012 Stefan Roese <sr@denx.de>
0004  */
0005
0006 #include <linux/device.h>
0007 #include <linux/firmware.h>
0008 #include <linux/module.h>
0009 #include <linux/errno.h>
0010 #include <linux/kernel.h>
0011 #include <linux/spi/spi.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/delay.h>
0014 #include <asm/unaligned.h>
0015
0016 #define FIRMWARE_NAME   "lattice-ecp3.bit"
0017
0018 /*
0019  * The JTAG ID's of the supported FPGA's. The ID is 32bit wide
0020  * reversed as noted in the manual.
0021  */
0022 #define ID_ECP3_17  0xc2088080
0023 #define ID_ECP3_35  0xc2048080
0024
0025 /* FPGA commands */
0026 #define FPGA_CMD_READ_ID    0x07    /* plus 24 bits */
0027 #define FPGA_CMD_READ_STATUS    0x09    /* plus 24 bits */
0028 #define FPGA_CMD_CLEAR      0x70
0029 #define FPGA_CMD_REFRESH    0x71
0030 #define FPGA_CMD_WRITE_EN   0x4a    /* plus 2 bits */
0031 #define FPGA_CMD_WRITE_DIS  0x4f    /* plus 8 bits */
0032 #define FPGA_CMD_WRITE_INC  0x41    /* plus 0 bits */
0033
0034 /*
0035  * The status register is 32bit revered, DONE is bit 17 from the TN1222.pdf
0036  * (LatticeECP3 Slave SPI Port User's Guide)
0037  */
0038 #define FPGA_STATUS_DONE    0x00004000
0039 #define FPGA_STATUS_CLEARED 0x00010000
0040
0041 #define FPGA_CLEAR_TIMEOUT  5000    /* max. 5000ms for FPGA clear */
0042 #define FPGA_CLEAR_MSLEEP   10
0043 #define FPGA_CLEAR_LOOP_COUNT   (FPGA_CLEAR_TIMEOUT / FPGA_CLEAR_MSLEEP)
0044
0045 struct fpga_data {
0046     struct completion fw_loaded;
0047 };
0048
0049 struct ecp3_dev {
0050     u32 jedec_id;
0051     char *name;
0052 };
0053
0054 static const struct ecp3_dev ecp3_dev[] = {
0055     {
0056         .jedec_id = ID_ECP3_17,
0057         .name = "Lattice ECP3-17",
0058     },
0059     {
0060         .jedec_id = ID_ECP3_35,
0061         .name = "Lattice ECP3-35",
0062     },
0063 };
0064
0065 static void firmware_load(const struct firmware *fw, void *context)
0066 {
0067     struct spi_device *spi = (struct spi_device *)context;
0068     struct fpga_data *data = spi_get_drvdata(spi);
0069     u8 *buffer;
0070     u8 txbuf[8];
0071     u8 rxbuf[8];
0072     int rx_len = 8;
0073     int i;
0074     u32 jedec_id;
0075     u32 status;
0076
0077     if (fw == NULL) {
0078         dev_err(&spi->dev, "Cannot load firmware, aborting\n");
0079         goto out;
0080     }
0081
0082     if (fw->size == 0) {
0083         dev_err(&spi->dev, "Error: Firmware size is 0!\n");
0084         goto out;
0085     }
0086
0087     /* Fill dummy data (24 stuffing bits for commands) */
0088     txbuf[1] = 0x00;
0089     txbuf[2] = 0x00;
0090     txbuf[3] = 0x00;
0091
0092     /* Trying to speak with the FPGA via SPI... */
0093     txbuf[0] = FPGA_CMD_READ_ID;
0094     spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
0095     jedec_id = get_unaligned_be32(&rxbuf[4]);
0096     dev_dbg(&spi->dev, "FPGA JTAG ID=%08x\n", jedec_id);
0097
0098     for (i = 0; i < ARRAY_SIZE(ecp3_dev); i++) {
0099         if (jedec_id == ecp3_dev[i].jedec_id)
0100             break;
0101     }
0102     if (i == ARRAY_SIZE(ecp3_dev)) {
0103         dev_err(&spi->dev,
0104             "Error: No supported FPGA detected (JEDEC_ID=%08x)!\n",
0105             jedec_id);
0106         goto out;
0107     }
0108
0109     dev_info(&spi->dev, "FPGA %s detected\n", ecp3_dev[i].name);
0110
0111     txbuf[0] = FPGA_CMD_READ_STATUS;
0112     spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
0113     status = get_unaligned_be32(&rxbuf[4]);
0114     dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);
0115
0116     buffer = kzalloc(fw->size + 8, GFP_KERNEL);
0117     if (!buffer) {
0118         dev_err(&spi->dev, "Error: Can't allocate memory!\n");
0119         goto out;
0120     }
0121
0122     /*
0123      * Insert WRITE_INC command into stream (one SPI frame)
0124      */
0125     buffer[0] = FPGA_CMD_WRITE_INC;
0126     buffer[1] = 0xff;
0127     buffer[2] = 0xff;
0128     buffer[3] = 0xff;
0129     memcpy(buffer + 4, fw->data, fw->size);
0130
0131     txbuf[0] = FPGA_CMD_REFRESH;
0132     spi_write(spi, txbuf, 4);
0133
0134     txbuf[0] = FPGA_CMD_WRITE_EN;
0135     spi_write(spi, txbuf, 4);
0136
0137     txbuf[0] = FPGA_CMD_CLEAR;
0138     spi_write(spi, txbuf, 4);
0139
0140     /*
0141      * Wait for FPGA memory to become cleared
0142      */
0143     for (i = 0; i < FPGA_CLEAR_LOOP_COUNT; i++) {
0144         txbuf[0] = FPGA_CMD_READ_STATUS;
0145         spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
0146         status = get_unaligned_be32(&rxbuf[4]);
0147         if (status == FPGA_STATUS_CLEARED)
0148             break;
0149
0150         msleep(FPGA_CLEAR_MSLEEP);
0151     }
0152
0153     if (i == FPGA_CLEAR_LOOP_COUNT) {
0154         dev_err(&spi->dev,
0155             "Error: Timeout waiting for FPGA to clear (status=%08x)!\n",
0156             status);
0157         kfree(buffer);
0158         goto out;
0159     }
0160
0161     dev_info(&spi->dev, "Configuring the FPGA...\n");
0162     spi_write(spi, buffer, fw->size + 8);
0163
0164     txbuf[0] = FPGA_CMD_WRITE_DIS;
0165     spi_write(spi, txbuf, 4);
0166
0167     txbuf[0] = FPGA_CMD_READ_STATUS;
0168     spi_write_then_read(spi, txbuf, 8, rxbuf, rx_len);
0169     status = get_unaligned_be32(&rxbuf[4]);
0170     dev_dbg(&spi->dev, "FPGA Status=%08x\n", status);
0171
0172     /* Check result */
0173     if (status & FPGA_STATUS_DONE)
0174         dev_info(&spi->dev, "FPGA successfully configured!\n");
0175     else
0176         dev_info(&spi->dev, "FPGA not configured (DONE not set)\n");
0177
0178     /*
0179      * Don't forget to release the firmware again
0180      */
0181     release_firmware(fw);
0182
0183     kfree(buffer);
0184 out:
0185     complete(&data->fw_loaded);
0186 }
0187
0188 static int lattice_ecp3_probe(struct spi_device *spi)
0189 {
0190     struct fpga_data *data;
0191     int err;
0192
0193     data = devm_kzalloc(&spi->dev, sizeof(*data), GFP_KERNEL);
0194     if (!data) {
0195         dev_err(&spi->dev, "Memory allocation for fpga_data failed\n");
0196         return -ENOMEM;
0197     }
0198     spi_set_drvdata(spi, data);
0199
0200     init_completion(&data->fw_loaded);
0201     err = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT,
0202                       FIRMWARE_NAME, &spi->dev,
0203                       GFP_KERNEL, spi, firmware_load);
0204     if (err) {
0205         dev_err(&spi->dev, "Firmware loading failed with %d!\n", err);
0206         return err;
0207     }
0208
0209     dev_info(&spi->dev, "FPGA bitstream configuration driver registered\n");
0210
0211     return 0;
0212 }
0213
0214 static void lattice_ecp3_remove(struct spi_device *spi)
0215 {
0216     struct fpga_data *data = spi_get_drvdata(spi);
0217
0218     wait_for_completion(&data->fw_loaded);
0219 }
0220
0221 static const struct spi_device_id lattice_ecp3_id[] = {
0222     { "ecp3-17", 0 },
0223     { "ecp3-35", 0 },
0224     { }
0225 };
0226 MODULE_DEVICE_TABLE(spi, lattice_ecp3_id);
0227
0228 static struct spi_driver lattice_ecp3_driver = {
0229     .driver = {
0230         .name = "lattice-ecp3",
0231     },
0232     .probe = lattice_ecp3_probe,
0233     .remove = lattice_ecp3_remove,
0234     .id_table = lattice_ecp3_id,
0235 };
0236
0237 module_spi_driver(lattice_ecp3_driver);
0238
0239 MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
0240 MODULE_DESCRIPTION("Lattice ECP3 FPGA configuration via SPI");
0241 MODULE_LICENSE("GPL");
0242 MODULE_FIRMWARE(FIRMWARE_NAME);