drivers/misc/ics932s401.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * A driver for the Integrated Circuits ICS932S401
0004  * Copyright (C) 2008 IBM
0005  *
0006  * Author: Darrick J. Wong <darrick.wong@oracle.com>
0007  */
0008
0009 #include <linux/module.h>
0010 #include <linux/jiffies.h>
0011 #include <linux/i2c.h>
0012 #include <linux/err.h>
0013 #include <linux/mutex.h>
0014 #include <linux/delay.h>
0015 #include <linux/log2.h>
0016 #include <linux/slab.h>
0017
0018 /* Addresses to scan */
0019 static const unsigned short normal_i2c[] = { 0x69, I2C_CLIENT_END };
0020
0021 /* ICS932S401 registers */
0022 #define ICS932S401_REG_CFG2         0x01
0023 #define     ICS932S401_CFG1_SPREAD      0x01
0024 #define ICS932S401_REG_CFG7         0x06
0025 #define     ICS932S401_FS_MASK      0x07
0026 #define ICS932S401_REG_VENDOR_REV       0x07
0027 #define     ICS932S401_VENDOR       1
0028 #define     ICS932S401_VENDOR_MASK      0x0F
0029 #define     ICS932S401_REV          4
0030 #define     ICS932S401_REV_SHIFT        4
0031 #define ICS932S401_REG_DEVICE           0x09
0032 #define     ICS932S401_DEVICE       11
0033 #define ICS932S401_REG_CTRL         0x0A
0034 #define     ICS932S401_MN_ENABLED       0x80
0035 #define     ICS932S401_CPU_ALT      0x04
0036 #define     ICS932S401_SRC_ALT      0x08
0037 #define ICS932S401_REG_CPU_M_CTRL       0x0B
0038 #define     ICS932S401_M_MASK       0x3F
0039 #define ICS932S401_REG_CPU_N_CTRL       0x0C
0040 #define ICS932S401_REG_CPU_SPREAD1      0x0D
0041 #define ICS932S401_REG_CPU_SPREAD2      0x0E
0042 #define     ICS932S401_SPREAD_MASK      0x7FFF
0043 #define ICS932S401_REG_SRC_M_CTRL       0x0F
0044 #define ICS932S401_REG_SRC_N_CTRL       0x10
0045 #define ICS932S401_REG_SRC_SPREAD1      0x11
0046 #define ICS932S401_REG_SRC_SPREAD2      0x12
0047 #define ICS932S401_REG_CPU_DIVISOR      0x13
0048 #define     ICS932S401_CPU_DIVISOR_SHIFT    4
0049 #define ICS932S401_REG_PCISRC_DIVISOR       0x14
0050 #define     ICS932S401_SRC_DIVISOR_MASK 0x0F
0051 #define     ICS932S401_PCI_DIVISOR_SHIFT    4
0052
0053 /* Base clock is 14.318MHz */
0054 #define BASE_CLOCK              14318
0055
0056 #define NUM_REGS                21
0057 #define NUM_MIRRORED_REGS           15
0058
0059 static int regs_to_copy[NUM_MIRRORED_REGS] = {
0060     ICS932S401_REG_CFG2,
0061     ICS932S401_REG_CFG7,
0062     ICS932S401_REG_VENDOR_REV,
0063     ICS932S401_REG_DEVICE,
0064     ICS932S401_REG_CTRL,
0065     ICS932S401_REG_CPU_M_CTRL,
0066     ICS932S401_REG_CPU_N_CTRL,
0067     ICS932S401_REG_CPU_SPREAD1,
0068     ICS932S401_REG_CPU_SPREAD2,
0069     ICS932S401_REG_SRC_M_CTRL,
0070     ICS932S401_REG_SRC_N_CTRL,
0071     ICS932S401_REG_SRC_SPREAD1,
0072     ICS932S401_REG_SRC_SPREAD2,
0073     ICS932S401_REG_CPU_DIVISOR,
0074     ICS932S401_REG_PCISRC_DIVISOR,
0075 };
0076
0077 /* How often do we reread sensors values? (In jiffies) */
0078 #define SENSOR_REFRESH_INTERVAL (2 * HZ)
0079
0080 /* How often do we reread sensor limit values? (In jiffies) */
0081 #define LIMIT_REFRESH_INTERVAL  (60 * HZ)
0082
0083 struct ics932s401_data {
0084     struct attribute_group  attrs;
0085     struct mutex        lock;
0086     char            sensors_valid;
0087     unsigned long       sensors_last_updated;   /* In jiffies */
0088
0089     u8          regs[NUM_REGS];
0090 };
0091
0092 static int ics932s401_probe(struct i2c_client *client,
0093              const struct i2c_device_id *id);
0094 static int ics932s401_detect(struct i2c_client *client,
0095               struct i2c_board_info *info);
0096 static int ics932s401_remove(struct i2c_client *client);
0097
0098 static const struct i2c_device_id ics932s401_id[] = {
0099     { "ics932s401", 0 },
0100     { }
0101 };
0102 MODULE_DEVICE_TABLE(i2c, ics932s401_id);
0103
0104 static struct i2c_driver ics932s401_driver = {
0105     .class      = I2C_CLASS_HWMON,
0106     .driver = {
0107         .name   = "ics932s401",
0108     },
0109     .probe      = ics932s401_probe,
0110     .remove     = ics932s401_remove,
0111     .id_table   = ics932s401_id,
0112     .detect     = ics932s401_detect,
0113     .address_list   = normal_i2c,
0114 };
0115
0116 static struct ics932s401_data *ics932s401_update_device(struct device *dev)
0117 {
0118     struct i2c_client *client = to_i2c_client(dev);
0119     struct ics932s401_data *data = i2c_get_clientdata(client);
0120     unsigned long local_jiffies = jiffies;
0121     int i, temp;
0122
0123     mutex_lock(&data->lock);
0124     if (time_before(local_jiffies, data->sensors_last_updated +
0125         SENSOR_REFRESH_INTERVAL)
0126         && data->sensors_valid)
0127         goto out;
0128
0129     /*
0130      * Each register must be read as a word and then right shifted 8 bits.
0131      * Not really sure why this is; setting the "byte count programming"
0132      * register to 1 does not fix this problem.
0133      */
0134     for (i = 0; i < NUM_MIRRORED_REGS; i++) {
0135         temp = i2c_smbus_read_word_data(client, regs_to_copy[i]);
0136         if (temp < 0)
0137             temp = 0;
0138         data->regs[regs_to_copy[i]] = temp >> 8;
0139     }
0140
0141     data->sensors_last_updated = local_jiffies;
0142     data->sensors_valid = 1;
0143
0144 out:
0145     mutex_unlock(&data->lock);
0146     return data;
0147 }
0148
0149 static ssize_t show_spread_enabled(struct device *dev,
0150                    struct device_attribute *devattr,
0151                    char *buf)
0152 {
0153     struct ics932s401_data *data = ics932s401_update_device(dev);
0154
0155     if (data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD)
0156         return sprintf(buf, "1\n");
0157
0158     return sprintf(buf, "0\n");
0159 }
0160
0161 /* bit to cpu khz map */
0162 static const int fs_speeds[] = {
0163     266666,
0164     133333,
0165     200000,
0166     166666,
0167     333333,
0168     100000,
0169     400000,
0170     0,
0171 };
0172
0173 /* clock divisor map */
0174 static const int divisors[] = {2, 3, 5, 15, 4, 6, 10, 30, 8, 12, 20, 60, 16,
0175                    24, 40, 120};
0176
0177 /* Calculate CPU frequency from the M/N registers. */
0178 static int calculate_cpu_freq(struct ics932s401_data *data)
0179 {
0180     int m, n, freq;
0181
0182     m = data->regs[ICS932S401_REG_CPU_M_CTRL] & ICS932S401_M_MASK;
0183     n = data->regs[ICS932S401_REG_CPU_N_CTRL];
0184
0185     /* Pull in bits 8 & 9 from the M register */
0186     n |= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x80) << 1;
0187     n |= ((int)data->regs[ICS932S401_REG_CPU_M_CTRL] & 0x40) << 3;
0188
0189     freq = BASE_CLOCK * (n + 8) / (m + 2);
0190     freq /= divisors[data->regs[ICS932S401_REG_CPU_DIVISOR] >>
0191              ICS932S401_CPU_DIVISOR_SHIFT];
0192
0193     return freq;
0194 }
0195
0196 static ssize_t show_cpu_clock(struct device *dev,
0197                   struct device_attribute *devattr,
0198                   char *buf)
0199 {
0200     struct ics932s401_data *data = ics932s401_update_device(dev);
0201
0202     return sprintf(buf, "%d\n", calculate_cpu_freq(data));
0203 }
0204
0205 static ssize_t show_cpu_clock_sel(struct device *dev,
0206                   struct device_attribute *devattr,
0207                   char *buf)
0208 {
0209     struct ics932s401_data *data = ics932s401_update_device(dev);
0210     int freq;
0211
0212     if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
0213         freq = calculate_cpu_freq(data);
0214     else {
0215         /* Freq is neatly wrapped up for us */
0216         int fid = data->regs[ICS932S401_REG_CFG7] & ICS932S401_FS_MASK;
0217
0218         freq = fs_speeds[fid];
0219         if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT) {
0220             switch (freq) {
0221             case 166666:
0222                 freq = 160000;
0223                 break;
0224             case 333333:
0225                 freq = 320000;
0226                 break;
0227             }
0228         }
0229     }
0230
0231     return sprintf(buf, "%d\n", freq);
0232 }
0233
0234 /* Calculate SRC frequency from the M/N registers. */
0235 static int calculate_src_freq(struct ics932s401_data *data)
0236 {
0237     int m, n, freq;
0238
0239     m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK;
0240     n = data->regs[ICS932S401_REG_SRC_N_CTRL];
0241
0242     /* Pull in bits 8 & 9 from the M register */
0243     n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1;
0244     n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3;
0245
0246     freq = BASE_CLOCK * (n + 8) / (m + 2);
0247     freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] &
0248              ICS932S401_SRC_DIVISOR_MASK];
0249
0250     return freq;
0251 }
0252
0253 static ssize_t show_src_clock(struct device *dev,
0254                   struct device_attribute *devattr,
0255                   char *buf)
0256 {
0257     struct ics932s401_data *data = ics932s401_update_device(dev);
0258
0259     return sprintf(buf, "%d\n", calculate_src_freq(data));
0260 }
0261
0262 static ssize_t show_src_clock_sel(struct device *dev,
0263                   struct device_attribute *devattr,
0264                   char *buf)
0265 {
0266     struct ics932s401_data *data = ics932s401_update_device(dev);
0267     int freq;
0268
0269     if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
0270         freq = calculate_src_freq(data);
0271     else
0272         /* Freq is neatly wrapped up for us */
0273         if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_CPU_ALT &&
0274             data->regs[ICS932S401_REG_CTRL] & ICS932S401_SRC_ALT)
0275             freq = 96000;
0276         else
0277             freq = 100000;
0278
0279     return sprintf(buf, "%d\n", freq);
0280 }
0281
0282 /* Calculate PCI frequency from the SRC M/N registers. */
0283 static int calculate_pci_freq(struct ics932s401_data *data)
0284 {
0285     int m, n, freq;
0286
0287     m = data->regs[ICS932S401_REG_SRC_M_CTRL] & ICS932S401_M_MASK;
0288     n = data->regs[ICS932S401_REG_SRC_N_CTRL];
0289
0290     /* Pull in bits 8 & 9 from the M register */
0291     n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x80) << 1;
0292     n |= ((int)data->regs[ICS932S401_REG_SRC_M_CTRL] & 0x40) << 3;
0293
0294     freq = BASE_CLOCK * (n + 8) / (m + 2);
0295     freq /= divisors[data->regs[ICS932S401_REG_PCISRC_DIVISOR] >>
0296              ICS932S401_PCI_DIVISOR_SHIFT];
0297
0298     return freq;
0299 }
0300
0301 static ssize_t show_pci_clock(struct device *dev,
0302                   struct device_attribute *devattr,
0303                   char *buf)
0304 {
0305     struct ics932s401_data *data = ics932s401_update_device(dev);
0306
0307     return sprintf(buf, "%d\n", calculate_pci_freq(data));
0308 }
0309
0310 static ssize_t show_pci_clock_sel(struct device *dev,
0311                   struct device_attribute *devattr,
0312                   char *buf)
0313 {
0314     struct ics932s401_data *data = ics932s401_update_device(dev);
0315     int freq;
0316
0317     if (data->regs[ICS932S401_REG_CTRL] & ICS932S401_MN_ENABLED)
0318         freq = calculate_pci_freq(data);
0319     else
0320         freq = 33333;
0321
0322     return sprintf(buf, "%d\n", freq);
0323 }
0324
0325 static ssize_t show_value(struct device *dev,
0326               struct device_attribute *devattr,
0327               char *buf);
0328
0329 static ssize_t show_spread(struct device *dev,
0330                struct device_attribute *devattr,
0331                char *buf);
0332
0333 static DEVICE_ATTR(spread_enabled, S_IRUGO, show_spread_enabled, NULL);
0334 static DEVICE_ATTR(cpu_clock_selection, S_IRUGO, show_cpu_clock_sel, NULL);
0335 static DEVICE_ATTR(cpu_clock, S_IRUGO, show_cpu_clock, NULL);
0336 static DEVICE_ATTR(src_clock_selection, S_IRUGO, show_src_clock_sel, NULL);
0337 static DEVICE_ATTR(src_clock, S_IRUGO, show_src_clock, NULL);
0338 static DEVICE_ATTR(pci_clock_selection, S_IRUGO, show_pci_clock_sel, NULL);
0339 static DEVICE_ATTR(pci_clock, S_IRUGO, show_pci_clock, NULL);
0340 static DEVICE_ATTR(usb_clock, S_IRUGO, show_value, NULL);
0341 static DEVICE_ATTR(ref_clock, S_IRUGO, show_value, NULL);
0342 static DEVICE_ATTR(cpu_spread, S_IRUGO, show_spread, NULL);
0343 static DEVICE_ATTR(src_spread, S_IRUGO, show_spread, NULL);
0344
0345 static struct attribute *ics932s401_attr[] = {
0346     &dev_attr_spread_enabled.attr,
0347     &dev_attr_cpu_clock_selection.attr,
0348     &dev_attr_cpu_clock.attr,
0349     &dev_attr_src_clock_selection.attr,
0350     &dev_attr_src_clock.attr,
0351     &dev_attr_pci_clock_selection.attr,
0352     &dev_attr_pci_clock.attr,
0353     &dev_attr_usb_clock.attr,
0354     &dev_attr_ref_clock.attr,
0355     &dev_attr_cpu_spread.attr,
0356     &dev_attr_src_spread.attr,
0357     NULL
0358 };
0359
0360 static ssize_t show_value(struct device *dev,
0361               struct device_attribute *devattr,
0362               char *buf)
0363 {
0364     int x;
0365
0366     if (devattr == &dev_attr_usb_clock)
0367         x = 48000;
0368     else if (devattr == &dev_attr_ref_clock)
0369         x = BASE_CLOCK;
0370     else
0371         BUG();
0372
0373     return sprintf(buf, "%d\n", x);
0374 }
0375
0376 static ssize_t show_spread(struct device *dev,
0377                struct device_attribute *devattr,
0378                char *buf)
0379 {
0380     struct ics932s401_data *data = ics932s401_update_device(dev);
0381     int reg;
0382     unsigned long val;
0383
0384     if (!(data->regs[ICS932S401_REG_CFG2] & ICS932S401_CFG1_SPREAD))
0385         return sprintf(buf, "0%%\n");
0386
0387     if (devattr == &dev_attr_src_spread)
0388         reg = ICS932S401_REG_SRC_SPREAD1;
0389     else if (devattr == &dev_attr_cpu_spread)
0390         reg = ICS932S401_REG_CPU_SPREAD1;
0391     else
0392         BUG();
0393
0394     val = data->regs[reg] | (data->regs[reg + 1] << 8);
0395     val &= ICS932S401_SPREAD_MASK;
0396
0397     /* Scale 0..2^14 to -0.5. */
0398     val = 500000 * val / 16384;
0399     return sprintf(buf, "-0.%lu%%\n", val);
0400 }
0401
0402 /* Return 0 if detection is successful, -ENODEV otherwise */
0403 static int ics932s401_detect(struct i2c_client *client,
0404               struct i2c_board_info *info)
0405 {
0406     struct i2c_adapter *adapter = client->adapter;
0407     int vendor, device, revision;
0408
0409     if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
0410         return -ENODEV;
0411
0412     vendor = i2c_smbus_read_word_data(client, ICS932S401_REG_VENDOR_REV);
0413     vendor >>= 8;
0414     revision = vendor >> ICS932S401_REV_SHIFT;
0415     vendor &= ICS932S401_VENDOR_MASK;
0416     if (vendor != ICS932S401_VENDOR)
0417         return -ENODEV;
0418
0419     device = i2c_smbus_read_word_data(client, ICS932S401_REG_DEVICE);
0420     device >>= 8;
0421     if (device != ICS932S401_DEVICE)
0422         return -ENODEV;
0423
0424     if (revision != ICS932S401_REV)
0425         dev_info(&adapter->dev, "Unknown revision %d\n", revision);
0426
0427     strlcpy(info->type, "ics932s401", I2C_NAME_SIZE);
0428
0429     return 0;
0430 }
0431
0432 static int ics932s401_probe(struct i2c_client *client,
0433              const struct i2c_device_id *id)
0434 {
0435     struct ics932s401_data *data;
0436     int err;
0437
0438     data = kzalloc(sizeof(struct ics932s401_data), GFP_KERNEL);
0439     if (!data) {
0440         err = -ENOMEM;
0441         goto exit;
0442     }
0443
0444     i2c_set_clientdata(client, data);
0445     mutex_init(&data->lock);
0446
0447     dev_info(&client->dev, "%s chip found\n", client->name);
0448
0449     /* Register sysfs hooks */
0450     data->attrs.attrs = ics932s401_attr;
0451     err = sysfs_create_group(&client->dev.kobj, &data->attrs);
0452     if (err)
0453         goto exit_free;
0454
0455     return 0;
0456
0457 exit_free:
0458     kfree(data);
0459 exit:
0460     return err;
0461 }
0462
0463 static int ics932s401_remove(struct i2c_client *client)
0464 {
0465     struct ics932s401_data *data = i2c_get_clientdata(client);
0466
0467     sysfs_remove_group(&client->dev.kobj, &data->attrs);
0468     kfree(data);
0469     return 0;
0470 }
0471
0472 module_i2c_driver(ics932s401_driver);
0473
0474 MODULE_AUTHOR("Darrick J. Wong <darrick.wong@oracle.com>");
0475 MODULE_DESCRIPTION("ICS932S401 driver");
0476 MODULE_LICENSE("GPL");
0477
0478 /* IBM IntelliStation Z30 */
0479 MODULE_ALIAS("dmi:bvnIBM:*:rn9228:*");
0480 MODULE_ALIAS("dmi:bvnIBM:*:rn9232:*");
0481
0482 /* IBM x3650/x3550 */
0483 MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3650*");
0484 MODULE_ALIAS("dmi:bvnIBM:*:pnIBMSystemx3550*");