misc/ibmasm/lowlevel.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * IBM ASM Service Processor Device Driver
0004  *
0005  * Copyright (C) IBM Corporation, 2004
0006  *
0007  * Author: Max Asböck <amax@us.ibm.com>
0008  */
0009
0010 /* Condor service processor specific hardware definitions */
0011
0012 #ifndef __IBMASM_CONDOR_H__
0013 #define __IBMASM_CONDOR_H__
0014
0015 #include <asm/io.h>
0016
0017 #define VENDORID_IBM    0x1014
0018 #define DEVICEID_RSA    0x010F
0019
0020 #define GET_MFA_ADDR(x)  (x & 0xFFFFFF00)
0021
0022 #define MAILBOX_FULL(x)  (x & 0x00000001)
0023
0024 #define NO_MFAS_AVAILABLE     0xFFFFFFFF
0025
0026
0027 #define INBOUND_QUEUE_PORT   0x40  /* contains address of next free MFA */
0028 #define OUTBOUND_QUEUE_PORT  0x44  /* contains address of posted MFA    */
0029
0030 #define SP_INTR_MASK    0x00000008
0031 #define UART_INTR_MASK  0x00000010
0032
0033 #define INTR_STATUS_REGISTER   0x13A0
0034 #define INTR_CONTROL_REGISTER  0x13A4
0035
0036 #define SCOUT_COM_A_BASE         0x0000
0037 #define SCOUT_COM_B_BASE         0x0100
0038 #define SCOUT_COM_C_BASE         0x0200
0039 #define SCOUT_COM_D_BASE         0x0300
0040
0041 static inline int sp_interrupt_pending(void __iomem *base_address)
0042 {
0043     return SP_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER);
0044 }
0045
0046 static inline int uart_interrupt_pending(void __iomem *base_address)
0047 {
0048     return UART_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER);
0049 }
0050
0051 static inline void ibmasm_enable_interrupts(void __iomem *base_address, int mask)
0052 {
0053     void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;
0054     writel( readl(ctrl_reg) & ~mask, ctrl_reg);
0055 }
0056
0057 static inline void ibmasm_disable_interrupts(void __iomem *base_address, int mask)
0058 {
0059     void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;
0060     writel( readl(ctrl_reg) | mask, ctrl_reg);
0061 }
0062
0063 static inline void enable_sp_interrupts(void __iomem *base_address)
0064 {
0065     ibmasm_enable_interrupts(base_address, SP_INTR_MASK);
0066 }
0067
0068 static inline void disable_sp_interrupts(void __iomem *base_address)
0069 {
0070     ibmasm_disable_interrupts(base_address, SP_INTR_MASK);
0071 }
0072
0073 static inline void enable_uart_interrupts(void __iomem *base_address)
0074 {
0075     ibmasm_enable_interrupts(base_address, UART_INTR_MASK);
0076 }
0077
0078 static inline void disable_uart_interrupts(void __iomem *base_address)
0079 {
0080     ibmasm_disable_interrupts(base_address, UART_INTR_MASK);
0081 }
0082
0083 #define valid_mfa(mfa)  ( (mfa) != NO_MFAS_AVAILABLE )
0084
0085 static inline u32 get_mfa_outbound(void __iomem *base_address)
0086 {
0087     int retry;
0088     u32 mfa;
0089
0090     for (retry=0; retry<=10; retry++) {
0091         mfa = readl(base_address + OUTBOUND_QUEUE_PORT);
0092         if (valid_mfa(mfa))
0093             break;
0094     }
0095     return mfa;
0096 }
0097
0098 static inline void set_mfa_outbound(void __iomem *base_address, u32 mfa)
0099 {
0100     writel(mfa, base_address + OUTBOUND_QUEUE_PORT);
0101 }
0102
0103 static inline u32 get_mfa_inbound(void __iomem *base_address)
0104 {
0105     u32 mfa = readl(base_address + INBOUND_QUEUE_PORT);
0106
0107     if (MAILBOX_FULL(mfa))
0108         return 0;
0109
0110     return mfa;
0111 }
0112
0113 static inline void set_mfa_inbound(void __iomem *base_address, u32 mfa)
0114 {
0115     writel(mfa, base_address + INBOUND_QUEUE_PORT);
0116 }
0117
0118 static inline struct i2o_message *get_i2o_message(void __iomem *base_address, u32 mfa)
0119 {
0120     return (struct i2o_message *)(GET_MFA_ADDR(mfa) + base_address);
0121 }
0122
0123 #endif /* __IBMASM_CONDOR_H__ */