drivers/misc/hpilo.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * linux/drivers/char/hpilo.h
0004  *
0005  * Copyright (C) 2008 Hewlett-Packard Development Company, L.P.
0006  *  David Altobelli <david.altobelli@hp.com>
0007  */
0008 #ifndef __HPILO_H
0009 #define __HPILO_H
0010
0011 #define ILO_NAME "hpilo"
0012
0013 /* iLO ASIC PCI revision id */
0014 #define PCI_REV_ID_NECHES   7
0015
0016 /* max number of open channel control blocks per device, hw limited to 32 */
0017 #define MAX_CCB        24
0018 /* min number of open channel control blocks per device, hw limited to 32 */
0019 #define MIN_CCB     8
0020 /* max number of supported devices */
0021 #define MAX_ILO_DEV 1
0022 /* max number of files */
0023 #define MAX_OPEN    (MAX_CCB * MAX_ILO_DEV)
0024 /* total wait time in usec */
0025 #define MAX_WAIT_TIME   10000
0026 /* per spin wait time in usec */
0027 #define WAIT_TIME   10
0028 /* spin counter for open/close delay */
0029 #define MAX_WAIT    (MAX_WAIT_TIME / WAIT_TIME)
0030
0031 /*
0032  * Per device, used to track global memory allocations.
0033  */
0034 struct ilo_hwinfo {
0035     /* mmio registers on device */
0036     char __iomem *mmio_vaddr;
0037
0038     /* doorbell registers on device */
0039     char __iomem *db_vaddr;
0040
0041     /* shared memory on device used for channel control blocks */
0042     char __iomem *ram_vaddr;
0043
0044     /* files corresponding to this device */
0045     struct ccb_data *ccb_alloc[MAX_CCB];
0046
0047     struct pci_dev *ilo_dev;
0048
0049     /*
0050      * open_lock      serializes ccb_cnt during open and close
0051      * [ irq disabled ]
0052      * -> alloc_lock  used when adding/removing/searching ccb_alloc,
0053      *                which represents all ccbs open on the device
0054      * --> fifo_lock  controls access to fifo queues shared with hw
0055      *
0056      * Locks must be taken in this order, but open_lock and alloc_lock
0057      * are optional, they do not need to be held in order to take a
0058      * lower level lock.
0059      */
0060     spinlock_t open_lock;
0061     spinlock_t alloc_lock;
0062     spinlock_t fifo_lock;
0063
0064     struct cdev cdev;
0065 };
0066
0067 /* offset from mmio_vaddr for enabling doorbell interrupts */
0068 #define DB_IRQ      0xB2
0069 /* offset from mmio_vaddr for outbound communications */
0070 #define DB_OUT      0xD4
0071 /* DB_OUT reset bit */
0072 #define DB_RESET    26
0073
0074 /*
0075  * Channel control block. Used to manage hardware queues.
0076  * The format must match hw's version.  The hw ccb is 128 bytes,
0077  * but the context area shouldn't be touched by the driver.
0078  */
0079 #define ILOSW_CCB_SZ    64
0080 #define ILOHW_CCB_SZ    128
0081 struct ccb {
0082     union {
0083         char *send_fifobar;
0084         u64 send_fifobar_pa;
0085     } ccb_u1;
0086     union {
0087         char *send_desc;
0088         u64 send_desc_pa;
0089     } ccb_u2;
0090     u64 send_ctrl;
0091
0092     union {
0093         char *recv_fifobar;
0094         u64 recv_fifobar_pa;
0095     } ccb_u3;
0096     union {
0097         char *recv_desc;
0098         u64 recv_desc_pa;
0099     } ccb_u4;
0100     u64 recv_ctrl;
0101
0102     union {
0103         char __iomem *db_base;
0104         u64 padding5;
0105     } ccb_u5;
0106
0107     u64 channel;
0108
0109     /* unused context area (64 bytes) */
0110 };
0111
0112 /* ccb queue parameters */
0113 #define SENDQ       1
0114 #define RECVQ       2
0115 #define NR_QENTRY       4
0116 #define L2_QENTRY_SZ    12
0117
0118 /* ccb ctrl bitfields */
0119 #define CTRL_BITPOS_L2SZ             0
0120 #define CTRL_BITPOS_FIFOINDEXMASK    4
0121 #define CTRL_BITPOS_DESCLIMIT        18
0122 #define CTRL_BITPOS_A                30
0123 #define CTRL_BITPOS_G                31
0124
0125 /* ccb doorbell macros */
0126 #define L2_DB_SIZE      14
0127 #define ONE_DB_SIZE     (1 << L2_DB_SIZE)
0128
0129 /*
0130  * Per fd structure used to track the ccb allocated to that dev file.
0131  */
0132 struct ccb_data {
0133     /* software version of ccb, using virtual addrs */
0134     struct ccb  driver_ccb;
0135
0136     /* hardware version of ccb, using physical addrs */
0137     struct ccb  ilo_ccb;
0138
0139     /* hardware ccb is written to this shared mapped device memory */
0140     struct ccb __iomem *mapped_ccb;
0141
0142     /* dma'able memory used for send/recv queues */
0143     void       *dma_va;
0144     dma_addr_t  dma_pa;
0145     size_t      dma_size;
0146
0147     /* pointer to hardware device info */
0148     struct ilo_hwinfo *ilo_hw;
0149
0150     /* queue for this ccb to wait for recv data */
0151     wait_queue_head_t ccb_waitq;
0152
0153     /* usage count, to allow for shared ccb's */
0154     int     ccb_cnt;
0155
0156     /* open wanted exclusive access to this ccb */
0157     int     ccb_excl;
0158 };
0159
0160 /*
0161  * FIFO queue structure, shared with hw.
0162  */
0163 #define ILO_START_ALIGN 4096
0164 #define ILO_CACHE_SZ     128
0165 struct fifo {
0166     u64 nrents; /* user requested number of fifo entries */
0167     u64 imask;  /* mask to extract valid fifo index */
0168     u64 merge;  /*  O/C bits to merge in during enqueue operation */
0169     u64 reset;  /* set to non-zero when the target device resets */
0170     u8  pad_0[ILO_CACHE_SZ - (sizeof(u64) * 4)];
0171
0172     u64 head;
0173     u8  pad_1[ILO_CACHE_SZ - (sizeof(u64))];
0174
0175     u64 tail;
0176     u8  pad_2[ILO_CACHE_SZ - (sizeof(u64))];
0177
0178     u64 fifobar[];
0179 };
0180
0181 /* convert between struct fifo, and the fifobar, which is saved in the ccb */
0182 #define FIFOHANDLESIZE (sizeof(struct fifo))
0183 #define FIFOBARTOHANDLE(_fifo) \
0184     ((struct fifo *)(((char *)(_fifo)) - FIFOHANDLESIZE))
0185
0186 /* the number of qwords to consume from the entry descriptor */
0187 #define ENTRY_BITPOS_QWORDS      0
0188 /* descriptor index number (within a specified queue) */
0189 #define ENTRY_BITPOS_DESCRIPTOR  10
0190 /* state bit, fifo entry consumed by consumer */
0191 #define ENTRY_BITPOS_C           22
0192 /* state bit, fifo entry is occupied */
0193 #define ENTRY_BITPOS_O           23
0194
0195 #define ENTRY_BITS_QWORDS        10
0196 #define ENTRY_BITS_DESCRIPTOR    12
0197 #define ENTRY_BITS_C             1
0198 #define ENTRY_BITS_O             1
0199 #define ENTRY_BITS_TOTAL    \
0200     (ENTRY_BITS_C + ENTRY_BITS_O + \
0201      ENTRY_BITS_QWORDS + ENTRY_BITS_DESCRIPTOR)
0202
0203 /* extract various entry fields */
0204 #define ENTRY_MASK ((1 << ENTRY_BITS_TOTAL) - 1)
0205 #define ENTRY_MASK_C (((1 << ENTRY_BITS_C) - 1) << ENTRY_BITPOS_C)
0206 #define ENTRY_MASK_O (((1 << ENTRY_BITS_O) - 1) << ENTRY_BITPOS_O)
0207 #define ENTRY_MASK_QWORDS \
0208     (((1 << ENTRY_BITS_QWORDS) - 1) << ENTRY_BITPOS_QWORDS)
0209 #define ENTRY_MASK_DESCRIPTOR \
0210     (((1 << ENTRY_BITS_DESCRIPTOR) - 1) << ENTRY_BITPOS_DESCRIPTOR)
0211
0212 #define ENTRY_MASK_NOSTATE (ENTRY_MASK >> (ENTRY_BITS_C + ENTRY_BITS_O))
0213
0214 #endif /* __HPILO_H */