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0008 #ifndef INCLUDE_MMU_V1_1_H_
0009 #define INCLUDE_MMU_V1_1_H_
0010
0011 #define MMU_V1_1_HOP0_MASK 0x3000000000000ull
0012 #define MMU_V1_1_HOP1_MASK 0x0FF8000000000ull
0013 #define MMU_V1_1_HOP2_MASK 0x0007FC0000000ull
0014 #define MMU_V1_1_HOP3_MASK 0x000003FE00000ull
0015 #define MMU_V1_1_HOP4_MASK 0x00000001FF000ull
0016
0017 #define MMU_V1_1_HOP0_SHIFT 48
0018 #define MMU_V1_1_HOP1_SHIFT 39
0019 #define MMU_V1_1_HOP2_SHIFT 30
0020 #define MMU_V1_1_HOP3_SHIFT 21
0021 #define MMU_V1_1_HOP4_SHIFT 12
0022
0023 #define MMU_ASID 0xC12004
0024 #define MMU_HOP0_PA43_12 0xC12008
0025 #define MMU_HOP0_PA49_44 0xC1200C
0026 #define MMU_BUSY 0xC12000
0027
0028 #endif