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0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2016-2018 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007 
0008 /************************************
0009  ** This is an auto-generated file **
0010  **       DO NOT EDIT BELOW        **
0011  ************************************/
0012 
0013 #ifndef ASIC_REG_TPC4_RTR_REGS_H_
0014 #define ASIC_REG_TPC4_RTR_REGS_H_
0015 
0016 /*
0017  *****************************************
0018  *   TPC4_RTR (Prototype: TPC_RTR)
0019  *****************************************
0020  */
0021 
0022 #define mmTPC4_RTR_HBW_RD_RQ_E_ARB                                   0xF00100
0023 
0024 #define mmTPC4_RTR_HBW_RD_RQ_W_ARB                                   0xF00104
0025 
0026 #define mmTPC4_RTR_HBW_RD_RQ_N_ARB                                   0xF00108
0027 
0028 #define mmTPC4_RTR_HBW_RD_RQ_S_ARB                                   0xF0010C
0029 
0030 #define mmTPC4_RTR_HBW_RD_RQ_L_ARB                                   0xF00110
0031 
0032 #define mmTPC4_RTR_HBW_E_ARB_MAX                                     0xF00120
0033 
0034 #define mmTPC4_RTR_HBW_W_ARB_MAX                                     0xF00124
0035 
0036 #define mmTPC4_RTR_HBW_N_ARB_MAX                                     0xF00128
0037 
0038 #define mmTPC4_RTR_HBW_S_ARB_MAX                                     0xF0012C
0039 
0040 #define mmTPC4_RTR_HBW_L_ARB_MAX                                     0xF00130
0041 
0042 #define mmTPC4_RTR_HBW_RD_RS_E_ARB                                   0xF00140
0043 
0044 #define mmTPC4_RTR_HBW_RD_RS_W_ARB                                   0xF00144
0045 
0046 #define mmTPC4_RTR_HBW_RD_RS_N_ARB                                   0xF00148
0047 
0048 #define mmTPC4_RTR_HBW_RD_RS_S_ARB                                   0xF0014C
0049 
0050 #define mmTPC4_RTR_HBW_RD_RS_L_ARB                                   0xF00150
0051 
0052 #define mmTPC4_RTR_HBW_WR_RQ_E_ARB                                   0xF00170
0053 
0054 #define mmTPC4_RTR_HBW_WR_RQ_W_ARB                                   0xF00174
0055 
0056 #define mmTPC4_RTR_HBW_WR_RQ_N_ARB                                   0xF00178
0057 
0058 #define mmTPC4_RTR_HBW_WR_RQ_S_ARB                                   0xF0017C
0059 
0060 #define mmTPC4_RTR_HBW_WR_RQ_L_ARB                                   0xF00180
0061 
0062 #define mmTPC4_RTR_HBW_WR_RS_E_ARB                                   0xF00190
0063 
0064 #define mmTPC4_RTR_HBW_WR_RS_W_ARB                                   0xF00194
0065 
0066 #define mmTPC4_RTR_HBW_WR_RS_N_ARB                                   0xF00198
0067 
0068 #define mmTPC4_RTR_HBW_WR_RS_S_ARB                                   0xF0019C
0069 
0070 #define mmTPC4_RTR_HBW_WR_RS_L_ARB                                   0xF001A0
0071 
0072 #define mmTPC4_RTR_LBW_RD_RQ_E_ARB                                   0xF00200
0073 
0074 #define mmTPC4_RTR_LBW_RD_RQ_W_ARB                                   0xF00204
0075 
0076 #define mmTPC4_RTR_LBW_RD_RQ_N_ARB                                   0xF00208
0077 
0078 #define mmTPC4_RTR_LBW_RD_RQ_S_ARB                                   0xF0020C
0079 
0080 #define mmTPC4_RTR_LBW_RD_RQ_L_ARB                                   0xF00210
0081 
0082 #define mmTPC4_RTR_LBW_E_ARB_MAX                                     0xF00220
0083 
0084 #define mmTPC4_RTR_LBW_W_ARB_MAX                                     0xF00224
0085 
0086 #define mmTPC4_RTR_LBW_N_ARB_MAX                                     0xF00228
0087 
0088 #define mmTPC4_RTR_LBW_S_ARB_MAX                                     0xF0022C
0089 
0090 #define mmTPC4_RTR_LBW_L_ARB_MAX                                     0xF00230
0091 
0092 #define mmTPC4_RTR_LBW_RD_RS_E_ARB                                   0xF00250
0093 
0094 #define mmTPC4_RTR_LBW_RD_RS_W_ARB                                   0xF00254
0095 
0096 #define mmTPC4_RTR_LBW_RD_RS_N_ARB                                   0xF00258
0097 
0098 #define mmTPC4_RTR_LBW_RD_RS_S_ARB                                   0xF0025C
0099 
0100 #define mmTPC4_RTR_LBW_RD_RS_L_ARB                                   0xF00260
0101 
0102 #define mmTPC4_RTR_LBW_WR_RQ_E_ARB                                   0xF00270
0103 
0104 #define mmTPC4_RTR_LBW_WR_RQ_W_ARB                                   0xF00274
0105 
0106 #define mmTPC4_RTR_LBW_WR_RQ_N_ARB                                   0xF00278
0107 
0108 #define mmTPC4_RTR_LBW_WR_RQ_S_ARB                                   0xF0027C
0109 
0110 #define mmTPC4_RTR_LBW_WR_RQ_L_ARB                                   0xF00280
0111 
0112 #define mmTPC4_RTR_LBW_WR_RS_E_ARB                                   0xF00290
0113 
0114 #define mmTPC4_RTR_LBW_WR_RS_W_ARB                                   0xF00294
0115 
0116 #define mmTPC4_RTR_LBW_WR_RS_N_ARB                                   0xF00298
0117 
0118 #define mmTPC4_RTR_LBW_WR_RS_S_ARB                                   0xF0029C
0119 
0120 #define mmTPC4_RTR_LBW_WR_RS_L_ARB                                   0xF002A0
0121 
0122 #define mmTPC4_RTR_DBG_E_ARB                                         0xF00300
0123 
0124 #define mmTPC4_RTR_DBG_W_ARB                                         0xF00304
0125 
0126 #define mmTPC4_RTR_DBG_N_ARB                                         0xF00308
0127 
0128 #define mmTPC4_RTR_DBG_S_ARB                                         0xF0030C
0129 
0130 #define mmTPC4_RTR_DBG_L_ARB                                         0xF00310
0131 
0132 #define mmTPC4_RTR_DBG_E_ARB_MAX                                     0xF00320
0133 
0134 #define mmTPC4_RTR_DBG_W_ARB_MAX                                     0xF00324
0135 
0136 #define mmTPC4_RTR_DBG_N_ARB_MAX                                     0xF00328
0137 
0138 #define mmTPC4_RTR_DBG_S_ARB_MAX                                     0xF0032C
0139 
0140 #define mmTPC4_RTR_DBG_L_ARB_MAX                                     0xF00330
0141 
0142 #define mmTPC4_RTR_SPLIT_COEF_0                                      0xF00400
0143 
0144 #define mmTPC4_RTR_SPLIT_COEF_1                                      0xF00404
0145 
0146 #define mmTPC4_RTR_SPLIT_COEF_2                                      0xF00408
0147 
0148 #define mmTPC4_RTR_SPLIT_COEF_3                                      0xF0040C
0149 
0150 #define mmTPC4_RTR_SPLIT_COEF_4                                      0xF00410
0151 
0152 #define mmTPC4_RTR_SPLIT_COEF_5                                      0xF00414
0153 
0154 #define mmTPC4_RTR_SPLIT_COEF_6                                      0xF00418
0155 
0156 #define mmTPC4_RTR_SPLIT_COEF_7                                      0xF0041C
0157 
0158 #define mmTPC4_RTR_SPLIT_COEF_8                                      0xF00420
0159 
0160 #define mmTPC4_RTR_SPLIT_COEF_9                                      0xF00424
0161 
0162 #define mmTPC4_RTR_SPLIT_CFG                                         0xF00440
0163 
0164 #define mmTPC4_RTR_SPLIT_RD_SAT                                      0xF00444
0165 
0166 #define mmTPC4_RTR_SPLIT_RD_RST_TOKEN                                0xF00448
0167 
0168 #define mmTPC4_RTR_SPLIT_RD_TIMEOUT_0                                0xF0044C
0169 
0170 #define mmTPC4_RTR_SPLIT_RD_TIMEOUT_1                                0xF00450
0171 
0172 #define mmTPC4_RTR_SPLIT_WR_SAT                                      0xF00454
0173 
0174 #define mmTPC4_RTR_WPLIT_WR_TST_TOLEN                                0xF00458
0175 
0176 #define mmTPC4_RTR_SPLIT_WR_TIMEOUT_0                                0xF0045C
0177 
0178 #define mmTPC4_RTR_SPLIT_WR_TIMEOUT_1                                0xF00460
0179 
0180 #define mmTPC4_RTR_HBW_RANGE_HIT                                     0xF00470
0181 
0182 #define mmTPC4_RTR_HBW_RANGE_MASK_L_0                                0xF00480
0183 
0184 #define mmTPC4_RTR_HBW_RANGE_MASK_L_1                                0xF00484
0185 
0186 #define mmTPC4_RTR_HBW_RANGE_MASK_L_2                                0xF00488
0187 
0188 #define mmTPC4_RTR_HBW_RANGE_MASK_L_3                                0xF0048C
0189 
0190 #define mmTPC4_RTR_HBW_RANGE_MASK_L_4                                0xF00490
0191 
0192 #define mmTPC4_RTR_HBW_RANGE_MASK_L_5                                0xF00494
0193 
0194 #define mmTPC4_RTR_HBW_RANGE_MASK_L_6                                0xF00498
0195 
0196 #define mmTPC4_RTR_HBW_RANGE_MASK_L_7                                0xF0049C
0197 
0198 #define mmTPC4_RTR_HBW_RANGE_MASK_H_0                                0xF004A0
0199 
0200 #define mmTPC4_RTR_HBW_RANGE_MASK_H_1                                0xF004A4
0201 
0202 #define mmTPC4_RTR_HBW_RANGE_MASK_H_2                                0xF004A8
0203 
0204 #define mmTPC4_RTR_HBW_RANGE_MASK_H_3                                0xF004AC
0205 
0206 #define mmTPC4_RTR_HBW_RANGE_MASK_H_4                                0xF004B0
0207 
0208 #define mmTPC4_RTR_HBW_RANGE_MASK_H_5                                0xF004B4
0209 
0210 #define mmTPC4_RTR_HBW_RANGE_MASK_H_6                                0xF004B8
0211 
0212 #define mmTPC4_RTR_HBW_RANGE_MASK_H_7                                0xF004BC
0213 
0214 #define mmTPC4_RTR_HBW_RANGE_BASE_L_0                                0xF004C0
0215 
0216 #define mmTPC4_RTR_HBW_RANGE_BASE_L_1                                0xF004C4
0217 
0218 #define mmTPC4_RTR_HBW_RANGE_BASE_L_2                                0xF004C8
0219 
0220 #define mmTPC4_RTR_HBW_RANGE_BASE_L_3                                0xF004CC
0221 
0222 #define mmTPC4_RTR_HBW_RANGE_BASE_L_4                                0xF004D0
0223 
0224 #define mmTPC4_RTR_HBW_RANGE_BASE_L_5                                0xF004D4
0225 
0226 #define mmTPC4_RTR_HBW_RANGE_BASE_L_6                                0xF004D8
0227 
0228 #define mmTPC4_RTR_HBW_RANGE_BASE_L_7                                0xF004DC
0229 
0230 #define mmTPC4_RTR_HBW_RANGE_BASE_H_0                                0xF004E0
0231 
0232 #define mmTPC4_RTR_HBW_RANGE_BASE_H_1                                0xF004E4
0233 
0234 #define mmTPC4_RTR_HBW_RANGE_BASE_H_2                                0xF004E8
0235 
0236 #define mmTPC4_RTR_HBW_RANGE_BASE_H_3                                0xF004EC
0237 
0238 #define mmTPC4_RTR_HBW_RANGE_BASE_H_4                                0xF004F0
0239 
0240 #define mmTPC4_RTR_HBW_RANGE_BASE_H_5                                0xF004F4
0241 
0242 #define mmTPC4_RTR_HBW_RANGE_BASE_H_6                                0xF004F8
0243 
0244 #define mmTPC4_RTR_HBW_RANGE_BASE_H_7                                0xF004FC
0245 
0246 #define mmTPC4_RTR_LBW_RANGE_HIT                                     0xF00500
0247 
0248 #define mmTPC4_RTR_LBW_RANGE_MASK_0                                  0xF00510
0249 
0250 #define mmTPC4_RTR_LBW_RANGE_MASK_1                                  0xF00514
0251 
0252 #define mmTPC4_RTR_LBW_RANGE_MASK_2                                  0xF00518
0253 
0254 #define mmTPC4_RTR_LBW_RANGE_MASK_3                                  0xF0051C
0255 
0256 #define mmTPC4_RTR_LBW_RANGE_MASK_4                                  0xF00520
0257 
0258 #define mmTPC4_RTR_LBW_RANGE_MASK_5                                  0xF00524
0259 
0260 #define mmTPC4_RTR_LBW_RANGE_MASK_6                                  0xF00528
0261 
0262 #define mmTPC4_RTR_LBW_RANGE_MASK_7                                  0xF0052C
0263 
0264 #define mmTPC4_RTR_LBW_RANGE_MASK_8                                  0xF00530
0265 
0266 #define mmTPC4_RTR_LBW_RANGE_MASK_9                                  0xF00534
0267 
0268 #define mmTPC4_RTR_LBW_RANGE_MASK_10                                 0xF00538
0269 
0270 #define mmTPC4_RTR_LBW_RANGE_MASK_11                                 0xF0053C
0271 
0272 #define mmTPC4_RTR_LBW_RANGE_MASK_12                                 0xF00540
0273 
0274 #define mmTPC4_RTR_LBW_RANGE_MASK_13                                 0xF00544
0275 
0276 #define mmTPC4_RTR_LBW_RANGE_MASK_14                                 0xF00548
0277 
0278 #define mmTPC4_RTR_LBW_RANGE_MASK_15                                 0xF0054C
0279 
0280 #define mmTPC4_RTR_LBW_RANGE_BASE_0                                  0xF00550
0281 
0282 #define mmTPC4_RTR_LBW_RANGE_BASE_1                                  0xF00554
0283 
0284 #define mmTPC4_RTR_LBW_RANGE_BASE_2                                  0xF00558
0285 
0286 #define mmTPC4_RTR_LBW_RANGE_BASE_3                                  0xF0055C
0287 
0288 #define mmTPC4_RTR_LBW_RANGE_BASE_4                                  0xF00560
0289 
0290 #define mmTPC4_RTR_LBW_RANGE_BASE_5                                  0xF00564
0291 
0292 #define mmTPC4_RTR_LBW_RANGE_BASE_6                                  0xF00568
0293 
0294 #define mmTPC4_RTR_LBW_RANGE_BASE_7                                  0xF0056C
0295 
0296 #define mmTPC4_RTR_LBW_RANGE_BASE_8                                  0xF00570
0297 
0298 #define mmTPC4_RTR_LBW_RANGE_BASE_9                                  0xF00574
0299 
0300 #define mmTPC4_RTR_LBW_RANGE_BASE_10                                 0xF00578
0301 
0302 #define mmTPC4_RTR_LBW_RANGE_BASE_11                                 0xF0057C
0303 
0304 #define mmTPC4_RTR_LBW_RANGE_BASE_12                                 0xF00580
0305 
0306 #define mmTPC4_RTR_LBW_RANGE_BASE_13                                 0xF00584
0307 
0308 #define mmTPC4_RTR_LBW_RANGE_BASE_14                                 0xF00588
0309 
0310 #define mmTPC4_RTR_LBW_RANGE_BASE_15                                 0xF0058C
0311 
0312 #define mmTPC4_RTR_RGLTR                                             0xF00590
0313 
0314 #define mmTPC4_RTR_RGLTR_WR_RESULT                                   0xF00594
0315 
0316 #define mmTPC4_RTR_RGLTR_RD_RESULT                                   0xF00598
0317 
0318 #define mmTPC4_RTR_SCRAMB_EN                                         0xF00600
0319 
0320 #define mmTPC4_RTR_NON_LIN_SCRAMB                                    0xF00604
0321 
0322 #endif /* ASIC_REG_TPC4_RTR_REGS_H_ */