OSCL-LXR linux-6.0.1/​drivers/​misc/​habanalabs/​include/​goya/​asic_reg/​tpc0_cfg_masks.h	Source navigation Diff markup Identifier search General search
	Version: linux-6.0.1 spark-3.0.0 hadoop-3.2.0-src hadoop-3.3.0-src spark-2.4.7 linux-4.15.13 hadoop-2.7.4-src Revert   Change

 /* SPDX-License-Identifier: GPL-2.0
  *
  * Copyright 2016-2018 HabanaLabs, Ltd.
  * All Rights Reserved.
  *
  */
 
 /************************************
  ** This is an auto-generated file **
  **       DO NOT EDIT BELOW        **
  ************************************/
 
 #ifndef ASIC_REG_TPC0_CFG_MASKS_H_
 #define ASIC_REG_TPC0_CFG_MASKS_H_
 
 /*
  *****************************************
  *   TPC0_CFG (Prototype: TPC)
  *****************************************
  */
 
 /* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */
 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */
 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT              0
 #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */
 #define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT               0
 #define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT       0
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK        0x3
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT  8
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK   0x1F00
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT        16
 #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK         0x70000
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT                  0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT                0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK                 0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET_V_SHIFT           0
 #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET_V_MASK            0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */
 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT              0
 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK               0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */
 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT             0
 #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK              0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT                       0
 #define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_SRF */
 #define TPC0_CFG_KERNEL_SRF_V_SHIFT                                  0
 #define TPC0_CFG_KERNEL_SRF_V_MASK                                   0xFFFFFFFF
 
 /* TPC0_CFG_KERNEL_KERNEL_CONFIG */
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT                0
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK                 0x1
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT             1
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK              0x2
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT           8
 #define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK            0x3F00
 
 /* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT     0
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK      0xFFFF
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT  16
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK   0x7FFF0000
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT       31
 #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK        0x80000000
 
 /* TPC0_CFG_RESERVED_DESC_END */
 #define TPC0_CFG_RESERVED_DESC_END_V_SHIFT                           0
 #define TPC0_CFG_RESERVED_DESC_END_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_ROUND_CSR */
 #define TPC0_CFG_ROUND_CSR_MODE_SHIFT                                0
 #define TPC0_CFG_ROUND_CSR_MODE_MASK                                 0x7
 
 /* TPC0_CFG_TBUF_BASE_ADDR_LOW */
 #define TPC0_CFG_TBUF_BASE_ADDR_LOW_V_SHIFT                          0
 #define TPC0_CFG_TBUF_BASE_ADDR_LOW_V_MASK                           0xFFFFFFFF
 
 /* TPC0_CFG_TBUF_BASE_ADDR_HIGH */
 #define TPC0_CFG_TBUF_BASE_ADDR_HIGH_V_SHIFT                         0
 #define TPC0_CFG_TBUF_BASE_ADDR_HIGH_V_MASK                          0xFFFFFFFF
 
 /* TPC0_CFG_SEMAPHORE */
 #define TPC0_CFG_SEMAPHORE_V_SHIFT                                   0
 #define TPC0_CFG_SEMAPHORE_V_MASK                                    0xFFFFFFFF
 
 /* TPC0_CFG_VFLAGS */
 #define TPC0_CFG_VFLAGS_V_SHIFT                                      0
 #define TPC0_CFG_VFLAGS_V_MASK                                       0xF
 
 /* TPC0_CFG_SFLAGS */
 #define TPC0_CFG_SFLAGS_V_SHIFT                                      0
 #define TPC0_CFG_SFLAGS_V_MASK                                       0xF
 
 /* TPC0_CFG_LFSR_POLYNOM */
 #define TPC0_CFG_LFSR_POLYNOM_V_SHIFT                                0
 #define TPC0_CFG_LFSR_POLYNOM_V_MASK                                 0xFFFFFFFF
 
 /* TPC0_CFG_STATUS */
 #define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT                      1
 #define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK                       0x2
 #define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT                      2
 #define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK                       0x4
 #define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT                               3
 #define TPC0_CFG_STATUS_IQ_EMPTY_MASK                                0x8
 #define TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_SHIFT                4
 #define TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_MASK                 0x10
 
 /* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */
 #define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT                       0
 #define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK                        0xFFFFFFFF
 
 /* TPC0_CFG_CFG_SUBTRACT_VALUE */
 #define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT                          0
 #define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK                           0xFFFFFFFF
 
 /* TPC0_CFG_SM_BASE_ADDRESS_LOW */
 #define TPC0_CFG_SM_BASE_ADDRESS_LOW_V_SHIFT                         0
 #define TPC0_CFG_SM_BASE_ADDRESS_LOW_V_MASK                          0xFFFFFFFF
 
 /* TPC0_CFG_SM_BASE_ADDRESS_HIGH */
 #define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT                        0
 #define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK                         0xFFFFFFFF
 
 /* TPC0_CFG_TPC_CMD */
 #define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT                     0
 #define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK                      0x1
 #define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT                     1
 #define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK                      0x2
 #define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT                     2
 #define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK                      0x4
 #define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT                     3
 #define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK                      0x8
 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT                  4
 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK                   0x10
 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT                  5
 #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK                   0x20
 #define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT                             6
 #define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK                              0x40
 
 /* TPC0_CFG_TPC_EXECUTE */
 #define TPC0_CFG_TPC_EXECUTE_V_SHIFT                                 0
 #define TPC0_CFG_TPC_EXECUTE_V_MASK                                  0x1
 
 /* TPC0_CFG_TPC_STALL */
 #define TPC0_CFG_TPC_STALL_V_SHIFT                                   0
 #define TPC0_CFG_TPC_STALL_V_MASK                                    0x1
 
 /* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */
 #define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT                    0
 #define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */
 #define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT                   0
 #define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_MSS_CONFIG */
 #define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT                            0
 #define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK                             0xF
 #define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT                            4
 #define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK                             0xF0
 #define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT              8
 #define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK               0x300
 #define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT                   10
 #define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK                    0x400
 
 /* TPC0_CFG_TPC_INTR_CAUSE */
 #define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT                          0
 #define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK                           0xFFFFFFFF
 
 /* TPC0_CFG_TPC_INTR_MASK */
 #define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT                            0
 #define TPC0_CFG_TPC_INTR_MASK_MASK_MASK                             0xFFFFFFFF
 
 /* TPC0_CFG_TSB_CONFIG */
 #define TPC0_CFG_TSB_CONFIG_TSB_AGU_MAX_CREDIT_SHIFT                 0
 #define TPC0_CFG_TSB_CONFIG_TSB_AGU_MAX_CREDIT_MASK                  0x1F
 #define TPC0_CFG_TSB_CONFIG_TSB_EU_MAX_CREDIT_SHIFT                  5
 #define TPC0_CFG_TSB_CONFIG_TSB_EU_MAX_CREDIT_MASK                   0x3E0
 #define TPC0_CFG_TSB_CONFIG_MAX_OUTSTANDING_SHIFT                    10
 #define TPC0_CFG_TSB_CONFIG_MAX_OUTSTANDING_MASK                     0xFFC00
 #define TPC0_CFG_TSB_CONFIG_MAX_SIZE_SHIFT                           20
 #define TPC0_CFG_TSB_CONFIG_MAX_SIZE_MASK                            0x3FF00000
 
 /* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */
 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */
 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT                  0
 #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */
 #define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT                   0
 #define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK                    0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT           0
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK            0x3
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT      8
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK       0x1F00
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT            16
 #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK             0x70000
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT                      0
 #define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */
 #define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT                    0
 #define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK                     0xFFFFFFFF
 
 /* TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET */
 #define TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET_V_SHIFT               0
 #define TPC0_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET_V_MASK                0xFFFFFFFF
 
 /* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */
 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT                  0
 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK                   0xFFFFFFFF
 
 /* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */
 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT                 0
 #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK                  0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_BASE_DIM_0 */
 #define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_SIZE_DIM_0 */
 #define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_BASE_DIM_1 */
 #define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_SIZE_DIM_1 */
 #define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_BASE_DIM_2 */
 #define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_SIZE_DIM_2 */
 #define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_BASE_DIM_3 */
 #define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_SIZE_DIM_3 */
 #define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_BASE_DIM_4 */
 #define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_TID_SIZE_DIM_4 */
 #define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT                           0
 #define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK                            0xFFFFFFFF
 
 /* TPC0_CFG_QM_SRF */
 #define TPC0_CFG_QM_SRF_V_SHIFT                                      0
 #define TPC0_CFG_QM_SRF_V_MASK                                       0xFFFFFFFF
 
 /* TPC0_CFG_QM_KERNEL_CONFIG */
 #define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT                    0
 #define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK                     0x1
 #define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT                 1
 #define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK                  0x2
 #define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT               8
 #define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK                0x3F00
 
 /* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */
 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT         0
 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK          0xFFFF
 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_SHIFT      16
 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_ADDRESS_OFFSET_MASK       0x7FFF0000
 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT           31
 #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK            0x80000000
 
 /* TPC0_CFG_ARUSER */
 #define TPC0_CFG_ARUSER_ASID_SHIFT                                   0
 #define TPC0_CFG_ARUSER_ASID_MASK                                    0x3FF
 #define TPC0_CFG_ARUSER_MMBP_SHIFT                                   10
 #define TPC0_CFG_ARUSER_MMBP_MASK                                    0x400
 #define TPC0_CFG_ARUSER_V_SHIFT                                      11
 #define TPC0_CFG_ARUSER_V_MASK                                       0xFFFFF800
 
 /* TPC0_CFG_AWUSER */
 #define TPC0_CFG_AWUSER_ASID_SHIFT                                   0
 #define TPC0_CFG_AWUSER_ASID_MASK                                    0x3FF
 #define TPC0_CFG_AWUSER_MMBP_SHIFT                                   10
 #define TPC0_CFG_AWUSER_MMBP_MASK                                    0x400
 #define TPC0_CFG_AWUSER_V_SHIFT                                      11
 #define TPC0_CFG_AWUSER_V_MASK                                       0xFFFFF800
 
 /* TPC0_CFG_FUNC_MBIST_CNTRL */
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT                  0
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK                   0x1
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT                   1
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK                    0x2
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT                 2
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK                  0x4
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT                 16
 #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK                  0x3FF0000
 
 /* TPC0_CFG_FUNC_MBIST_PAT */
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT            0
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK             0x3
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT             2
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK              0xC
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT            4
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK             0x30
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT             6
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK              0xC0
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT            8
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK             0x300
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT             10
 #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK              0xC00
 
 /* TPC0_CFG_FUNC_MBIST_MEM */
 #define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT                       0
 #define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK                        0x7FF
 #define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT                     12
 #define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK                      0x7000
 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT               16
 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK                0x7FF0000
 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT            28
 #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK             0x70000000
 
 #endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */

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