Back to home page

OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2016-2018 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007 
0008 /************************************
0009  ** This is an auto-generated file **
0010  **       DO NOT EDIT BELOW        **
0011  ************************************/
0012 
0013 #ifndef ASIC_REG_PSOC_SPI_REGS_H_
0014 #define ASIC_REG_PSOC_SPI_REGS_H_
0015 
0016 /*
0017  *****************************************
0018  *   PSOC_SPI (Prototype: SPI)
0019  *****************************************
0020  */
0021 
0022 #define mmPSOC_SPI_CTRLR0                                            0xC43000
0023 
0024 #define mmPSOC_SPI_CTRLR1                                            0xC43004
0025 
0026 #define mmPSOC_SPI_SSIENR                                            0xC43008
0027 
0028 #define mmPSOC_SPI_MWCR                                              0xC4300C
0029 
0030 #define mmPSOC_SPI_SER                                               0xC43010
0031 
0032 #define mmPSOC_SPI_BAUDR                                             0xC43014
0033 
0034 #define mmPSOC_SPI_TXFTLR                                            0xC43018
0035 
0036 #define mmPSOC_SPI_RXFTLR                                            0xC4301C
0037 
0038 #define mmPSOC_SPI_TXFLR                                             0xC43020
0039 
0040 #define mmPSOC_SPI_RXFLR                                             0xC43024
0041 
0042 #define mmPSOC_SPI_SR                                                0xC43028
0043 
0044 #define mmPSOC_SPI_IMR                                               0xC4302C
0045 
0046 #define mmPSOC_SPI_ISR                                               0xC43030
0047 
0048 #define mmPSOC_SPI_RISR                                              0xC43034
0049 
0050 #define mmPSOC_SPI_TXOICR                                            0xC43038
0051 
0052 #define mmPSOC_SPI_RXOICR                                            0xC4303C
0053 
0054 #define mmPSOC_SPI_RXUICR                                            0xC43040
0055 
0056 #define mmPSOC_SPI_MSTICR                                            0xC43044
0057 
0058 #define mmPSOC_SPI_ICR                                               0xC43048
0059 
0060 #define mmPSOC_SPI_IDR                                               0xC43058
0061 
0062 #define mmPSOC_SPI_SSI_VERSION_ID                                    0xC4305C
0063 
0064 #define mmPSOC_SPI_DR0                                               0xC43060
0065 
0066 #define mmPSOC_SPI_DR1                                               0xC43064
0067 
0068 #define mmPSOC_SPI_DR2                                               0xC43068
0069 
0070 #define mmPSOC_SPI_DR3                                               0xC4306C
0071 
0072 #define mmPSOC_SPI_DR4                                               0xC43070
0073 
0074 #define mmPSOC_SPI_DR5                                               0xC43074
0075 
0076 #define mmPSOC_SPI_DR6                                               0xC43078
0077 
0078 #define mmPSOC_SPI_DR7                                               0xC4307C
0079 
0080 #define mmPSOC_SPI_DR8                                               0xC43080
0081 
0082 #define mmPSOC_SPI_DR9                                               0xC43084
0083 
0084 #define mmPSOC_SPI_DR10                                              0xC43088
0085 
0086 #define mmPSOC_SPI_DR11                                              0xC4308C
0087 
0088 #define mmPSOC_SPI_DR12                                              0xC43090
0089 
0090 #define mmPSOC_SPI_DR13                                              0xC43094
0091 
0092 #define mmPSOC_SPI_DR14                                              0xC43098
0093 
0094 #define mmPSOC_SPI_DR15                                              0xC4309C
0095 
0096 #define mmPSOC_SPI_DR16                                              0xC430A0
0097 
0098 #define mmPSOC_SPI_DR17                                              0xC430A4
0099 
0100 #define mmPSOC_SPI_DR18                                              0xC430A8
0101 
0102 #define mmPSOC_SPI_DR19                                              0xC430AC
0103 
0104 #define mmPSOC_SPI_DR20                                              0xC430B0
0105 
0106 #define mmPSOC_SPI_DR21                                              0xC430B4
0107 
0108 #define mmPSOC_SPI_DR22                                              0xC430B8
0109 
0110 #define mmPSOC_SPI_DR23                                              0xC430BC
0111 
0112 #define mmPSOC_SPI_DR24                                              0xC430C0
0113 
0114 #define mmPSOC_SPI_DR25                                              0xC430C4
0115 
0116 #define mmPSOC_SPI_DR26                                              0xC430C8
0117 
0118 #define mmPSOC_SPI_DR27                                              0xC430CC
0119 
0120 #define mmPSOC_SPI_DR28                                              0xC430D0
0121 
0122 #define mmPSOC_SPI_DR29                                              0xC430D4
0123 
0124 #define mmPSOC_SPI_DR30                                              0xC430D8
0125 
0126 #define mmPSOC_SPI_DR31                                              0xC430DC
0127 
0128 #define mmPSOC_SPI_DR32                                              0xC430E0
0129 
0130 #define mmPSOC_SPI_DR33                                              0xC430E4
0131 
0132 #define mmPSOC_SPI_DR34                                              0xC430E8
0133 
0134 #define mmPSOC_SPI_DR35                                              0xC430EC
0135 
0136 #define mmPSOC_SPI_RX_SAMPLE_DLY                                     0xC430F0
0137 
0138 #define mmPSOC_SPI_RSVD_1                                            0xC430F8
0139 
0140 #define mmPSOC_SPI_RSVD_2                                            0xC430FC
0141 
0142 #endif /* ASIC_REG_PSOC_SPI_REGS_H_ */