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0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2016-2018 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007 
0008 /************************************
0009  ** This is an auto-generated file **
0010  **       DO NOT EDIT BELOW        **
0011  ************************************/
0012 
0013 #ifndef ASIC_REG_PSOC_MME_PLL_REGS_H_
0014 #define ASIC_REG_PSOC_MME_PLL_REGS_H_
0015 
0016 /*
0017  *****************************************
0018  *   PSOC_MME_PLL (Prototype: PLL)
0019  *****************************************
0020  */
0021 
0022 #define mmPSOC_MME_PLL_NR                                            0xC71100
0023 
0024 #define mmPSOC_MME_PLL_NF                                            0xC71104
0025 
0026 #define mmPSOC_MME_PLL_OD                                            0xC71108
0027 
0028 #define mmPSOC_MME_PLL_NB                                            0xC7110C
0029 
0030 #define mmPSOC_MME_PLL_CFG                                           0xC71110
0031 
0032 #define mmPSOC_MME_PLL_LOSE_MASK                                     0xC71120
0033 
0034 #define mmPSOC_MME_PLL_LOCK_INTR                                     0xC71128
0035 
0036 #define mmPSOC_MME_PLL_LOCK_BYPASS                                   0xC7112C
0037 
0038 #define mmPSOC_MME_PLL_DATA_CHNG                                     0xC71130
0039 
0040 #define mmPSOC_MME_PLL_RST                                           0xC71134
0041 
0042 #define mmPSOC_MME_PLL_SLIP_WD_CNTR                                  0xC71150
0043 
0044 #define mmPSOC_MME_PLL_DIV_FACTOR_0                                  0xC71200
0045 
0046 #define mmPSOC_MME_PLL_DIV_FACTOR_1                                  0xC71204
0047 
0048 #define mmPSOC_MME_PLL_DIV_FACTOR_2                                  0xC71208
0049 
0050 #define mmPSOC_MME_PLL_DIV_FACTOR_3                                  0xC7120C
0051 
0052 #define mmPSOC_MME_PLL_DIV_FACTOR_CMD_0                              0xC71220
0053 
0054 #define mmPSOC_MME_PLL_DIV_FACTOR_CMD_1                              0xC71224
0055 
0056 #define mmPSOC_MME_PLL_DIV_FACTOR_CMD_2                              0xC71228
0057 
0058 #define mmPSOC_MME_PLL_DIV_FACTOR_CMD_3                              0xC7122C
0059 
0060 #define mmPSOC_MME_PLL_DIV_SEL_0                                     0xC71280
0061 
0062 #define mmPSOC_MME_PLL_DIV_SEL_1                                     0xC71284
0063 
0064 #define mmPSOC_MME_PLL_DIV_SEL_2                                     0xC71288
0065 
0066 #define mmPSOC_MME_PLL_DIV_SEL_3                                     0xC7128C
0067 
0068 #define mmPSOC_MME_PLL_DIV_EN_0                                      0xC712A0
0069 
0070 #define mmPSOC_MME_PLL_DIV_EN_1                                      0xC712A4
0071 
0072 #define mmPSOC_MME_PLL_DIV_EN_2                                      0xC712A8
0073 
0074 #define mmPSOC_MME_PLL_DIV_EN_3                                      0xC712AC
0075 
0076 #define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_0                             0xC712C0
0077 
0078 #define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_1                             0xC712C4
0079 
0080 #define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_2                             0xC712C8
0081 
0082 #define mmPSOC_MME_PLL_DIV_FACTOR_BUSY_3                             0xC712CC
0083 
0084 #define mmPSOC_MME_PLL_CLK_GATER                                     0xC71300
0085 
0086 #define mmPSOC_MME_PLL_CLK_RLX_0                                     0xC71310
0087 
0088 #define mmPSOC_MME_PLL_CLK_RLX_1                                     0xC71314
0089 
0090 #define mmPSOC_MME_PLL_CLK_RLX_2                                     0xC71318
0091 
0092 #define mmPSOC_MME_PLL_CLK_RLX_3                                     0xC7131C
0093 
0094 #define mmPSOC_MME_PLL_REF_CNTR_PERIOD                               0xC71400
0095 
0096 #define mmPSOC_MME_PLL_REF_LOW_THRESHOLD                             0xC71410
0097 
0098 #define mmPSOC_MME_PLL_REF_HIGH_THRESHOLD                            0xC71420
0099 
0100 #define mmPSOC_MME_PLL_PLL_NOT_STABLE                                0xC71430
0101 
0102 #define mmPSOC_MME_PLL_FREQ_CALC_EN                                  0xC71440
0103 
0104 #endif /* ASIC_REG_PSOC_MME_PLL_REGS_H_ */