0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013 #ifndef ASIC_REG_MMU_REGS_H_
0014 #define ASIC_REG_MMU_REGS_H_
0015
0016
0017
0018
0019
0020
0021
0022 #define mmMMU_INPUT_FIFO_THRESHOLD 0x480000
0023
0024 #define mmMMU_MMU_ENABLE 0x48000C
0025
0026 #define mmMMU_FORCE_ORDERING 0x480010
0027
0028 #define mmMMU_FEATURE_ENABLE 0x480014
0029
0030 #define mmMMU_VA_ORDERING_MASK_31_7 0x480018
0031
0032 #define mmMMU_VA_ORDERING_MASK_49_32 0x48001C
0033
0034 #define mmMMU_LOG2_DDR_SIZE 0x480020
0035
0036 #define mmMMU_SCRAMBLER 0x480024
0037
0038 #define mmMMU_MEM_INIT_BUSY 0x480028
0039
0040 #define mmMMU_SPI_MASK 0x48002C
0041
0042 #define mmMMU_SPI_CAUSE 0x480030
0043
0044 #define mmMMU_PAGE_ERROR_CAPTURE 0x480034
0045
0046 #define mmMMU_PAGE_ERROR_CAPTURE_VA 0x480038
0047
0048 #define mmMMU_ACCESS_ERROR_CAPTURE 0x48003C
0049
0050 #define mmMMU_ACCESS_ERROR_CAPTURE_VA 0x480040
0051
0052 #endif