goya/asic_reg/mmu_masks.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2016-2018 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007
0008 /************************************
0009  ** This is an auto-generated file **
0010  **       DO NOT EDIT BELOW        **
0011  ************************************/
0012
0013 #ifndef ASIC_REG_MMU_MASKS_H_
0014 #define ASIC_REG_MMU_MASKS_H_
0015
0016 /*
0017  *****************************************
0018  *   MMU (Prototype: MMU)
0019  *****************************************
0020  */
0021
0022 /* MMU_INPUT_FIFO_THRESHOLD */
0023 #define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT                           0
0024 #define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK                            0x7
0025 #define MMU_INPUT_FIFO_THRESHOLD_PSOC_SHIFT                          4
0026 #define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK                           0x70
0027 #define MMU_INPUT_FIFO_THRESHOLD_DMA_SHIFT                           8
0028 #define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK                            0x700
0029 #define MMU_INPUT_FIFO_THRESHOLD_CPU_SHIFT                           12
0030 #define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK                            0x7000
0031 #define MMU_INPUT_FIFO_THRESHOLD_MME_SHIFT                           16
0032 #define MMU_INPUT_FIFO_THRESHOLD_MME_MASK                            0x70000
0033 #define MMU_INPUT_FIFO_THRESHOLD_TPC_SHIFT                           20
0034 #define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK                            0x700000
0035 #define MMU_INPUT_FIFO_THRESHOLD_OTHER_SHIFT                         24
0036 #define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK                          0x7000000
0037
0038 /* MMU_MMU_ENABLE */
0039 #define MMU_MMU_ENABLE_R_SHIFT                                       0
0040 #define MMU_MMU_ENABLE_R_MASK                                        0x1
0041
0042 /* MMU_FORCE_ORDERING */
0043 #define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_SHIFT                   0
0044 #define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_MASK                    0x1
0045 #define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_SHIFT                  1
0046 #define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_MASK                   0x2
0047 #define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_SHIFT                   2
0048 #define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_MASK                    0x4
0049 #define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_SHIFT                   3
0050 #define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_MASK                    0x8
0051 #define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_SHIFT                   4
0052 #define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_MASK                    0x10
0053 #define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_SHIFT                   5
0054 #define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_MASK                    0x20
0055 #define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_SHIFT               6
0056 #define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_MASK                0x40
0057 #define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_SHIFT                 8
0058 #define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_MASK                  0x100
0059 #define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_SHIFT                9
0060 #define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_MASK                 0x200
0061 #define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_SHIFT                 10
0062 #define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_MASK                  0x400
0063 #define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_SHIFT                 11
0064 #define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_MASK                  0x800
0065 #define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_SHIFT                 12
0066 #define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_MASK                  0x1000
0067 #define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_SHIFT                 13
0068 #define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_MASK                  0x2000
0069 #define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_SHIFT             14
0070 #define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_MASK              0x4000
0071
0072 /* MMU_FEATURE_ENABLE */
0073 #define MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT                      0
0074 #define MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK                       0x1
0075 #define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT                     1
0076 #define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK                      0x2
0077 #define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT                       2
0078 #define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK                        0x4
0079 #define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT                     3
0080 #define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK                      0x8
0081 #define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT             4
0082 #define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK              0x10
0083 #define MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT                        5
0084 #define MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK                         0x20
0085
0086 /* MMU_VA_ORDERING_MASK_31_7 */
0087 #define MMU_VA_ORDERING_MASK_31_7_R_SHIFT                            0
0088 #define MMU_VA_ORDERING_MASK_31_7_R_MASK                             0x1FFFFFF
0089
0090 /* MMU_VA_ORDERING_MASK_49_32 */
0091 #define MMU_VA_ORDERING_MASK_49_32_R_SHIFT                           0
0092 #define MMU_VA_ORDERING_MASK_49_32_R_MASK                            0x3FFFF
0093
0094 /* MMU_LOG2_DDR_SIZE */
0095 #define MMU_LOG2_DDR_SIZE_R_SHIFT                                    0
0096 #define MMU_LOG2_DDR_SIZE_R_MASK                                     0xFF
0097
0098 /* MMU_SCRAMBLER */
0099 #define MMU_SCRAMBLER_ADDR_BIT_SHIFT                                 0
0100 #define MMU_SCRAMBLER_ADDR_BIT_MASK                                  0x3F
0101 #define MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT                            6
0102 #define MMU_SCRAMBLER_SINGLE_DDR_EN_MASK                             0x40
0103 #define MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT                            7
0104 #define MMU_SCRAMBLER_SINGLE_DDR_ID_MASK                             0x80
0105
0106 /* MMU_MEM_INIT_BUSY */
0107 #define MMU_MEM_INIT_BUSY_DATA_SHIFT                                 0
0108 #define MMU_MEM_INIT_BUSY_DATA_MASK                                  0x3
0109 #define MMU_MEM_INIT_BUSY_OBI0_SHIFT                                 2
0110 #define MMU_MEM_INIT_BUSY_OBI0_MASK                                  0x4
0111 #define MMU_MEM_INIT_BUSY_OBI1_SHIFT                                 3
0112 #define MMU_MEM_INIT_BUSY_OBI1_MASK                                  0x8
0113
0114 /* MMU_SPI_MASK */
0115 #define MMU_SPI_MASK_R_SHIFT                                         0
0116 #define MMU_SPI_MASK_R_MASK                                          0xFF
0117
0118 /* MMU_SPI_CAUSE */
0119 #define MMU_SPI_CAUSE_R_SHIFT                                        0
0120 #define MMU_SPI_CAUSE_R_MASK                                         0xFF
0121
0122 /* MMU_PAGE_ERROR_CAPTURE */
0123 #define MMU_PAGE_ERROR_CAPTURE_VA_49_32_SHIFT                        0
0124 #define MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK                         0x3FFFF
0125 #define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_SHIFT                     18
0126 #define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK                      0x40000
0127
0128 /* MMU_PAGE_ERROR_CAPTURE_VA */
0129 #define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT                      0
0130 #define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK                       0xFFFFFFFF
0131
0132 /* MMU_ACCESS_ERROR_CAPTURE */
0133 #define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_SHIFT                      0
0134 #define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_MASK                       0x3FFFF
0135 #define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_SHIFT                   18
0136 #define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK                    0x40000
0137
0138 /* MMU_ACCESS_ERROR_CAPTURE_VA */
0139 #define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT                    0
0140 #define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK                     0xFFFFFFFF
0141
0142 #endif /* ASIC_REG_MMU_MASKS_H_ */