OSCL-LXR linux-6.0.1/​drivers/​misc/​habanalabs/​include/​goya/​asic_reg/​mme5_rtr_regs.h	Source navigation Diff markup Identifier search General search
	Version: linux-6.0.1 spark-3.0.0 hadoop-3.2.0-src hadoop-3.3.0-src spark-2.4.7 linux-4.15.13 hadoop-2.7.4-src Revert   Change

 /* SPDX-License-Identifier: GPL-2.0
  *
  * Copyright 2016-2018 HabanaLabs, Ltd.
  * All Rights Reserved.
  *
  */
 
 /************************************
  ** This is an auto-generated file **
  **       DO NOT EDIT BELOW        **
  ************************************/
 
 #ifndef ASIC_REG_MME5_RTR_REGS_H_
 #define ASIC_REG_MME5_RTR_REGS_H_
 
 /*
  *****************************************
  *   MME5_RTR (Prototype: MME_RTR)
  *****************************************
  */
 
 #define mmMME5_RTR_HBW_RD_RQ_E_ARB                                   0x140100
 
 #define mmMME5_RTR_HBW_RD_RQ_W_ARB                                   0x140104
 
 #define mmMME5_RTR_HBW_RD_RQ_N_ARB                                   0x140108
 
 #define mmMME5_RTR_HBW_RD_RQ_S_ARB                                   0x14010C
 
 #define mmMME5_RTR_HBW_RD_RQ_L_ARB                                   0x140110
 
 #define mmMME5_RTR_HBW_E_ARB_MAX                                     0x140120
 
 #define mmMME5_RTR_HBW_W_ARB_MAX                                     0x140124
 
 #define mmMME5_RTR_HBW_N_ARB_MAX                                     0x140128
 
 #define mmMME5_RTR_HBW_S_ARB_MAX                                     0x14012C
 
 #define mmMME5_RTR_HBW_L_ARB_MAX                                     0x140130
 
 #define mmMME5_RTR_HBW_RD_RS_MAX_CREDIT                              0x140140
 
 #define mmMME5_RTR_HBW_WR_RQ_MAX_CREDIT                              0x140144
 
 #define mmMME5_RTR_HBW_RD_RQ_MAX_CREDIT                              0x140148
 
 #define mmMME5_RTR_HBW_RD_RS_E_ARB                                   0x140150
 
 #define mmMME5_RTR_HBW_RD_RS_W_ARB                                   0x140154
 
 #define mmMME5_RTR_HBW_RD_RS_N_ARB                                   0x140158
 
 #define mmMME5_RTR_HBW_RD_RS_S_ARB                                   0x14015C
 
 #define mmMME5_RTR_HBW_RD_RS_L_ARB                                   0x140160
 
 #define mmMME5_RTR_HBW_WR_RQ_E_ARB                                   0x140170
 
 #define mmMME5_RTR_HBW_WR_RQ_W_ARB                                   0x140174
 
 #define mmMME5_RTR_HBW_WR_RQ_N_ARB                                   0x140178
 
 #define mmMME5_RTR_HBW_WR_RQ_S_ARB                                   0x14017C
 
 #define mmMME5_RTR_HBW_WR_RQ_L_ARB                                   0x140180
 
 #define mmMME5_RTR_HBW_WR_RS_E_ARB                                   0x140190
 
 #define mmMME5_RTR_HBW_WR_RS_W_ARB                                   0x140194
 
 #define mmMME5_RTR_HBW_WR_RS_N_ARB                                   0x140198
 
 #define mmMME5_RTR_HBW_WR_RS_S_ARB                                   0x14019C
 
 #define mmMME5_RTR_HBW_WR_RS_L_ARB                                   0x1401A0
 
 #define mmMME5_RTR_LBW_RD_RQ_E_ARB                                   0x140200
 
 #define mmMME5_RTR_LBW_RD_RQ_W_ARB                                   0x140204
 
 #define mmMME5_RTR_LBW_RD_RQ_N_ARB                                   0x140208
 
 #define mmMME5_RTR_LBW_RD_RQ_S_ARB                                   0x14020C
 
 #define mmMME5_RTR_LBW_RD_RQ_L_ARB                                   0x140210
 
 #define mmMME5_RTR_LBW_E_ARB_MAX                                     0x140220
 
 #define mmMME5_RTR_LBW_W_ARB_MAX                                     0x140224
 
 #define mmMME5_RTR_LBW_N_ARB_MAX                                     0x140228
 
 #define mmMME5_RTR_LBW_S_ARB_MAX                                     0x14022C
 
 #define mmMME5_RTR_LBW_L_ARB_MAX                                     0x140230
 
 #define mmMME5_RTR_LBW_SRAM_MAX_CREDIT                               0x140240
 
 #define mmMME5_RTR_LBW_RD_RS_E_ARB                                   0x140250
 
 #define mmMME5_RTR_LBW_RD_RS_W_ARB                                   0x140254
 
 #define mmMME5_RTR_LBW_RD_RS_N_ARB                                   0x140258
 
 #define mmMME5_RTR_LBW_RD_RS_S_ARB                                   0x14025C
 
 #define mmMME5_RTR_LBW_RD_RS_L_ARB                                   0x140260
 
 #define mmMME5_RTR_LBW_WR_RQ_E_ARB                                   0x140270
 
 #define mmMME5_RTR_LBW_WR_RQ_W_ARB                                   0x140274
 
 #define mmMME5_RTR_LBW_WR_RQ_N_ARB                                   0x140278
 
 #define mmMME5_RTR_LBW_WR_RQ_S_ARB                                   0x14027C
 
 #define mmMME5_RTR_LBW_WR_RQ_L_ARB                                   0x140280
 
 #define mmMME5_RTR_LBW_WR_RS_E_ARB                                   0x140290
 
 #define mmMME5_RTR_LBW_WR_RS_W_ARB                                   0x140294
 
 #define mmMME5_RTR_LBW_WR_RS_N_ARB                                   0x140298
 
 #define mmMME5_RTR_LBW_WR_RS_S_ARB                                   0x14029C
 
 #define mmMME5_RTR_LBW_WR_RS_L_ARB                                   0x1402A0
 
 #define mmMME5_RTR_DBG_E_ARB                                         0x140300
 
 #define mmMME5_RTR_DBG_W_ARB                                         0x140304
 
 #define mmMME5_RTR_DBG_N_ARB                                         0x140308
 
 #define mmMME5_RTR_DBG_S_ARB                                         0x14030C
 
 #define mmMME5_RTR_DBG_L_ARB                                         0x140310
 
 #define mmMME5_RTR_DBG_E_ARB_MAX                                     0x140320
 
 #define mmMME5_RTR_DBG_W_ARB_MAX                                     0x140324
 
 #define mmMME5_RTR_DBG_N_ARB_MAX                                     0x140328
 
 #define mmMME5_RTR_DBG_S_ARB_MAX                                     0x14032C
 
 #define mmMME5_RTR_DBG_L_ARB_MAX                                     0x140330
 
 #define mmMME5_RTR_SPLIT_COEF_0                                      0x140400
 
 #define mmMME5_RTR_SPLIT_COEF_1                                      0x140404
 
 #define mmMME5_RTR_SPLIT_COEF_2                                      0x140408
 
 #define mmMME5_RTR_SPLIT_COEF_3                                      0x14040C
 
 #define mmMME5_RTR_SPLIT_COEF_4                                      0x140410
 
 #define mmMME5_RTR_SPLIT_COEF_5                                      0x140414
 
 #define mmMME5_RTR_SPLIT_COEF_6                                      0x140418
 
 #define mmMME5_RTR_SPLIT_COEF_7                                      0x14041C
 
 #define mmMME5_RTR_SPLIT_COEF_8                                      0x140420
 
 #define mmMME5_RTR_SPLIT_COEF_9                                      0x140424
 
 #define mmMME5_RTR_SPLIT_CFG                                         0x140440
 
 #define mmMME5_RTR_SPLIT_RD_SAT                                      0x140444
 
 #define mmMME5_RTR_SPLIT_RD_RST_TOKEN                                0x140448
 
 #define mmMME5_RTR_SPLIT_RD_TIMEOUT_0                                0x14044C
 
 #define mmMME5_RTR_SPLIT_RD_TIMEOUT_1                                0x140450
 
 #define mmMME5_RTR_SPLIT_WR_SAT                                      0x140454
 
 #define mmMME5_RTR_WPLIT_WR_TST_TOLEN                                0x140458
 
 #define mmMME5_RTR_SPLIT_WR_TIMEOUT_0                                0x14045C
 
 #define mmMME5_RTR_SPLIT_WR_TIMEOUT_1                                0x140460
 
 #define mmMME5_RTR_HBW_RANGE_HIT                                     0x140470
 
 #define mmMME5_RTR_HBW_RANGE_MASK_L_0                                0x140480
 
 #define mmMME5_RTR_HBW_RANGE_MASK_L_1                                0x140484
 
 #define mmMME5_RTR_HBW_RANGE_MASK_L_2                                0x140488
 
 #define mmMME5_RTR_HBW_RANGE_MASK_L_3                                0x14048C
 
 #define mmMME5_RTR_HBW_RANGE_MASK_L_4                                0x140490
 
 #define mmMME5_RTR_HBW_RANGE_MASK_L_5                                0x140494
 
 #define mmMME5_RTR_HBW_RANGE_MASK_L_6                                0x140498
 
 #define mmMME5_RTR_HBW_RANGE_MASK_L_7                                0x14049C
 
 #define mmMME5_RTR_HBW_RANGE_MASK_H_0                                0x1404A0
 
 #define mmMME5_RTR_HBW_RANGE_MASK_H_1                                0x1404A4
 
 #define mmMME5_RTR_HBW_RANGE_MASK_H_2                                0x1404A8
 
 #define mmMME5_RTR_HBW_RANGE_MASK_H_3                                0x1404AC
 
 #define mmMME5_RTR_HBW_RANGE_MASK_H_4                                0x1404B0
 
 #define mmMME5_RTR_HBW_RANGE_MASK_H_5                                0x1404B4
 
 #define mmMME5_RTR_HBW_RANGE_MASK_H_6                                0x1404B8
 
 #define mmMME5_RTR_HBW_RANGE_MASK_H_7                                0x1404BC
 
 #define mmMME5_RTR_HBW_RANGE_BASE_L_0                                0x1404C0
 
 #define mmMME5_RTR_HBW_RANGE_BASE_L_1                                0x1404C4
 
 #define mmMME5_RTR_HBW_RANGE_BASE_L_2                                0x1404C8
 
 #define mmMME5_RTR_HBW_RANGE_BASE_L_3                                0x1404CC
 
 #define mmMME5_RTR_HBW_RANGE_BASE_L_4                                0x1404D0
 
 #define mmMME5_RTR_HBW_RANGE_BASE_L_5                                0x1404D4
 
 #define mmMME5_RTR_HBW_RANGE_BASE_L_6                                0x1404D8
 
 #define mmMME5_RTR_HBW_RANGE_BASE_L_7                                0x1404DC
 
 #define mmMME5_RTR_HBW_RANGE_BASE_H_0                                0x1404E0
 
 #define mmMME5_RTR_HBW_RANGE_BASE_H_1                                0x1404E4
 
 #define mmMME5_RTR_HBW_RANGE_BASE_H_2                                0x1404E8
 
 #define mmMME5_RTR_HBW_RANGE_BASE_H_3                                0x1404EC
 
 #define mmMME5_RTR_HBW_RANGE_BASE_H_4                                0x1404F0
 
 #define mmMME5_RTR_HBW_RANGE_BASE_H_5                                0x1404F4
 
 #define mmMME5_RTR_HBW_RANGE_BASE_H_6                                0x1404F8
 
 #define mmMME5_RTR_HBW_RANGE_BASE_H_7                                0x1404FC
 
 #define mmMME5_RTR_LBW_RANGE_HIT                                     0x140500
 
 #define mmMME5_RTR_LBW_RANGE_MASK_0                                  0x140510
 
 #define mmMME5_RTR_LBW_RANGE_MASK_1                                  0x140514
 
 #define mmMME5_RTR_LBW_RANGE_MASK_2                                  0x140518
 
 #define mmMME5_RTR_LBW_RANGE_MASK_3                                  0x14051C
 
 #define mmMME5_RTR_LBW_RANGE_MASK_4                                  0x140520
 
 #define mmMME5_RTR_LBW_RANGE_MASK_5                                  0x140524
 
 #define mmMME5_RTR_LBW_RANGE_MASK_6                                  0x140528
 
 #define mmMME5_RTR_LBW_RANGE_MASK_7                                  0x14052C
 
 #define mmMME5_RTR_LBW_RANGE_MASK_8                                  0x140530
 
 #define mmMME5_RTR_LBW_RANGE_MASK_9                                  0x140534
 
 #define mmMME5_RTR_LBW_RANGE_MASK_10                                 0x140538
 
 #define mmMME5_RTR_LBW_RANGE_MASK_11                                 0x14053C
 
 #define mmMME5_RTR_LBW_RANGE_MASK_12                                 0x140540
 
 #define mmMME5_RTR_LBW_RANGE_MASK_13                                 0x140544
 
 #define mmMME5_RTR_LBW_RANGE_MASK_14                                 0x140548
 
 #define mmMME5_RTR_LBW_RANGE_MASK_15                                 0x14054C
 
 #define mmMME5_RTR_LBW_RANGE_BASE_0                                  0x140550
 
 #define mmMME5_RTR_LBW_RANGE_BASE_1                                  0x140554
 
 #define mmMME5_RTR_LBW_RANGE_BASE_2                                  0x140558
 
 #define mmMME5_RTR_LBW_RANGE_BASE_3                                  0x14055C
 
 #define mmMME5_RTR_LBW_RANGE_BASE_4                                  0x140560
 
 #define mmMME5_RTR_LBW_RANGE_BASE_5                                  0x140564
 
 #define mmMME5_RTR_LBW_RANGE_BASE_6                                  0x140568
 
 #define mmMME5_RTR_LBW_RANGE_BASE_7                                  0x14056C
 
 #define mmMME5_RTR_LBW_RANGE_BASE_8                                  0x140570
 
 #define mmMME5_RTR_LBW_RANGE_BASE_9                                  0x140574
 
 #define mmMME5_RTR_LBW_RANGE_BASE_10                                 0x140578
 
 #define mmMME5_RTR_LBW_RANGE_BASE_11                                 0x14057C
 
 #define mmMME5_RTR_LBW_RANGE_BASE_12                                 0x140580
 
 #define mmMME5_RTR_LBW_RANGE_BASE_13                                 0x140584
 
 #define mmMME5_RTR_LBW_RANGE_BASE_14                                 0x140588
 
 #define mmMME5_RTR_LBW_RANGE_BASE_15                                 0x14058C
 
 #define mmMME5_RTR_RGLTR                                             0x140590
 
 #define mmMME5_RTR_RGLTR_WR_RESULT                                   0x140594
 
 #define mmMME5_RTR_RGLTR_RD_RESULT                                   0x140598
 
 #define mmMME5_RTR_SCRAMB_EN                                         0x140600
 
 #define mmMME5_RTR_NON_LIN_SCRAMB                                    0x140604
 
 #endif /* ASIC_REG_MME5_RTR_REGS_H_ */

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