OSCL-LXR linux-6.0.1/​drivers/​misc/​habanalabs/​include/​goya/​asic_reg/​mme3_rtr_regs.h	Source navigation Diff markup Identifier search General search
	Version: linux-6.0.1 spark-3.0.0 hadoop-3.2.0-src hadoop-3.3.0-src spark-2.4.7 linux-4.15.13 hadoop-2.7.4-src Revert   Change

 /* SPDX-License-Identifier: GPL-2.0
  *
  * Copyright 2016-2018 HabanaLabs, Ltd.
  * All Rights Reserved.
  *
  */
 
 /************************************
  ** This is an auto-generated file **
  **       DO NOT EDIT BELOW        **
  ************************************/
 
 #ifndef ASIC_REG_MME3_RTR_REGS_H_
 #define ASIC_REG_MME3_RTR_REGS_H_
 
 /*
  *****************************************
  *   MME3_RTR (Prototype: MME_RTR)
  *****************************************
  */
 
 #define mmMME3_RTR_HBW_RD_RQ_E_ARB                                   0xC0100
 
 #define mmMME3_RTR_HBW_RD_RQ_W_ARB                                   0xC0104
 
 #define mmMME3_RTR_HBW_RD_RQ_N_ARB                                   0xC0108
 
 #define mmMME3_RTR_HBW_RD_RQ_S_ARB                                   0xC010C
 
 #define mmMME3_RTR_HBW_RD_RQ_L_ARB                                   0xC0110
 
 #define mmMME3_RTR_HBW_E_ARB_MAX                                     0xC0120
 
 #define mmMME3_RTR_HBW_W_ARB_MAX                                     0xC0124
 
 #define mmMME3_RTR_HBW_N_ARB_MAX                                     0xC0128
 
 #define mmMME3_RTR_HBW_S_ARB_MAX                                     0xC012C
 
 #define mmMME3_RTR_HBW_L_ARB_MAX                                     0xC0130
 
 #define mmMME3_RTR_HBW_RD_RS_MAX_CREDIT                              0xC0140
 
 #define mmMME3_RTR_HBW_WR_RQ_MAX_CREDIT                              0xC0144
 
 #define mmMME3_RTR_HBW_RD_RQ_MAX_CREDIT                              0xC0148
 
 #define mmMME3_RTR_HBW_RD_RS_E_ARB                                   0xC0150
 
 #define mmMME3_RTR_HBW_RD_RS_W_ARB                                   0xC0154
 
 #define mmMME3_RTR_HBW_RD_RS_N_ARB                                   0xC0158
 
 #define mmMME3_RTR_HBW_RD_RS_S_ARB                                   0xC015C
 
 #define mmMME3_RTR_HBW_RD_RS_L_ARB                                   0xC0160
 
 #define mmMME3_RTR_HBW_WR_RQ_E_ARB                                   0xC0170
 
 #define mmMME3_RTR_HBW_WR_RQ_W_ARB                                   0xC0174
 
 #define mmMME3_RTR_HBW_WR_RQ_N_ARB                                   0xC0178
 
 #define mmMME3_RTR_HBW_WR_RQ_S_ARB                                   0xC017C
 
 #define mmMME3_RTR_HBW_WR_RQ_L_ARB                                   0xC0180
 
 #define mmMME3_RTR_HBW_WR_RS_E_ARB                                   0xC0190
 
 #define mmMME3_RTR_HBW_WR_RS_W_ARB                                   0xC0194
 
 #define mmMME3_RTR_HBW_WR_RS_N_ARB                                   0xC0198
 
 #define mmMME3_RTR_HBW_WR_RS_S_ARB                                   0xC019C
 
 #define mmMME3_RTR_HBW_WR_RS_L_ARB                                   0xC01A0
 
 #define mmMME3_RTR_LBW_RD_RQ_E_ARB                                   0xC0200
 
 #define mmMME3_RTR_LBW_RD_RQ_W_ARB                                   0xC0204
 
 #define mmMME3_RTR_LBW_RD_RQ_N_ARB                                   0xC0208
 
 #define mmMME3_RTR_LBW_RD_RQ_S_ARB                                   0xC020C
 
 #define mmMME3_RTR_LBW_RD_RQ_L_ARB                                   0xC0210
 
 #define mmMME3_RTR_LBW_E_ARB_MAX                                     0xC0220
 
 #define mmMME3_RTR_LBW_W_ARB_MAX                                     0xC0224
 
 #define mmMME3_RTR_LBW_N_ARB_MAX                                     0xC0228
 
 #define mmMME3_RTR_LBW_S_ARB_MAX                                     0xC022C
 
 #define mmMME3_RTR_LBW_L_ARB_MAX                                     0xC0230
 
 #define mmMME3_RTR_LBW_SRAM_MAX_CREDIT                               0xC0240
 
 #define mmMME3_RTR_LBW_RD_RS_E_ARB                                   0xC0250
 
 #define mmMME3_RTR_LBW_RD_RS_W_ARB                                   0xC0254
 
 #define mmMME3_RTR_LBW_RD_RS_N_ARB                                   0xC0258
 
 #define mmMME3_RTR_LBW_RD_RS_S_ARB                                   0xC025C
 
 #define mmMME3_RTR_LBW_RD_RS_L_ARB                                   0xC0260
 
 #define mmMME3_RTR_LBW_WR_RQ_E_ARB                                   0xC0270
 
 #define mmMME3_RTR_LBW_WR_RQ_W_ARB                                   0xC0274
 
 #define mmMME3_RTR_LBW_WR_RQ_N_ARB                                   0xC0278
 
 #define mmMME3_RTR_LBW_WR_RQ_S_ARB                                   0xC027C
 
 #define mmMME3_RTR_LBW_WR_RQ_L_ARB                                   0xC0280
 
 #define mmMME3_RTR_LBW_WR_RS_E_ARB                                   0xC0290
 
 #define mmMME3_RTR_LBW_WR_RS_W_ARB                                   0xC0294
 
 #define mmMME3_RTR_LBW_WR_RS_N_ARB                                   0xC0298
 
 #define mmMME3_RTR_LBW_WR_RS_S_ARB                                   0xC029C
 
 #define mmMME3_RTR_LBW_WR_RS_L_ARB                                   0xC02A0
 
 #define mmMME3_RTR_DBG_E_ARB                                         0xC0300
 
 #define mmMME3_RTR_DBG_W_ARB                                         0xC0304
 
 #define mmMME3_RTR_DBG_N_ARB                                         0xC0308
 
 #define mmMME3_RTR_DBG_S_ARB                                         0xC030C
 
 #define mmMME3_RTR_DBG_L_ARB                                         0xC0310
 
 #define mmMME3_RTR_DBG_E_ARB_MAX                                     0xC0320
 
 #define mmMME3_RTR_DBG_W_ARB_MAX                                     0xC0324
 
 #define mmMME3_RTR_DBG_N_ARB_MAX                                     0xC0328
 
 #define mmMME3_RTR_DBG_S_ARB_MAX                                     0xC032C
 
 #define mmMME3_RTR_DBG_L_ARB_MAX                                     0xC0330
 
 #define mmMME3_RTR_SPLIT_COEF_0                                      0xC0400
 
 #define mmMME3_RTR_SPLIT_COEF_1                                      0xC0404
 
 #define mmMME3_RTR_SPLIT_COEF_2                                      0xC0408
 
 #define mmMME3_RTR_SPLIT_COEF_3                                      0xC040C
 
 #define mmMME3_RTR_SPLIT_COEF_4                                      0xC0410
 
 #define mmMME3_RTR_SPLIT_COEF_5                                      0xC0414
 
 #define mmMME3_RTR_SPLIT_COEF_6                                      0xC0418
 
 #define mmMME3_RTR_SPLIT_COEF_7                                      0xC041C
 
 #define mmMME3_RTR_SPLIT_COEF_8                                      0xC0420
 
 #define mmMME3_RTR_SPLIT_COEF_9                                      0xC0424
 
 #define mmMME3_RTR_SPLIT_CFG                                         0xC0440
 
 #define mmMME3_RTR_SPLIT_RD_SAT                                      0xC0444
 
 #define mmMME3_RTR_SPLIT_RD_RST_TOKEN                                0xC0448
 
 #define mmMME3_RTR_SPLIT_RD_TIMEOUT_0                                0xC044C
 
 #define mmMME3_RTR_SPLIT_RD_TIMEOUT_1                                0xC0450
 
 #define mmMME3_RTR_SPLIT_WR_SAT                                      0xC0454
 
 #define mmMME3_RTR_WPLIT_WR_TST_TOLEN                                0xC0458
 
 #define mmMME3_RTR_SPLIT_WR_TIMEOUT_0                                0xC045C
 
 #define mmMME3_RTR_SPLIT_WR_TIMEOUT_1                                0xC0460
 
 #define mmMME3_RTR_HBW_RANGE_HIT                                     0xC0470
 
 #define mmMME3_RTR_HBW_RANGE_MASK_L_0                                0xC0480
 
 #define mmMME3_RTR_HBW_RANGE_MASK_L_1                                0xC0484
 
 #define mmMME3_RTR_HBW_RANGE_MASK_L_2                                0xC0488
 
 #define mmMME3_RTR_HBW_RANGE_MASK_L_3                                0xC048C
 
 #define mmMME3_RTR_HBW_RANGE_MASK_L_4                                0xC0490
 
 #define mmMME3_RTR_HBW_RANGE_MASK_L_5                                0xC0494
 
 #define mmMME3_RTR_HBW_RANGE_MASK_L_6                                0xC0498
 
 #define mmMME3_RTR_HBW_RANGE_MASK_L_7                                0xC049C
 
 #define mmMME3_RTR_HBW_RANGE_MASK_H_0                                0xC04A0
 
 #define mmMME3_RTR_HBW_RANGE_MASK_H_1                                0xC04A4
 
 #define mmMME3_RTR_HBW_RANGE_MASK_H_2                                0xC04A8
 
 #define mmMME3_RTR_HBW_RANGE_MASK_H_3                                0xC04AC
 
 #define mmMME3_RTR_HBW_RANGE_MASK_H_4                                0xC04B0
 
 #define mmMME3_RTR_HBW_RANGE_MASK_H_5                                0xC04B4
 
 #define mmMME3_RTR_HBW_RANGE_MASK_H_6                                0xC04B8
 
 #define mmMME3_RTR_HBW_RANGE_MASK_H_7                                0xC04BC
 
 #define mmMME3_RTR_HBW_RANGE_BASE_L_0                                0xC04C0
 
 #define mmMME3_RTR_HBW_RANGE_BASE_L_1                                0xC04C4
 
 #define mmMME3_RTR_HBW_RANGE_BASE_L_2                                0xC04C8
 
 #define mmMME3_RTR_HBW_RANGE_BASE_L_3                                0xC04CC
 
 #define mmMME3_RTR_HBW_RANGE_BASE_L_4                                0xC04D0
 
 #define mmMME3_RTR_HBW_RANGE_BASE_L_5                                0xC04D4
 
 #define mmMME3_RTR_HBW_RANGE_BASE_L_6                                0xC04D8
 
 #define mmMME3_RTR_HBW_RANGE_BASE_L_7                                0xC04DC
 
 #define mmMME3_RTR_HBW_RANGE_BASE_H_0                                0xC04E0
 
 #define mmMME3_RTR_HBW_RANGE_BASE_H_1                                0xC04E4
 
 #define mmMME3_RTR_HBW_RANGE_BASE_H_2                                0xC04E8
 
 #define mmMME3_RTR_HBW_RANGE_BASE_H_3                                0xC04EC
 
 #define mmMME3_RTR_HBW_RANGE_BASE_H_4                                0xC04F0
 
 #define mmMME3_RTR_HBW_RANGE_BASE_H_5                                0xC04F4
 
 #define mmMME3_RTR_HBW_RANGE_BASE_H_6                                0xC04F8
 
 #define mmMME3_RTR_HBW_RANGE_BASE_H_7                                0xC04FC
 
 #define mmMME3_RTR_LBW_RANGE_HIT                                     0xC0500
 
 #define mmMME3_RTR_LBW_RANGE_MASK_0                                  0xC0510
 
 #define mmMME3_RTR_LBW_RANGE_MASK_1                                  0xC0514
 
 #define mmMME3_RTR_LBW_RANGE_MASK_2                                  0xC0518
 
 #define mmMME3_RTR_LBW_RANGE_MASK_3                                  0xC051C
 
 #define mmMME3_RTR_LBW_RANGE_MASK_4                                  0xC0520
 
 #define mmMME3_RTR_LBW_RANGE_MASK_5                                  0xC0524
 
 #define mmMME3_RTR_LBW_RANGE_MASK_6                                  0xC0528
 
 #define mmMME3_RTR_LBW_RANGE_MASK_7                                  0xC052C
 
 #define mmMME3_RTR_LBW_RANGE_MASK_8                                  0xC0530
 
 #define mmMME3_RTR_LBW_RANGE_MASK_9                                  0xC0534
 
 #define mmMME3_RTR_LBW_RANGE_MASK_10                                 0xC0538
 
 #define mmMME3_RTR_LBW_RANGE_MASK_11                                 0xC053C
 
 #define mmMME3_RTR_LBW_RANGE_MASK_12                                 0xC0540
 
 #define mmMME3_RTR_LBW_RANGE_MASK_13                                 0xC0544
 
 #define mmMME3_RTR_LBW_RANGE_MASK_14                                 0xC0548
 
 #define mmMME3_RTR_LBW_RANGE_MASK_15                                 0xC054C
 
 #define mmMME3_RTR_LBW_RANGE_BASE_0                                  0xC0550
 
 #define mmMME3_RTR_LBW_RANGE_BASE_1                                  0xC0554
 
 #define mmMME3_RTR_LBW_RANGE_BASE_2                                  0xC0558
 
 #define mmMME3_RTR_LBW_RANGE_BASE_3                                  0xC055C
 
 #define mmMME3_RTR_LBW_RANGE_BASE_4                                  0xC0560
 
 #define mmMME3_RTR_LBW_RANGE_BASE_5                                  0xC0564
 
 #define mmMME3_RTR_LBW_RANGE_BASE_6                                  0xC0568
 
 #define mmMME3_RTR_LBW_RANGE_BASE_7                                  0xC056C
 
 #define mmMME3_RTR_LBW_RANGE_BASE_8                                  0xC0570
 
 #define mmMME3_RTR_LBW_RANGE_BASE_9                                  0xC0574
 
 #define mmMME3_RTR_LBW_RANGE_BASE_10                                 0xC0578
 
 #define mmMME3_RTR_LBW_RANGE_BASE_11                                 0xC057C
 
 #define mmMME3_RTR_LBW_RANGE_BASE_12                                 0xC0580
 
 #define mmMME3_RTR_LBW_RANGE_BASE_13                                 0xC0584
 
 #define mmMME3_RTR_LBW_RANGE_BASE_14                                 0xC0588
 
 #define mmMME3_RTR_LBW_RANGE_BASE_15                                 0xC058C
 
 #define mmMME3_RTR_RGLTR                                             0xC0590
 
 #define mmMME3_RTR_RGLTR_WR_RESULT                                   0xC0594
 
 #define mmMME3_RTR_RGLTR_RD_RESULT                                   0xC0598
 
 #define mmMME3_RTR_SCRAMB_EN                                         0xC0600
 
 #define mmMME3_RTR_NON_LIN_SCRAMB                                    0xC0604
 
 #endif /* ASIC_REG_MME3_RTR_REGS_H_ */

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