OSCL-LXR linux-6.0.1/​drivers/​misc/​habanalabs/​include/​goya/​asic_reg/​mme1_rtr_masks.h	Source navigation Diff markup Identifier search General search
	Version: linux-6.0.1 spark-3.0.0 hadoop-3.2.0-src hadoop-3.3.0-src spark-2.4.7 linux-4.15.13 hadoop-2.7.4-src Revert   Change

 /* SPDX-License-Identifier: GPL-2.0
  *
  * Copyright 2016-2018 HabanaLabs, Ltd.
  * All Rights Reserved.
  *
  */
 
 /************************************
  ** This is an auto-generated file **
  **       DO NOT EDIT BELOW        **
  ************************************/
 
 #ifndef ASIC_REG_MME1_RTR_MASKS_H_
 #define ASIC_REG_MME1_RTR_MASKS_H_
 
 /*
  *****************************************
  *   MME1_RTR (Prototype: MME_RTR)
  *****************************************
  */
 
 /* MME1_RTR_HBW_RD_RQ_E_ARB */
 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_SHIFT                             8
 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK                              0x700
 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_SHIFT                             16
 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK                              0x70000
 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_RD_RQ_W_ARB */
 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT                             0
 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK                              0x7
 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_SHIFT                             8
 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK                              0x700
 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_SHIFT                             16
 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK                              0x70000
 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_RD_RQ_N_ARB */
 #define MME1_RTR_HBW_RD_RQ_N_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_RD_RQ_N_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_RD_RQ_N_ARB_E_SHIFT                             8
 #define MME1_RTR_HBW_RD_RQ_N_ARB_E_MASK                              0x700
 #define MME1_RTR_HBW_RD_RQ_N_ARB_S_SHIFT                             16
 #define MME1_RTR_HBW_RD_RQ_N_ARB_S_MASK                              0x70000
 #define MME1_RTR_HBW_RD_RQ_N_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_RD_RQ_N_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_RD_RQ_S_ARB */
 #define MME1_RTR_HBW_RD_RQ_S_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_RD_RQ_S_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_RD_RQ_S_ARB_E_SHIFT                             8
 #define MME1_RTR_HBW_RD_RQ_S_ARB_E_MASK                              0x700
 #define MME1_RTR_HBW_RD_RQ_S_ARB_N_SHIFT                             16
 #define MME1_RTR_HBW_RD_RQ_S_ARB_N_MASK                              0x70000
 #define MME1_RTR_HBW_RD_RQ_S_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_RD_RQ_S_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_RD_RQ_L_ARB */
 #define MME1_RTR_HBW_RD_RQ_L_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_RD_RQ_L_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_RD_RQ_L_ARB_E_SHIFT                             8
 #define MME1_RTR_HBW_RD_RQ_L_ARB_E_MASK                              0x700
 #define MME1_RTR_HBW_RD_RQ_L_ARB_S_SHIFT                             16
 #define MME1_RTR_HBW_RD_RQ_L_ARB_S_MASK                              0x70000
 #define MME1_RTR_HBW_RD_RQ_L_ARB_N_SHIFT                             24
 #define MME1_RTR_HBW_RD_RQ_L_ARB_N_MASK                              0x7000000
 
 /* MME1_RTR_HBW_E_ARB_MAX */
 #define MME1_RTR_HBW_E_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_HBW_E_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_HBW_W_ARB_MAX */
 #define MME1_RTR_HBW_W_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_HBW_W_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_HBW_N_ARB_MAX */
 #define MME1_RTR_HBW_N_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_HBW_N_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_HBW_S_ARB_MAX */
 #define MME1_RTR_HBW_S_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_HBW_S_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_HBW_L_ARB_MAX */
 #define MME1_RTR_HBW_L_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_HBW_L_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_HBW_RD_RS_MAX_CREDIT */
 #define MME1_RTR_HBW_RD_RS_MAX_CREDIT_A_SHIFT                        0
 #define MME1_RTR_HBW_RD_RS_MAX_CREDIT_A_MASK                         0x3F
 #define MME1_RTR_HBW_RD_RS_MAX_CREDIT_B_SHIFT                        8
 #define MME1_RTR_HBW_RD_RS_MAX_CREDIT_B_MASK                         0x3F00
 
 /* MME1_RTR_HBW_WR_RQ_MAX_CREDIT */
 #define MME1_RTR_HBW_WR_RQ_MAX_CREDIT_VAL_SHIFT                      0
 #define MME1_RTR_HBW_WR_RQ_MAX_CREDIT_VAL_MASK                       0x3F
 
 /* MME1_RTR_HBW_RD_RQ_MAX_CREDIT */
 #define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_A_SHIFT                        0
 #define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_A_MASK                         0x3F
 #define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_B_SHIFT                        8
 #define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_B_MASK                         0x3F00
 #define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_IC_SHIFT                       16
 #define MME1_RTR_HBW_RD_RQ_MAX_CREDIT_IC_MASK                        0x3F0000
 
 /* MME1_RTR_HBW_RD_RS_E_ARB */
 #define MME1_RTR_HBW_RD_RS_E_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_RD_RS_E_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_RD_RS_E_ARB_S_SHIFT                             8
 #define MME1_RTR_HBW_RD_RS_E_ARB_S_MASK                              0x700
 #define MME1_RTR_HBW_RD_RS_E_ARB_N_SHIFT                             16
 #define MME1_RTR_HBW_RD_RS_E_ARB_N_MASK                              0x70000
 #define MME1_RTR_HBW_RD_RS_E_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_RD_RS_E_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_RD_RS_W_ARB */
 #define MME1_RTR_HBW_RD_RS_W_ARB_E_SHIFT                             0
 #define MME1_RTR_HBW_RD_RS_W_ARB_E_MASK                              0x7
 #define MME1_RTR_HBW_RD_RS_W_ARB_S_SHIFT                             8
 #define MME1_RTR_HBW_RD_RS_W_ARB_S_MASK                              0x700
 #define MME1_RTR_HBW_RD_RS_W_ARB_N_SHIFT                             16
 #define MME1_RTR_HBW_RD_RS_W_ARB_N_MASK                              0x70000
 #define MME1_RTR_HBW_RD_RS_W_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_RD_RS_W_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_RD_RS_N_ARB */
 #define MME1_RTR_HBW_RD_RS_N_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_RD_RS_N_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_RD_RS_N_ARB_E_SHIFT                             8
 #define MME1_RTR_HBW_RD_RS_N_ARB_E_MASK                              0x700
 #define MME1_RTR_HBW_RD_RS_N_ARB_S_SHIFT                             16
 #define MME1_RTR_HBW_RD_RS_N_ARB_S_MASK                              0x70000
 #define MME1_RTR_HBW_RD_RS_N_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_RD_RS_N_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_RD_RS_S_ARB */
 #define MME1_RTR_HBW_RD_RS_S_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_RD_RS_S_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_RD_RS_S_ARB_E_SHIFT                             8
 #define MME1_RTR_HBW_RD_RS_S_ARB_E_MASK                              0x700
 #define MME1_RTR_HBW_RD_RS_S_ARB_N_SHIFT                             16
 #define MME1_RTR_HBW_RD_RS_S_ARB_N_MASK                              0x70000
 #define MME1_RTR_HBW_RD_RS_S_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_RD_RS_S_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_RD_RS_L_ARB */
 #define MME1_RTR_HBW_RD_RS_L_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_RD_RS_L_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_RD_RS_L_ARB_E_SHIFT                             8
 #define MME1_RTR_HBW_RD_RS_L_ARB_E_MASK                              0x700
 #define MME1_RTR_HBW_RD_RS_L_ARB_S_SHIFT                             16
 #define MME1_RTR_HBW_RD_RS_L_ARB_S_MASK                              0x70000
 #define MME1_RTR_HBW_RD_RS_L_ARB_N_SHIFT                             24
 #define MME1_RTR_HBW_RD_RS_L_ARB_N_MASK                              0x7000000
 
 /* MME1_RTR_HBW_WR_RQ_E_ARB */
 #define MME1_RTR_HBW_WR_RQ_E_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_WR_RQ_E_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_WR_RQ_E_ARB_S_SHIFT                             8
 #define MME1_RTR_HBW_WR_RQ_E_ARB_S_MASK                              0x700
 #define MME1_RTR_HBW_WR_RQ_E_ARB_N_SHIFT                             16
 #define MME1_RTR_HBW_WR_RQ_E_ARB_N_MASK                              0x70000
 #define MME1_RTR_HBW_WR_RQ_E_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_WR_RQ_E_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_WR_RQ_W_ARB */
 #define MME1_RTR_HBW_WR_RQ_W_ARB_E_SHIFT                             0
 #define MME1_RTR_HBW_WR_RQ_W_ARB_E_MASK                              0x7
 #define MME1_RTR_HBW_WR_RQ_W_ARB_S_SHIFT                             8
 #define MME1_RTR_HBW_WR_RQ_W_ARB_S_MASK                              0x700
 #define MME1_RTR_HBW_WR_RQ_W_ARB_N_SHIFT                             16
 #define MME1_RTR_HBW_WR_RQ_W_ARB_N_MASK                              0x70000
 #define MME1_RTR_HBW_WR_RQ_W_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_WR_RQ_W_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_WR_RQ_N_ARB */
 #define MME1_RTR_HBW_WR_RQ_N_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_WR_RQ_N_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_WR_RQ_N_ARB_E_SHIFT                             8
 #define MME1_RTR_HBW_WR_RQ_N_ARB_E_MASK                              0x700
 #define MME1_RTR_HBW_WR_RQ_N_ARB_S_SHIFT                             16
 #define MME1_RTR_HBW_WR_RQ_N_ARB_S_MASK                              0x70000
 #define MME1_RTR_HBW_WR_RQ_N_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_WR_RQ_N_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_WR_RQ_S_ARB */
 #define MME1_RTR_HBW_WR_RQ_S_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_WR_RQ_S_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_WR_RQ_S_ARB_E_SHIFT                             8
 #define MME1_RTR_HBW_WR_RQ_S_ARB_E_MASK                              0x700
 #define MME1_RTR_HBW_WR_RQ_S_ARB_N_SHIFT                             16
 #define MME1_RTR_HBW_WR_RQ_S_ARB_N_MASK                              0x70000
 #define MME1_RTR_HBW_WR_RQ_S_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_WR_RQ_S_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_WR_RQ_L_ARB */
 #define MME1_RTR_HBW_WR_RQ_L_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_WR_RQ_L_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_WR_RQ_L_ARB_E_SHIFT                             8
 #define MME1_RTR_HBW_WR_RQ_L_ARB_E_MASK                              0x700
 #define MME1_RTR_HBW_WR_RQ_L_ARB_S_SHIFT                             16
 #define MME1_RTR_HBW_WR_RQ_L_ARB_S_MASK                              0x70000
 #define MME1_RTR_HBW_WR_RQ_L_ARB_N_SHIFT                             24
 #define MME1_RTR_HBW_WR_RQ_L_ARB_N_MASK                              0x7000000
 
 /* MME1_RTR_HBW_WR_RS_E_ARB */
 #define MME1_RTR_HBW_WR_RS_E_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_WR_RS_E_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_WR_RS_E_ARB_S_SHIFT                             8
 #define MME1_RTR_HBW_WR_RS_E_ARB_S_MASK                              0x700
 #define MME1_RTR_HBW_WR_RS_E_ARB_N_SHIFT                             16
 #define MME1_RTR_HBW_WR_RS_E_ARB_N_MASK                              0x70000
 #define MME1_RTR_HBW_WR_RS_E_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_WR_RS_E_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_WR_RS_W_ARB */
 #define MME1_RTR_HBW_WR_RS_W_ARB_E_SHIFT                             0
 #define MME1_RTR_HBW_WR_RS_W_ARB_E_MASK                              0x7
 #define MME1_RTR_HBW_WR_RS_W_ARB_S_SHIFT                             8
 #define MME1_RTR_HBW_WR_RS_W_ARB_S_MASK                              0x700
 #define MME1_RTR_HBW_WR_RS_W_ARB_N_SHIFT                             16
 #define MME1_RTR_HBW_WR_RS_W_ARB_N_MASK                              0x70000
 #define MME1_RTR_HBW_WR_RS_W_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_WR_RS_W_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_WR_RS_N_ARB */
 #define MME1_RTR_HBW_WR_RS_N_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_WR_RS_N_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_WR_RS_N_ARB_E_SHIFT                             8
 #define MME1_RTR_HBW_WR_RS_N_ARB_E_MASK                              0x700
 #define MME1_RTR_HBW_WR_RS_N_ARB_S_SHIFT                             16
 #define MME1_RTR_HBW_WR_RS_N_ARB_S_MASK                              0x70000
 #define MME1_RTR_HBW_WR_RS_N_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_WR_RS_N_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_WR_RS_S_ARB */
 #define MME1_RTR_HBW_WR_RS_S_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_WR_RS_S_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_WR_RS_S_ARB_E_SHIFT                             8
 #define MME1_RTR_HBW_WR_RS_S_ARB_E_MASK                              0x700
 #define MME1_RTR_HBW_WR_RS_S_ARB_N_SHIFT                             16
 #define MME1_RTR_HBW_WR_RS_S_ARB_N_MASK                              0x70000
 #define MME1_RTR_HBW_WR_RS_S_ARB_L_SHIFT                             24
 #define MME1_RTR_HBW_WR_RS_S_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_HBW_WR_RS_L_ARB */
 #define MME1_RTR_HBW_WR_RS_L_ARB_W_SHIFT                             0
 #define MME1_RTR_HBW_WR_RS_L_ARB_W_MASK                              0x7
 #define MME1_RTR_HBW_WR_RS_L_ARB_E_SHIFT                             8
 #define MME1_RTR_HBW_WR_RS_L_ARB_E_MASK                              0x700
 #define MME1_RTR_HBW_WR_RS_L_ARB_S_SHIFT                             16
 #define MME1_RTR_HBW_WR_RS_L_ARB_S_MASK                              0x70000
 #define MME1_RTR_HBW_WR_RS_L_ARB_N_SHIFT                             24
 #define MME1_RTR_HBW_WR_RS_L_ARB_N_MASK                              0x7000000
 
 /* MME1_RTR_LBW_RD_RQ_E_ARB */
 #define MME1_RTR_LBW_RD_RQ_E_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_RD_RQ_E_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_RD_RQ_E_ARB_S_SHIFT                             8
 #define MME1_RTR_LBW_RD_RQ_E_ARB_S_MASK                              0x700
 #define MME1_RTR_LBW_RD_RQ_E_ARB_N_SHIFT                             16
 #define MME1_RTR_LBW_RD_RQ_E_ARB_N_MASK                              0x70000
 #define MME1_RTR_LBW_RD_RQ_E_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_RD_RQ_E_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_RD_RQ_W_ARB */
 #define MME1_RTR_LBW_RD_RQ_W_ARB_E_SHIFT                             0
 #define MME1_RTR_LBW_RD_RQ_W_ARB_E_MASK                              0x7
 #define MME1_RTR_LBW_RD_RQ_W_ARB_S_SHIFT                             8
 #define MME1_RTR_LBW_RD_RQ_W_ARB_S_MASK                              0x700
 #define MME1_RTR_LBW_RD_RQ_W_ARB_N_SHIFT                             16
 #define MME1_RTR_LBW_RD_RQ_W_ARB_N_MASK                              0x70000
 #define MME1_RTR_LBW_RD_RQ_W_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_RD_RQ_W_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_RD_RQ_N_ARB */
 #define MME1_RTR_LBW_RD_RQ_N_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_RD_RQ_N_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_RD_RQ_N_ARB_E_SHIFT                             8
 #define MME1_RTR_LBW_RD_RQ_N_ARB_E_MASK                              0x700
 #define MME1_RTR_LBW_RD_RQ_N_ARB_S_SHIFT                             16
 #define MME1_RTR_LBW_RD_RQ_N_ARB_S_MASK                              0x70000
 #define MME1_RTR_LBW_RD_RQ_N_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_RD_RQ_N_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_RD_RQ_S_ARB */
 #define MME1_RTR_LBW_RD_RQ_S_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_RD_RQ_S_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_RD_RQ_S_ARB_E_SHIFT                             8
 #define MME1_RTR_LBW_RD_RQ_S_ARB_E_MASK                              0x700
 #define MME1_RTR_LBW_RD_RQ_S_ARB_N_SHIFT                             16
 #define MME1_RTR_LBW_RD_RQ_S_ARB_N_MASK                              0x70000
 #define MME1_RTR_LBW_RD_RQ_S_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_RD_RQ_S_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_RD_RQ_L_ARB */
 #define MME1_RTR_LBW_RD_RQ_L_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_RD_RQ_L_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_RD_RQ_L_ARB_E_SHIFT                             8
 #define MME1_RTR_LBW_RD_RQ_L_ARB_E_MASK                              0x700
 #define MME1_RTR_LBW_RD_RQ_L_ARB_S_SHIFT                             16
 #define MME1_RTR_LBW_RD_RQ_L_ARB_S_MASK                              0x70000
 #define MME1_RTR_LBW_RD_RQ_L_ARB_N_SHIFT                             24
 #define MME1_RTR_LBW_RD_RQ_L_ARB_N_MASK                              0x7000000
 
 /* MME1_RTR_LBW_E_ARB_MAX */
 #define MME1_RTR_LBW_E_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_LBW_E_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_LBW_W_ARB_MAX */
 #define MME1_RTR_LBW_W_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_LBW_W_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_LBW_N_ARB_MAX */
 #define MME1_RTR_LBW_N_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_LBW_N_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_LBW_S_ARB_MAX */
 #define MME1_RTR_LBW_S_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_LBW_S_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_LBW_L_ARB_MAX */
 #define MME1_RTR_LBW_L_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_LBW_L_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_LBW_SRAM_MAX_CREDIT */
 #define MME1_RTR_LBW_SRAM_MAX_CREDIT_MSTR_SHIFT                      0
 #define MME1_RTR_LBW_SRAM_MAX_CREDIT_MSTR_MASK                       0x3F
 #define MME1_RTR_LBW_SRAM_MAX_CREDIT_SLV_SHIFT                       8
 #define MME1_RTR_LBW_SRAM_MAX_CREDIT_SLV_MASK                        0x3F00
 
 /* MME1_RTR_LBW_RD_RS_E_ARB */
 #define MME1_RTR_LBW_RD_RS_E_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_RD_RS_E_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_RD_RS_E_ARB_S_SHIFT                             8
 #define MME1_RTR_LBW_RD_RS_E_ARB_S_MASK                              0x700
 #define MME1_RTR_LBW_RD_RS_E_ARB_N_SHIFT                             16
 #define MME1_RTR_LBW_RD_RS_E_ARB_N_MASK                              0x70000
 #define MME1_RTR_LBW_RD_RS_E_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_RD_RS_E_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_RD_RS_W_ARB */
 #define MME1_RTR_LBW_RD_RS_W_ARB_E_SHIFT                             0
 #define MME1_RTR_LBW_RD_RS_W_ARB_E_MASK                              0x7
 #define MME1_RTR_LBW_RD_RS_W_ARB_S_SHIFT                             8
 #define MME1_RTR_LBW_RD_RS_W_ARB_S_MASK                              0x700
 #define MME1_RTR_LBW_RD_RS_W_ARB_N_SHIFT                             16
 #define MME1_RTR_LBW_RD_RS_W_ARB_N_MASK                              0x70000
 #define MME1_RTR_LBW_RD_RS_W_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_RD_RS_W_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_RD_RS_N_ARB */
 #define MME1_RTR_LBW_RD_RS_N_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_RD_RS_N_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_RD_RS_N_ARB_E_SHIFT                             8
 #define MME1_RTR_LBW_RD_RS_N_ARB_E_MASK                              0x700
 #define MME1_RTR_LBW_RD_RS_N_ARB_S_SHIFT                             16
 #define MME1_RTR_LBW_RD_RS_N_ARB_S_MASK                              0x70000
 #define MME1_RTR_LBW_RD_RS_N_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_RD_RS_N_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_RD_RS_S_ARB */
 #define MME1_RTR_LBW_RD_RS_S_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_RD_RS_S_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_RD_RS_S_ARB_E_SHIFT                             8
 #define MME1_RTR_LBW_RD_RS_S_ARB_E_MASK                              0x700
 #define MME1_RTR_LBW_RD_RS_S_ARB_N_SHIFT                             16
 #define MME1_RTR_LBW_RD_RS_S_ARB_N_MASK                              0x70000
 #define MME1_RTR_LBW_RD_RS_S_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_RD_RS_S_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_RD_RS_L_ARB */
 #define MME1_RTR_LBW_RD_RS_L_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_RD_RS_L_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_RD_RS_L_ARB_E_SHIFT                             8
 #define MME1_RTR_LBW_RD_RS_L_ARB_E_MASK                              0x700
 #define MME1_RTR_LBW_RD_RS_L_ARB_S_SHIFT                             16
 #define MME1_RTR_LBW_RD_RS_L_ARB_S_MASK                              0x70000
 #define MME1_RTR_LBW_RD_RS_L_ARB_N_SHIFT                             24
 #define MME1_RTR_LBW_RD_RS_L_ARB_N_MASK                              0x7000000
 
 /* MME1_RTR_LBW_WR_RQ_E_ARB */
 #define MME1_RTR_LBW_WR_RQ_E_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_WR_RQ_E_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_WR_RQ_E_ARB_S_SHIFT                             8
 #define MME1_RTR_LBW_WR_RQ_E_ARB_S_MASK                              0x700
 #define MME1_RTR_LBW_WR_RQ_E_ARB_N_SHIFT                             16
 #define MME1_RTR_LBW_WR_RQ_E_ARB_N_MASK                              0x70000
 #define MME1_RTR_LBW_WR_RQ_E_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_WR_RQ_E_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_WR_RQ_W_ARB */
 #define MME1_RTR_LBW_WR_RQ_W_ARB_E_SHIFT                             0
 #define MME1_RTR_LBW_WR_RQ_W_ARB_E_MASK                              0x7
 #define MME1_RTR_LBW_WR_RQ_W_ARB_S_SHIFT                             8
 #define MME1_RTR_LBW_WR_RQ_W_ARB_S_MASK                              0x700
 #define MME1_RTR_LBW_WR_RQ_W_ARB_N_SHIFT                             16
 #define MME1_RTR_LBW_WR_RQ_W_ARB_N_MASK                              0x70000
 #define MME1_RTR_LBW_WR_RQ_W_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_WR_RQ_W_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_WR_RQ_N_ARB */
 #define MME1_RTR_LBW_WR_RQ_N_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_WR_RQ_N_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_WR_RQ_N_ARB_E_SHIFT                             8
 #define MME1_RTR_LBW_WR_RQ_N_ARB_E_MASK                              0x700
 #define MME1_RTR_LBW_WR_RQ_N_ARB_S_SHIFT                             16
 #define MME1_RTR_LBW_WR_RQ_N_ARB_S_MASK                              0x70000
 #define MME1_RTR_LBW_WR_RQ_N_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_WR_RQ_N_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_WR_RQ_S_ARB */
 #define MME1_RTR_LBW_WR_RQ_S_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_WR_RQ_S_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_WR_RQ_S_ARB_E_SHIFT                             8
 #define MME1_RTR_LBW_WR_RQ_S_ARB_E_MASK                              0x700
 #define MME1_RTR_LBW_WR_RQ_S_ARB_N_SHIFT                             16
 #define MME1_RTR_LBW_WR_RQ_S_ARB_N_MASK                              0x70000
 #define MME1_RTR_LBW_WR_RQ_S_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_WR_RQ_S_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_WR_RQ_L_ARB */
 #define MME1_RTR_LBW_WR_RQ_L_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_WR_RQ_L_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_WR_RQ_L_ARB_E_SHIFT                             8
 #define MME1_RTR_LBW_WR_RQ_L_ARB_E_MASK                              0x700
 #define MME1_RTR_LBW_WR_RQ_L_ARB_S_SHIFT                             16
 #define MME1_RTR_LBW_WR_RQ_L_ARB_S_MASK                              0x70000
 #define MME1_RTR_LBW_WR_RQ_L_ARB_N_SHIFT                             24
 #define MME1_RTR_LBW_WR_RQ_L_ARB_N_MASK                              0x7000000
 
 /* MME1_RTR_LBW_WR_RS_E_ARB */
 #define MME1_RTR_LBW_WR_RS_E_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_WR_RS_E_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_WR_RS_E_ARB_S_SHIFT                             8
 #define MME1_RTR_LBW_WR_RS_E_ARB_S_MASK                              0x700
 #define MME1_RTR_LBW_WR_RS_E_ARB_N_SHIFT                             16
 #define MME1_RTR_LBW_WR_RS_E_ARB_N_MASK                              0x70000
 #define MME1_RTR_LBW_WR_RS_E_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_WR_RS_E_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_WR_RS_W_ARB */
 #define MME1_RTR_LBW_WR_RS_W_ARB_E_SHIFT                             0
 #define MME1_RTR_LBW_WR_RS_W_ARB_E_MASK                              0x7
 #define MME1_RTR_LBW_WR_RS_W_ARB_S_SHIFT                             8
 #define MME1_RTR_LBW_WR_RS_W_ARB_S_MASK                              0x700
 #define MME1_RTR_LBW_WR_RS_W_ARB_N_SHIFT                             16
 #define MME1_RTR_LBW_WR_RS_W_ARB_N_MASK                              0x70000
 #define MME1_RTR_LBW_WR_RS_W_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_WR_RS_W_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_WR_RS_N_ARB */
 #define MME1_RTR_LBW_WR_RS_N_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_WR_RS_N_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_WR_RS_N_ARB_E_SHIFT                             8
 #define MME1_RTR_LBW_WR_RS_N_ARB_E_MASK                              0x700
 #define MME1_RTR_LBW_WR_RS_N_ARB_S_SHIFT                             16
 #define MME1_RTR_LBW_WR_RS_N_ARB_S_MASK                              0x70000
 #define MME1_RTR_LBW_WR_RS_N_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_WR_RS_N_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_WR_RS_S_ARB */
 #define MME1_RTR_LBW_WR_RS_S_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_WR_RS_S_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_WR_RS_S_ARB_E_SHIFT                             8
 #define MME1_RTR_LBW_WR_RS_S_ARB_E_MASK                              0x700
 #define MME1_RTR_LBW_WR_RS_S_ARB_N_SHIFT                             16
 #define MME1_RTR_LBW_WR_RS_S_ARB_N_MASK                              0x70000
 #define MME1_RTR_LBW_WR_RS_S_ARB_L_SHIFT                             24
 #define MME1_RTR_LBW_WR_RS_S_ARB_L_MASK                              0x7000000
 
 /* MME1_RTR_LBW_WR_RS_L_ARB */
 #define MME1_RTR_LBW_WR_RS_L_ARB_W_SHIFT                             0
 #define MME1_RTR_LBW_WR_RS_L_ARB_W_MASK                              0x7
 #define MME1_RTR_LBW_WR_RS_L_ARB_E_SHIFT                             8
 #define MME1_RTR_LBW_WR_RS_L_ARB_E_MASK                              0x700
 #define MME1_RTR_LBW_WR_RS_L_ARB_S_SHIFT                             16
 #define MME1_RTR_LBW_WR_RS_L_ARB_S_MASK                              0x70000
 #define MME1_RTR_LBW_WR_RS_L_ARB_N_SHIFT                             24
 #define MME1_RTR_LBW_WR_RS_L_ARB_N_MASK                              0x7000000
 
 /* MME1_RTR_DBG_E_ARB */
 #define MME1_RTR_DBG_E_ARB_W_SHIFT                                   0
 #define MME1_RTR_DBG_E_ARB_W_MASK                                    0x7
 #define MME1_RTR_DBG_E_ARB_S_SHIFT                                   8
 #define MME1_RTR_DBG_E_ARB_S_MASK                                    0x700
 #define MME1_RTR_DBG_E_ARB_N_SHIFT                                   16
 #define MME1_RTR_DBG_E_ARB_N_MASK                                    0x70000
 #define MME1_RTR_DBG_E_ARB_L_SHIFT                                   24
 #define MME1_RTR_DBG_E_ARB_L_MASK                                    0x7000000
 
 /* MME1_RTR_DBG_W_ARB */
 #define MME1_RTR_DBG_W_ARB_E_SHIFT                                   0
 #define MME1_RTR_DBG_W_ARB_E_MASK                                    0x7
 #define MME1_RTR_DBG_W_ARB_S_SHIFT                                   8
 #define MME1_RTR_DBG_W_ARB_S_MASK                                    0x700
 #define MME1_RTR_DBG_W_ARB_N_SHIFT                                   16
 #define MME1_RTR_DBG_W_ARB_N_MASK                                    0x70000
 #define MME1_RTR_DBG_W_ARB_L_SHIFT                                   24
 #define MME1_RTR_DBG_W_ARB_L_MASK                                    0x7000000
 
 /* MME1_RTR_DBG_N_ARB */
 #define MME1_RTR_DBG_N_ARB_W_SHIFT                                   0
 #define MME1_RTR_DBG_N_ARB_W_MASK                                    0x7
 #define MME1_RTR_DBG_N_ARB_E_SHIFT                                   8
 #define MME1_RTR_DBG_N_ARB_E_MASK                                    0x700
 #define MME1_RTR_DBG_N_ARB_S_SHIFT                                   16
 #define MME1_RTR_DBG_N_ARB_S_MASK                                    0x70000
 #define MME1_RTR_DBG_N_ARB_L_SHIFT                                   24
 #define MME1_RTR_DBG_N_ARB_L_MASK                                    0x7000000
 
 /* MME1_RTR_DBG_S_ARB */
 #define MME1_RTR_DBG_S_ARB_W_SHIFT                                   0
 #define MME1_RTR_DBG_S_ARB_W_MASK                                    0x7
 #define MME1_RTR_DBG_S_ARB_E_SHIFT                                   8
 #define MME1_RTR_DBG_S_ARB_E_MASK                                    0x700
 #define MME1_RTR_DBG_S_ARB_N_SHIFT                                   16
 #define MME1_RTR_DBG_S_ARB_N_MASK                                    0x70000
 #define MME1_RTR_DBG_S_ARB_L_SHIFT                                   24
 #define MME1_RTR_DBG_S_ARB_L_MASK                                    0x7000000
 
 /* MME1_RTR_DBG_L_ARB */
 #define MME1_RTR_DBG_L_ARB_W_SHIFT                                   0
 #define MME1_RTR_DBG_L_ARB_W_MASK                                    0x7
 #define MME1_RTR_DBG_L_ARB_E_SHIFT                                   8
 #define MME1_RTR_DBG_L_ARB_E_MASK                                    0x700
 #define MME1_RTR_DBG_L_ARB_S_SHIFT                                   16
 #define MME1_RTR_DBG_L_ARB_S_MASK                                    0x70000
 #define MME1_RTR_DBG_L_ARB_N_SHIFT                                   24
 #define MME1_RTR_DBG_L_ARB_N_MASK                                    0x7000000
 
 /* MME1_RTR_DBG_E_ARB_MAX */
 #define MME1_RTR_DBG_E_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_DBG_E_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_DBG_W_ARB_MAX */
 #define MME1_RTR_DBG_W_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_DBG_W_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_DBG_N_ARB_MAX */
 #define MME1_RTR_DBG_N_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_DBG_N_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_DBG_S_ARB_MAX */
 #define MME1_RTR_DBG_S_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_DBG_S_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_DBG_L_ARB_MAX */
 #define MME1_RTR_DBG_L_ARB_MAX_CREDIT_SHIFT                          0
 #define MME1_RTR_DBG_L_ARB_MAX_CREDIT_MASK                           0x3F
 
 /* MME1_RTR_SPLIT_COEF */
 #define MME1_RTR_SPLIT_COEF_VAL_SHIFT                                0
 #define MME1_RTR_SPLIT_COEF_VAL_MASK                                 0xFFFF
 
 /* MME1_RTR_SPLIT_CFG */
 #define MME1_RTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT                     0
 #define MME1_RTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK                      0x1
 #define MME1_RTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT                  1
 #define MME1_RTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK                   0x2
 #define MME1_RTR_SPLIT_CFG_DEFAULT_MESH_SHIFT                        2
 #define MME1_RTR_SPLIT_CFG_DEFAULT_MESH_MASK                         0xC
 #define MME1_RTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT                      4
 #define MME1_RTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK                       0x10
 #define MME1_RTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT                      5
 #define MME1_RTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK                       0x20
 #define MME1_RTR_SPLIT_CFG_B2B_OPT_SHIFT                             6
 #define MME1_RTR_SPLIT_CFG_B2B_OPT_MASK                              0x1C0
 
 /* MME1_RTR_SPLIT_RD_SAT */
 #define MME1_RTR_SPLIT_RD_SAT_VAL_SHIFT                              0
 #define MME1_RTR_SPLIT_RD_SAT_VAL_MASK                               0xFFFF
 
 /* MME1_RTR_SPLIT_RD_RST_TOKEN */
 #define MME1_RTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT                        0
 #define MME1_RTR_SPLIT_RD_RST_TOKEN_VAL_MASK                         0xFFFF
 
 /* MME1_RTR_SPLIT_RD_TIMEOUT */
 #define MME1_RTR_SPLIT_RD_TIMEOUT_VAL_SHIFT                          0
 #define MME1_RTR_SPLIT_RD_TIMEOUT_VAL_MASK                           0xFFFFFFFF
 
 /* MME1_RTR_SPLIT_WR_SAT */
 #define MME1_RTR_SPLIT_WR_SAT_VAL_SHIFT                              0
 #define MME1_RTR_SPLIT_WR_SAT_VAL_MASK                               0xFFFF
 
 /* MME1_RTR_WPLIT_WR_TST_TOLEN */
 #define MME1_RTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT                        0
 #define MME1_RTR_WPLIT_WR_TST_TOLEN_VAL_MASK                         0xFFFF
 
 /* MME1_RTR_SPLIT_WR_TIMEOUT */
 #define MME1_RTR_SPLIT_WR_TIMEOUT_VAL_SHIFT                          0
 #define MME1_RTR_SPLIT_WR_TIMEOUT_VAL_MASK                           0xFFFFFFFF
 
 /* MME1_RTR_HBW_RANGE_HIT */
 #define MME1_RTR_HBW_RANGE_HIT_IND_SHIFT                             0
 #define MME1_RTR_HBW_RANGE_HIT_IND_MASK                              0xFF
 
 /* MME1_RTR_HBW_RANGE_MASK_L */
 #define MME1_RTR_HBW_RANGE_MASK_L_VAL_SHIFT                          0
 #define MME1_RTR_HBW_RANGE_MASK_L_VAL_MASK                           0xFFFFFFFF
 
 /* MME1_RTR_HBW_RANGE_MASK_H */
 #define MME1_RTR_HBW_RANGE_MASK_H_VAL_SHIFT                          0
 #define MME1_RTR_HBW_RANGE_MASK_H_VAL_MASK                           0x3FFFF
 
 /* MME1_RTR_HBW_RANGE_BASE_L */
 #define MME1_RTR_HBW_RANGE_BASE_L_VAL_SHIFT                          0
 #define MME1_RTR_HBW_RANGE_BASE_L_VAL_MASK                           0xFFFFFFFF
 
 /* MME1_RTR_HBW_RANGE_BASE_H */
 #define MME1_RTR_HBW_RANGE_BASE_H_VAL_SHIFT                          0
 #define MME1_RTR_HBW_RANGE_BASE_H_VAL_MASK                           0x3FFFF
 
 /* MME1_RTR_LBW_RANGE_HIT */
 #define MME1_RTR_LBW_RANGE_HIT_IND_SHIFT                             0
 #define MME1_RTR_LBW_RANGE_HIT_IND_MASK                              0xFFFF
 
 /* MME1_RTR_LBW_RANGE_MASK */
 #define MME1_RTR_LBW_RANGE_MASK_VAL_SHIFT                            0
 #define MME1_RTR_LBW_RANGE_MASK_VAL_MASK                             0x3FFFFFF
 
 /* MME1_RTR_LBW_RANGE_BASE */
 #define MME1_RTR_LBW_RANGE_BASE_VAL_SHIFT                            0
 #define MME1_RTR_LBW_RANGE_BASE_VAL_MASK                             0x3FFFFFF
 
 /* MME1_RTR_RGLTR */
 #define MME1_RTR_RGLTR_WR_EN_SHIFT                                   0
 #define MME1_RTR_RGLTR_WR_EN_MASK                                    0x1
 #define MME1_RTR_RGLTR_RD_EN_SHIFT                                   4
 #define MME1_RTR_RGLTR_RD_EN_MASK                                    0x10
 
 /* MME1_RTR_RGLTR_WR_RESULT */
 #define MME1_RTR_RGLTR_WR_RESULT_VAL_SHIFT                           0
 #define MME1_RTR_RGLTR_WR_RESULT_VAL_MASK                            0xFF
 
 /* MME1_RTR_RGLTR_RD_RESULT */
 #define MME1_RTR_RGLTR_RD_RESULT_VAL_SHIFT                           0
 #define MME1_RTR_RGLTR_RD_RESULT_VAL_MASK                            0xFF
 
 /* MME1_RTR_SCRAMB_EN */
 #define MME1_RTR_SCRAMB_EN_VAL_SHIFT                                 0
 #define MME1_RTR_SCRAMB_EN_VAL_MASK                                  0x1
 
 /* MME1_RTR_NON_LIN_SCRAMB */
 #define MME1_RTR_NON_LIN_SCRAMB_EN_SHIFT                             0
 #define MME1_RTR_NON_LIN_SCRAMB_EN_MASK                              0x1
 
 #endif /* ASIC_REG_MME1_RTR_MASKS_H_ */

This page was automatically generated by the 2.1.0 LXR engine. The LXR team