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0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2016-2018 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007 
0008 /************************************
0009  ** This is an auto-generated file **
0010  **       DO NOT EDIT BELOW        **
0011  ************************************/
0012 
0013 #ifndef ASIC_REG_IC_PLL_REGS_H_
0014 #define ASIC_REG_IC_PLL_REGS_H_
0015 
0016 /*
0017  *****************************************
0018  *   IC_PLL (Prototype: PLL)
0019  *****************************************
0020  */
0021 
0022 #define mmIC_PLL_NR                                                  0x4A3100
0023 
0024 #define mmIC_PLL_NF                                                  0x4A3104
0025 
0026 #define mmIC_PLL_OD                                                  0x4A3108
0027 
0028 #define mmIC_PLL_NB                                                  0x4A310C
0029 
0030 #define mmIC_PLL_CFG                                                 0x4A3110
0031 
0032 #define mmIC_PLL_LOSE_MASK                                           0x4A3120
0033 
0034 #define mmIC_PLL_LOCK_INTR                                           0x4A3128
0035 
0036 #define mmIC_PLL_LOCK_BYPASS                                         0x4A312C
0037 
0038 #define mmIC_PLL_DATA_CHNG                                           0x4A3130
0039 
0040 #define mmIC_PLL_RST                                                 0x4A3134
0041 
0042 #define mmIC_PLL_SLIP_WD_CNTR                                        0x4A3150
0043 
0044 #define mmIC_PLL_DIV_FACTOR_0                                        0x4A3200
0045 
0046 #define mmIC_PLL_DIV_FACTOR_1                                        0x4A3204
0047 
0048 #define mmIC_PLL_DIV_FACTOR_2                                        0x4A3208
0049 
0050 #define mmIC_PLL_DIV_FACTOR_3                                        0x4A320C
0051 
0052 #define mmIC_PLL_DIV_FACTOR_CMD_0                                    0x4A3220
0053 
0054 #define mmIC_PLL_DIV_FACTOR_CMD_1                                    0x4A3224
0055 
0056 #define mmIC_PLL_DIV_FACTOR_CMD_2                                    0x4A3228
0057 
0058 #define mmIC_PLL_DIV_FACTOR_CMD_3                                    0x4A322C
0059 
0060 #define mmIC_PLL_DIV_SEL_0                                           0x4A3280
0061 
0062 #define mmIC_PLL_DIV_SEL_1                                           0x4A3284
0063 
0064 #define mmIC_PLL_DIV_SEL_2                                           0x4A3288
0065 
0066 #define mmIC_PLL_DIV_SEL_3                                           0x4A328C
0067 
0068 #define mmIC_PLL_DIV_EN_0                                            0x4A32A0
0069 
0070 #define mmIC_PLL_DIV_EN_1                                            0x4A32A4
0071 
0072 #define mmIC_PLL_DIV_EN_2                                            0x4A32A8
0073 
0074 #define mmIC_PLL_DIV_EN_3                                            0x4A32AC
0075 
0076 #define mmIC_PLL_DIV_FACTOR_BUSY_0                                   0x4A32C0
0077 
0078 #define mmIC_PLL_DIV_FACTOR_BUSY_1                                   0x4A32C4
0079 
0080 #define mmIC_PLL_DIV_FACTOR_BUSY_2                                   0x4A32C8
0081 
0082 #define mmIC_PLL_DIV_FACTOR_BUSY_3                                   0x4A32CC
0083 
0084 #define mmIC_PLL_CLK_GATER                                           0x4A3300
0085 
0086 #define mmIC_PLL_CLK_RLX_0                                           0x4A3310
0087 
0088 #define mmIC_PLL_CLK_RLX_1                                           0x4A3314
0089 
0090 #define mmIC_PLL_CLK_RLX_2                                           0x4A3318
0091 
0092 #define mmIC_PLL_CLK_RLX_3                                           0x4A331C
0093 
0094 #define mmIC_PLL_REF_CNTR_PERIOD                                     0x4A3400
0095 
0096 #define mmIC_PLL_REF_LOW_THRESHOLD                                   0x4A3410
0097 
0098 #define mmIC_PLL_REF_HIGH_THRESHOLD                                  0x4A3420
0099 
0100 #define mmIC_PLL_PLL_NOT_STABLE                                      0x4A3430
0101 
0102 #define mmIC_PLL_FREQ_CALC_EN                                        0x4A3440
0103 
0104 #endif /* ASIC_REG_IC_PLL_REGS_H_ */