goya/asic_reg/goya_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2016-2019 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007
0008 #ifndef ASIC_REG_GOYA_REGS_H_
0009 #define ASIC_REG_GOYA_REGS_H_
0010
0011 #include "goya_blocks.h"
0012 #include "stlb_regs.h"
0013 #include "mmu_regs.h"
0014 #include "pcie_aux_regs.h"
0015 #include "pcie_wrap_regs.h"
0016 #include "psoc_global_conf_regs.h"
0017 #include "psoc_spi_regs.h"
0018 #include "psoc_mme_pll_regs.h"
0019 #include "psoc_pci_pll_regs.h"
0020 #include "psoc_emmc_pll_regs.h"
0021 #include "psoc_timestamp_regs.h"
0022 #include "cpu_if_regs.h"
0023 #include "cpu_ca53_cfg_regs.h"
0024 #include "cpu_pll_regs.h"
0025 #include "ic_pll_regs.h"
0026 #include "mc_pll_regs.h"
0027 #include "tpc_pll_regs.h"
0028 #include "dma_qm_0_regs.h"
0029 #include "dma_qm_1_regs.h"
0030 #include "dma_qm_2_regs.h"
0031 #include "dma_qm_3_regs.h"
0032 #include "dma_qm_4_regs.h"
0033 #include "dma_ch_0_regs.h"
0034 #include "dma_ch_1_regs.h"
0035 #include "dma_ch_2_regs.h"
0036 #include "dma_ch_3_regs.h"
0037 #include "dma_ch_4_regs.h"
0038 #include "dma_macro_regs.h"
0039 #include "dma_nrtr_regs.h"
0040 #include "pci_nrtr_regs.h"
0041 #include "sram_y0_x0_rtr_regs.h"
0042 #include "sram_y0_x1_rtr_regs.h"
0043 #include "sram_y0_x2_rtr_regs.h"
0044 #include "sram_y0_x3_rtr_regs.h"
0045 #include "sram_y0_x4_rtr_regs.h"
0046 #include "mme_regs.h"
0047 #include "mme_qm_regs.h"
0048 #include "mme_cmdq_regs.h"
0049 #include "mme1_rtr_regs.h"
0050 #include "mme2_rtr_regs.h"
0051 #include "mme3_rtr_regs.h"
0052 #include "mme4_rtr_regs.h"
0053 #include "mme5_rtr_regs.h"
0054 #include "mme6_rtr_regs.h"
0055 #include "tpc0_cfg_regs.h"
0056 #include "tpc1_cfg_regs.h"
0057 #include "tpc2_cfg_regs.h"
0058 #include "tpc3_cfg_regs.h"
0059 #include "tpc4_cfg_regs.h"
0060 #include "tpc5_cfg_regs.h"
0061 #include "tpc6_cfg_regs.h"
0062 #include "tpc7_cfg_regs.h"
0063 #include "tpc0_qm_regs.h"
0064 #include "tpc1_qm_regs.h"
0065 #include "tpc2_qm_regs.h"
0066 #include "tpc3_qm_regs.h"
0067 #include "tpc4_qm_regs.h"
0068 #include "tpc5_qm_regs.h"
0069 #include "tpc6_qm_regs.h"
0070 #include "tpc7_qm_regs.h"
0071 #include "tpc0_cmdq_regs.h"
0072 #include "tpc1_cmdq_regs.h"
0073 #include "tpc2_cmdq_regs.h"
0074 #include "tpc3_cmdq_regs.h"
0075 #include "tpc4_cmdq_regs.h"
0076 #include "tpc5_cmdq_regs.h"
0077 #include "tpc6_cmdq_regs.h"
0078 #include "tpc7_cmdq_regs.h"
0079 #include "tpc0_nrtr_regs.h"
0080 #include "tpc1_rtr_regs.h"
0081 #include "tpc2_rtr_regs.h"
0082 #include "tpc3_rtr_regs.h"
0083 #include "tpc4_rtr_regs.h"
0084 #include "tpc5_rtr_regs.h"
0085 #include "tpc6_rtr_regs.h"
0086 #include "tpc7_nrtr_regs.h"
0087 #include "tpc0_eml_cfg_regs.h"
0088 #include "psoc_etr_regs.h"
0089
0090 #include "psoc_global_conf_masks.h"
0091 #include "dma_macro_masks.h"
0092 #include "dma_qm_0_masks.h"
0093 #include "dma_ch_0_masks.h"
0094 #include "tpc0_qm_masks.h"
0095 #include "tpc0_cmdq_masks.h"
0096 #include "mme_qm_masks.h"
0097 #include "mme_cmdq_masks.h"
0098 #include "tpc0_cfg_masks.h"
0099 #include "tpc0_eml_cfg_masks.h"
0100 #include "mme1_rtr_masks.h"
0101 #include "tpc0_nrtr_masks.h"
0102 #include "dma_nrtr_masks.h"
0103 #include "pci_nrtr_masks.h"
0104 #include "stlb_masks.h"
0105 #include "cpu_ca53_cfg_masks.h"
0106 #include "mmu_masks.h"
0107 #include "mme_masks.h"
0108
0109 #define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG                           0xC02000
0110 #define mmPCIE_DBI_MSIX_DOORBELL_OFF                                 0xC02948
0111
0112 #define mmSYNC_MNGR_MON_PAY_ADDRL_0                                  0x113000
0113 #define mmSYNC_MNGR_SOB_OBJ_0                                        0x112000
0114 #define mmSYNC_MNGR_SOB_OBJ_1000                                     0x112FA0
0115 #define mmSYNC_MNGR_SOB_OBJ_1007                                     0x112FBC
0116 #define mmSYNC_MNGR_SOB_OBJ_1023                                     0x112FFC
0117 #define mmSYNC_MNGR_MON_STATUS_0                                     0x114000
0118 #define mmSYNC_MNGR_MON_STATUS_255                                   0x1143FC
0119
0120 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR                         0x800040
0121
0122 #endif /* ASIC_REG_GOYA_REGS_H_ */