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0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2016-2018 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007 
0008 /************************************
0009  ** This is an auto-generated file **
0010  **       DO NOT EDIT BELOW        **
0011  ************************************/
0012 
0013 #ifndef ASIC_REG_DMA_NRTR_MASKS_H_
0014 #define ASIC_REG_DMA_NRTR_MASKS_H_
0015 
0016 /*
0017  *****************************************
0018  *   DMA_NRTR (Prototype: IF_NRTR)
0019  *****************************************
0020  */
0021 
0022 /* DMA_NRTR_HBW_MAX_CRED */
0023 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT                            0
0024 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK                             0x3F
0025 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_SHIFT                            8
0026 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK                             0x3F00
0027 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT                            16
0028 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK                             0x3F0000
0029 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_SHIFT                            24
0030 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK                             0x3F000000
0031 
0032 /* DMA_NRTR_LBW_MAX_CRED */
0033 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT                            0
0034 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK                             0x3F
0035 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_SHIFT                            8
0036 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK                             0x3F00
0037 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT                            16
0038 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK                             0x3F0000
0039 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_SHIFT                            24
0040 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK                             0x3F000000
0041 
0042 /* DMA_NRTR_DBG_E_ARB */
0043 #define DMA_NRTR_DBG_E_ARB_W_SHIFT                                   0
0044 #define DMA_NRTR_DBG_E_ARB_W_MASK                                    0x7
0045 #define DMA_NRTR_DBG_E_ARB_S_SHIFT                                   8
0046 #define DMA_NRTR_DBG_E_ARB_S_MASK                                    0x700
0047 #define DMA_NRTR_DBG_E_ARB_N_SHIFT                                   16
0048 #define DMA_NRTR_DBG_E_ARB_N_MASK                                    0x70000
0049 #define DMA_NRTR_DBG_E_ARB_L_SHIFT                                   24
0050 #define DMA_NRTR_DBG_E_ARB_L_MASK                                    0x7000000
0051 
0052 /* DMA_NRTR_DBG_W_ARB */
0053 #define DMA_NRTR_DBG_W_ARB_E_SHIFT                                   0
0054 #define DMA_NRTR_DBG_W_ARB_E_MASK                                    0x7
0055 #define DMA_NRTR_DBG_W_ARB_S_SHIFT                                   8
0056 #define DMA_NRTR_DBG_W_ARB_S_MASK                                    0x700
0057 #define DMA_NRTR_DBG_W_ARB_N_SHIFT                                   16
0058 #define DMA_NRTR_DBG_W_ARB_N_MASK                                    0x70000
0059 #define DMA_NRTR_DBG_W_ARB_L_SHIFT                                   24
0060 #define DMA_NRTR_DBG_W_ARB_L_MASK                                    0x7000000
0061 
0062 /* DMA_NRTR_DBG_N_ARB */
0063 #define DMA_NRTR_DBG_N_ARB_W_SHIFT                                   0
0064 #define DMA_NRTR_DBG_N_ARB_W_MASK                                    0x7
0065 #define DMA_NRTR_DBG_N_ARB_E_SHIFT                                   8
0066 #define DMA_NRTR_DBG_N_ARB_E_MASK                                    0x700
0067 #define DMA_NRTR_DBG_N_ARB_S_SHIFT                                   16
0068 #define DMA_NRTR_DBG_N_ARB_S_MASK                                    0x70000
0069 #define DMA_NRTR_DBG_N_ARB_L_SHIFT                                   24
0070 #define DMA_NRTR_DBG_N_ARB_L_MASK                                    0x7000000
0071 
0072 /* DMA_NRTR_DBG_S_ARB */
0073 #define DMA_NRTR_DBG_S_ARB_W_SHIFT                                   0
0074 #define DMA_NRTR_DBG_S_ARB_W_MASK                                    0x7
0075 #define DMA_NRTR_DBG_S_ARB_E_SHIFT                                   8
0076 #define DMA_NRTR_DBG_S_ARB_E_MASK                                    0x700
0077 #define DMA_NRTR_DBG_S_ARB_N_SHIFT                                   16
0078 #define DMA_NRTR_DBG_S_ARB_N_MASK                                    0x70000
0079 #define DMA_NRTR_DBG_S_ARB_L_SHIFT                                   24
0080 #define DMA_NRTR_DBG_S_ARB_L_MASK                                    0x7000000
0081 
0082 /* DMA_NRTR_DBG_L_ARB */
0083 #define DMA_NRTR_DBG_L_ARB_W_SHIFT                                   0
0084 #define DMA_NRTR_DBG_L_ARB_W_MASK                                    0x7
0085 #define DMA_NRTR_DBG_L_ARB_E_SHIFT                                   8
0086 #define DMA_NRTR_DBG_L_ARB_E_MASK                                    0x700
0087 #define DMA_NRTR_DBG_L_ARB_S_SHIFT                                   16
0088 #define DMA_NRTR_DBG_L_ARB_S_MASK                                    0x70000
0089 #define DMA_NRTR_DBG_L_ARB_N_SHIFT                                   24
0090 #define DMA_NRTR_DBG_L_ARB_N_MASK                                    0x7000000
0091 
0092 /* DMA_NRTR_DBG_E_ARB_MAX */
0093 #define DMA_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT                          0
0094 #define DMA_NRTR_DBG_E_ARB_MAX_CREDIT_MASK                           0x3F
0095 
0096 /* DMA_NRTR_DBG_W_ARB_MAX */
0097 #define DMA_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT                          0
0098 #define DMA_NRTR_DBG_W_ARB_MAX_CREDIT_MASK                           0x3F
0099 
0100 /* DMA_NRTR_DBG_N_ARB_MAX */
0101 #define DMA_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT                          0
0102 #define DMA_NRTR_DBG_N_ARB_MAX_CREDIT_MASK                           0x3F
0103 
0104 /* DMA_NRTR_DBG_S_ARB_MAX */
0105 #define DMA_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT                          0
0106 #define DMA_NRTR_DBG_S_ARB_MAX_CREDIT_MASK                           0x3F
0107 
0108 /* DMA_NRTR_DBG_L_ARB_MAX */
0109 #define DMA_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT                          0
0110 #define DMA_NRTR_DBG_L_ARB_MAX_CREDIT_MASK                           0x3F
0111 
0112 /* DMA_NRTR_SPLIT_COEF */
0113 #define DMA_NRTR_SPLIT_COEF_VAL_SHIFT                                0
0114 #define DMA_NRTR_SPLIT_COEF_VAL_MASK                                 0xFFFF
0115 
0116 /* DMA_NRTR_SPLIT_CFG */
0117 #define DMA_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT                     0
0118 #define DMA_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK                      0x1
0119 #define DMA_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT                  1
0120 #define DMA_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK                   0x2
0121 #define DMA_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT                        2
0122 #define DMA_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK                         0xC
0123 #define DMA_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT                      4
0124 #define DMA_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK                       0x10
0125 #define DMA_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT                      5
0126 #define DMA_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK                       0x20
0127 #define DMA_NRTR_SPLIT_CFG_B2B_OPT_SHIFT                             6
0128 #define DMA_NRTR_SPLIT_CFG_B2B_OPT_MASK                              0x1C0
0129 
0130 /* DMA_NRTR_SPLIT_RD_SAT */
0131 #define DMA_NRTR_SPLIT_RD_SAT_VAL_SHIFT                              0
0132 #define DMA_NRTR_SPLIT_RD_SAT_VAL_MASK                               0xFFFF
0133 
0134 /* DMA_NRTR_SPLIT_RD_RST_TOKEN */
0135 #define DMA_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT                        0
0136 #define DMA_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK                         0xFFFF
0137 
0138 /* DMA_NRTR_SPLIT_RD_TIMEOUT */
0139 #define DMA_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT                          0
0140 #define DMA_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK                           0xFFFFFFFF
0141 
0142 /* DMA_NRTR_SPLIT_WR_SAT */
0143 #define DMA_NRTR_SPLIT_WR_SAT_VAL_SHIFT                              0
0144 #define DMA_NRTR_SPLIT_WR_SAT_VAL_MASK                               0xFFFF
0145 
0146 /* DMA_NRTR_WPLIT_WR_TST_TOLEN */
0147 #define DMA_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT                        0
0148 #define DMA_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK                         0xFFFF
0149 
0150 /* DMA_NRTR_SPLIT_WR_TIMEOUT */
0151 #define DMA_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT                          0
0152 #define DMA_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK                           0xFFFFFFFF
0153 
0154 /* DMA_NRTR_HBW_RANGE_HIT */
0155 #define DMA_NRTR_HBW_RANGE_HIT_IND_SHIFT                             0
0156 #define DMA_NRTR_HBW_RANGE_HIT_IND_MASK                              0xFF
0157 
0158 /* DMA_NRTR_HBW_RANGE_MASK_L */
0159 #define DMA_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT                          0
0160 #define DMA_NRTR_HBW_RANGE_MASK_L_VAL_MASK                           0xFFFFFFFF
0161 
0162 /* DMA_NRTR_HBW_RANGE_MASK_H */
0163 #define DMA_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT                          0
0164 #define DMA_NRTR_HBW_RANGE_MASK_H_VAL_MASK                           0x3FFFF
0165 
0166 /* DMA_NRTR_HBW_RANGE_BASE_L */
0167 #define DMA_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT                          0
0168 #define DMA_NRTR_HBW_RANGE_BASE_L_VAL_MASK                           0xFFFFFFFF
0169 
0170 /* DMA_NRTR_HBW_RANGE_BASE_H */
0171 #define DMA_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT                          0
0172 #define DMA_NRTR_HBW_RANGE_BASE_H_VAL_MASK                           0x3FFFF
0173 
0174 /* DMA_NRTR_LBW_RANGE_HIT */
0175 #define DMA_NRTR_LBW_RANGE_HIT_IND_SHIFT                             0
0176 #define DMA_NRTR_LBW_RANGE_HIT_IND_MASK                              0xFFFF
0177 
0178 /* DMA_NRTR_LBW_RANGE_MASK */
0179 #define DMA_NRTR_LBW_RANGE_MASK_VAL_SHIFT                            0
0180 #define DMA_NRTR_LBW_RANGE_MASK_VAL_MASK                             0x3FFFFFF
0181 
0182 /* DMA_NRTR_LBW_RANGE_BASE */
0183 #define DMA_NRTR_LBW_RANGE_BASE_VAL_SHIFT                            0
0184 #define DMA_NRTR_LBW_RANGE_BASE_VAL_MASK                             0x3FFFFFF
0185 
0186 /* DMA_NRTR_RGLTR */
0187 #define DMA_NRTR_RGLTR_WR_EN_SHIFT                                   0
0188 #define DMA_NRTR_RGLTR_WR_EN_MASK                                    0x1
0189 #define DMA_NRTR_RGLTR_RD_EN_SHIFT                                   4
0190 #define DMA_NRTR_RGLTR_RD_EN_MASK                                    0x10
0191 
0192 /* DMA_NRTR_RGLTR_WR_RESULT */
0193 #define DMA_NRTR_RGLTR_WR_RESULT_VAL_SHIFT                           0
0194 #define DMA_NRTR_RGLTR_WR_RESULT_VAL_MASK                            0xFF
0195 
0196 /* DMA_NRTR_RGLTR_RD_RESULT */
0197 #define DMA_NRTR_RGLTR_RD_RESULT_VAL_SHIFT                           0
0198 #define DMA_NRTR_RGLTR_RD_RESULT_VAL_MASK                            0xFF
0199 
0200 /* DMA_NRTR_SCRAMB_EN */
0201 #define DMA_NRTR_SCRAMB_EN_VAL_SHIFT                                 0
0202 #define DMA_NRTR_SCRAMB_EN_VAL_MASK                                  0x1
0203 
0204 /* DMA_NRTR_NON_LIN_SCRAMB */
0205 #define DMA_NRTR_NON_LIN_SCRAMB_EN_SHIFT                             0
0206 #define DMA_NRTR_NON_LIN_SCRAMB_EN_MASK                              0x1
0207 
0208 #endif /* ASIC_REG_DMA_NRTR_MASKS_H_ */
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