goya/asic_reg/dma_macro_masks.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2016-2018 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007
0008 /************************************
0009  ** This is an auto-generated file **
0010  **       DO NOT EDIT BELOW        **
0011  ************************************/
0012
0013 #ifndef ASIC_REG_DMA_MACRO_MASKS_H_
0014 #define ASIC_REG_DMA_MACRO_MASKS_H_
0015
0016 /*
0017  *****************************************
0018  *   DMA_MACRO (Prototype: DMA_MACRO)
0019  *****************************************
0020  */
0021
0022 /* DMA_MACRO_LBW_RANGE_HIT_BLOCK */
0023 #define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_SHIFT                        0
0024 #define DMA_MACRO_LBW_RANGE_HIT_BLOCK_R_MASK                         0xFFFF
0025
0026 /* DMA_MACRO_LBW_RANGE_MASK */
0027 #define DMA_MACRO_LBW_RANGE_MASK_R_SHIFT                             0
0028 #define DMA_MACRO_LBW_RANGE_MASK_R_MASK                              0x3FFFFFF
0029
0030 /* DMA_MACRO_LBW_RANGE_BASE */
0031 #define DMA_MACRO_LBW_RANGE_BASE_R_SHIFT                             0
0032 #define DMA_MACRO_LBW_RANGE_BASE_R_MASK                              0x3FFFFFF
0033
0034 /* DMA_MACRO_HBW_RANGE_HIT_BLOCK */
0035 #define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_SHIFT                        0
0036 #define DMA_MACRO_HBW_RANGE_HIT_BLOCK_R_MASK                         0xFF
0037
0038 /* DMA_MACRO_HBW_RANGE_MASK_49_32 */
0039 #define DMA_MACRO_HBW_RANGE_MASK_49_32_R_SHIFT                       0
0040 #define DMA_MACRO_HBW_RANGE_MASK_49_32_R_MASK                        0x3FFFF
0041
0042 /* DMA_MACRO_HBW_RANGE_MASK_31_0 */
0043 #define DMA_MACRO_HBW_RANGE_MASK_31_0_R_SHIFT                        0
0044 #define DMA_MACRO_HBW_RANGE_MASK_31_0_R_MASK                         0xFFFFFFFF
0045
0046 /* DMA_MACRO_HBW_RANGE_BASE_49_32 */
0047 #define DMA_MACRO_HBW_RANGE_BASE_49_32_R_SHIFT                       0
0048 #define DMA_MACRO_HBW_RANGE_BASE_49_32_R_MASK                        0x3FFFF
0049
0050 /* DMA_MACRO_HBW_RANGE_BASE_31_0 */
0051 #define DMA_MACRO_HBW_RANGE_BASE_31_0_R_SHIFT                        0
0052 #define DMA_MACRO_HBW_RANGE_BASE_31_0_R_MASK                         0xFFFFFFFF
0053
0054 /* DMA_MACRO_WRITE_EN */
0055 #define DMA_MACRO_WRITE_EN_R_SHIFT                                   0
0056 #define DMA_MACRO_WRITE_EN_R_MASK                                    0x1
0057
0058 /* DMA_MACRO_WRITE_CREDIT */
0059 #define DMA_MACRO_WRITE_CREDIT_R_SHIFT                               0
0060 #define DMA_MACRO_WRITE_CREDIT_R_MASK                                0x3FF
0061
0062 /* DMA_MACRO_READ_EN */
0063 #define DMA_MACRO_READ_EN_R_SHIFT                                    0
0064 #define DMA_MACRO_READ_EN_R_MASK                                     0x1
0065
0066 /* DMA_MACRO_READ_CREDIT */
0067 #define DMA_MACRO_READ_CREDIT_R_SHIFT                                0
0068 #define DMA_MACRO_READ_CREDIT_R_MASK                                 0x3FF
0069
0070 /* DMA_MACRO_SRAM_BUSY */
0071
0072 /* DMA_MACRO_RAZWI_LBW_WT_VLD */
0073 #define DMA_MACRO_RAZWI_LBW_WT_VLD_R_SHIFT                           0
0074 #define DMA_MACRO_RAZWI_LBW_WT_VLD_R_MASK                            0x1
0075
0076 /* DMA_MACRO_RAZWI_LBW_WT_ID */
0077 #define DMA_MACRO_RAZWI_LBW_WT_ID_R_SHIFT                            0
0078 #define DMA_MACRO_RAZWI_LBW_WT_ID_R_MASK                             0x7FFF
0079
0080 /* DMA_MACRO_RAZWI_LBW_RD_VLD */
0081 #define DMA_MACRO_RAZWI_LBW_RD_VLD_R_SHIFT                           0
0082 #define DMA_MACRO_RAZWI_LBW_RD_VLD_R_MASK                            0x1
0083
0084 /* DMA_MACRO_RAZWI_LBW_RD_ID */
0085 #define DMA_MACRO_RAZWI_LBW_RD_ID_R_SHIFT                            0
0086 #define DMA_MACRO_RAZWI_LBW_RD_ID_R_MASK                             0x7FFF
0087
0088 /* DMA_MACRO_RAZWI_HBW_WT_VLD */
0089 #define DMA_MACRO_RAZWI_HBW_WT_VLD_R_SHIFT                           0
0090 #define DMA_MACRO_RAZWI_HBW_WT_VLD_R_MASK                            0x1
0091
0092 /* DMA_MACRO_RAZWI_HBW_WT_ID */
0093 #define DMA_MACRO_RAZWI_HBW_WT_ID_R_SHIFT                            0
0094 #define DMA_MACRO_RAZWI_HBW_WT_ID_R_MASK                             0x1FFFFFFF
0095
0096 /* DMA_MACRO_RAZWI_HBW_RD_VLD */
0097 #define DMA_MACRO_RAZWI_HBW_RD_VLD_R_SHIFT                           0
0098 #define DMA_MACRO_RAZWI_HBW_RD_VLD_R_MASK                            0x1
0099
0100 /* DMA_MACRO_RAZWI_HBW_RD_ID */
0101 #define DMA_MACRO_RAZWI_HBW_RD_ID_R_SHIFT                            0
0102 #define DMA_MACRO_RAZWI_HBW_RD_ID_R_MASK                             0x1FFFFFFF
0103
0104 #endif /* ASIC_REG_DMA_MACRO_MASKS_H_ */