goya/asic_reg/cpu_ca53_cfg_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2016-2018 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007
0008 /************************************
0009  ** This is an auto-generated file **
0010  **       DO NOT EDIT BELOW        **
0011  ************************************/
0012
0013 #ifndef ASIC_REG_CPU_CA53_CFG_REGS_H_
0014 #define ASIC_REG_CPU_CA53_CFG_REGS_H_
0015
0016 /*
0017  *****************************************
0018  *   CPU_CA53_CFG (Prototype: CA53_CFG)
0019  *****************************************
0020  */
0021
0022 #define mmCPU_CA53_CFG_ARM_CFG                                       0x441100
0023
0024 #define mmCPU_CA53_CFG_RST_ADDR_LSB_0                                0x441104
0025
0026 #define mmCPU_CA53_CFG_RST_ADDR_LSB_1                                0x441108
0027
0028 #define mmCPU_CA53_CFG_RST_ADDR_MSB_0                                0x441114
0029
0030 #define mmCPU_CA53_CFG_RST_ADDR_MSB_1                                0x441118
0031
0032 #define mmCPU_CA53_CFG_ARM_RST_CONTROL                               0x441124
0033
0034 #define mmCPU_CA53_CFG_ARM_AFFINITY                                  0x441128
0035
0036 #define mmCPU_CA53_CFG_ARM_DISABLE                                   0x44112C
0037
0038 #define mmCPU_CA53_CFG_ARM_GIC_PERIPHBASE                            0x441130
0039
0040 #define mmCPU_CA53_CFG_ARM_GIC_IRQ_CFG                               0x441134
0041
0042 #define mmCPU_CA53_CFG_ARM_PWR_MNG                                   0x441138
0043
0044 #define mmCPU_CA53_CFG_ARB_DBG_ROM_ADDR                              0x44113C
0045
0046 #define mmCPU_CA53_CFG_ARM_DBG_MODES                                 0x441140
0047
0048 #define mmCPU_CA53_CFG_ARM_PWR_STAT_0                                0x441200
0049
0050 #define mmCPU_CA53_CFG_ARM_PWR_STAT_1                                0x441204
0051
0052 #define mmCPU_CA53_CFG_ARM_DBG_STATUS                                0x441208
0053
0054 #define mmCPU_CA53_CFG_ARM_MEM_ATTR                                  0x44120C
0055
0056 #define mmCPU_CA53_CFG_ARM_PMU_0                                     0x441210
0057
0058 #define mmCPU_CA53_CFG_ARM_PMU_1                                     0x441214
0059
0060 #endif /* ASIC_REG_CPU_CA53_CFG_REGS_H_ */