goya/asic_reg/cpu_ca53_cfg_masks.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2016-2018 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007
0008 /************************************
0009  ** This is an auto-generated file **
0010  **       DO NOT EDIT BELOW        **
0011  ************************************/
0012
0013 #ifndef ASIC_REG_CPU_CA53_CFG_MASKS_H_
0014 #define ASIC_REG_CPU_CA53_CFG_MASKS_H_
0015
0016 /*
0017  *****************************************
0018  *   CPU_CA53_CFG (Prototype: CA53_CFG)
0019  *****************************************
0020  */
0021
0022 /* CPU_CA53_CFG_ARM_CFG */
0023 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT                         0
0024 #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK                          0x3
0025 #define CPU_CA53_CFG_ARM_CFG_END_SHIFT                               4
0026 #define CPU_CA53_CFG_ARM_CFG_END_MASK                                0x30
0027 #define CPU_CA53_CFG_ARM_CFG_TE_SHIFT                                8
0028 #define CPU_CA53_CFG_ARM_CFG_TE_MASK                                 0x300
0029 #define CPU_CA53_CFG_ARM_CFG_VINITHI_SHIFT                           12
0030 #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK                            0x3000
0031
0032 /* CPU_CA53_CFG_RST_ADDR_LSB */
0033 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT                       0
0034 #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK                        0xFFFFFFFF
0035
0036 /* CPU_CA53_CFG_RST_ADDR_MSB */
0037 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT                       0
0038 #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK                        0xFF
0039
0040 /* CPU_CA53_CFG_ARM_RST_CONTROL */
0041 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT               0
0042 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK                0x3
0043 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT                4
0044 #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK                 0x30
0045 #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT                  8
0046 #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK                   0x100
0047 #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT                12
0048 #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK                 0x1000
0049 #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT               16
0050 #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK                0x10000
0051 #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT                20
0052 #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK                 0x300000
0053
0054 /* CPU_CA53_CFG_ARM_AFFINITY */
0055 #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_SHIFT                      0
0056 #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_MASK                       0xFF
0057 #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_SHIFT                      8
0058 #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_MASK                       0xFF00
0059
0060 /* CPU_CA53_CFG_ARM_DISABLE */
0061 #define CPU_CA53_CFG_ARM_DISABLE_CP15S_SHIFT                         0
0062 #define CPU_CA53_CFG_ARM_DISABLE_CP15S_MASK                          0x3
0063 #define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_SHIFT                        4
0064 #define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_MASK                         0x30
0065 #define CPU_CA53_CFG_ARM_DISABLE_L2_RST_SHIFT                        8
0066 #define CPU_CA53_CFG_ARM_DISABLE_L2_RST_MASK                         0x100
0067 #define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_SHIFT                    9
0068 #define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_MASK                     0x200
0069
0070 /* CPU_CA53_CFG_ARM_GIC_PERIPHBASE */
0071 #define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_SHIFT             0
0072 #define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_MASK              0x3FFFFF
0073
0074 /* CPU_CA53_CFG_ARM_GIC_IRQ_CFG */
0075 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_SHIFT                      0
0076 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_MASK                       0x3
0077 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_SHIFT                      4
0078 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_MASK                       0x30
0079 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_SHIFT                      8
0080 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_MASK                       0x300
0081 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_SHIFT                      12
0082 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_MASK                       0x3000
0083 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_SHIFT                     16
0084 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_MASK                      0x30000
0085 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_SHIFT                     20
0086 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_MASK                      0x300000
0087 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_SHIFT                     24
0088 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_MASK                      0x3000000
0089 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_SHIFT                    31
0090 #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_MASK                     0x80000000
0091
0092 /* CPU_CA53_CFG_ARM_PWR_MNG */
0093 #define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_SHIFT                   0
0094 #define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_MASK                    0x1
0095 #define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_SHIFT                        1
0096 #define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_MASK                         0x2
0097 #define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_SHIFT                    2
0098 #define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_MASK                     0x4
0099 #define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_SHIFT                       3
0100 #define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_MASK                        0x8
0101 #define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_SHIFT                      4
0102 #define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_MASK                       0x30
0103 #define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_SHIFT                     8
0104 #define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_MASK                      0x300
0105 #define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_SHIFT                     12
0106 #define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_MASK                      0x3000
0107
0108 /* CPU_CA53_CFG_ARB_DBG_ROM_ADDR */
0109 #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_SHIFT      0
0110 #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_MASK       0xFFFFFFF
0111 #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_SHIFT 31
0112 #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_MASK 0x80000000
0113
0114 /* CPU_CA53_CFG_ARM_DBG_MODES */
0115 #define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_SHIFT                      0
0116 #define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_MASK                       0x3
0117 #define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_SHIFT                       4
0118 #define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_MASK                        0x30
0119 #define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_SHIFT                       8
0120 #define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_MASK                        0x300
0121 #define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_SHIFT                      12
0122 #define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_MASK                       0x3000
0123 #define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_SHIFT                     16
0124 #define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_MASK                      0x30000
0125
0126 /* CPU_CA53_CFG_ARM_PWR_STAT_0 */
0127 #define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_SHIFT                0
0128 #define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_MASK                 0x1
0129 #define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_SHIFT                     1
0130 #define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_MASK                      0x2
0131 #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_SHIFT                 4
0132 #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_MASK                  0x30
0133 #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_SHIFT                 8
0134 #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_MASK                  0x300
0135 #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_SHIFT               12
0136 #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_MASK                0x1000
0137 #define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_SHIFT                13
0138 #define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_MASK                 0x2000
0139 #define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_SHIFT                      16
0140 #define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_MASK                       0x30000
0141
0142 /* CPU_CA53_CFG_ARM_PWR_STAT_1 */
0143 #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_SHIFT                 0
0144 #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_MASK                  0x3
0145 #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_SHIFT                   4
0146 #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_MASK                    0x30
0147 #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_SHIFT                8
0148 #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_MASK                 0x300
0149 #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_SHIFT                12
0150 #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_MASK                 0x3000
0151 #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_SHIFT                  16
0152 #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_MASK                   0x30000
0153 #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_SHIFT               20
0154 #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_MASK                0x300000
0155 #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_SHIFT                  24
0156 #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_MASK                   0x1000000
0157 #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_SHIFT                    25
0158 #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_MASK                     0x2000000
0159 #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_SHIFT                 26
0160 #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_MASK                  0x4000000
0161
0162 /* CPU_CA53_CFG_ARM_DBG_STATUS */
0163 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_SHIFT                     0
0164 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_MASK                      0x3
0165 #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_SHIFT                     4
0166 #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_MASK                      0x30
0167 #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_SHIFT                     8
0168 #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_MASK                      0x300
0169 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_SHIFT                  12
0170 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_MASK                   0x3000
0171 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_SHIFT                16
0172 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_MASK                 0x30000
0173 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_SHIFT                20
0174 #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_MASK                 0x300000
0175
0176 /* CPU_CA53_CFG_ARM_MEM_ATTR */
0177 #define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_SHIFT                    0
0178 #define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_MASK                     0xFF
0179 #define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_SHIFT                    8
0180 #define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_MASK                     0xFF00
0181 #define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_SHIFT                        16
0182 #define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_MASK                         0x10000
0183 #define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_SHIFT                        20
0184 #define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_MASK                         0x100000
0185
0186 /* CPU_CA53_CFG_ARM_PMU */
0187 #define CPU_CA53_CFG_ARM_PMU_EVENT_SHIFT                             0
0188 #define CPU_CA53_CFG_ARM_PMU_EVENT_MASK                              0x3FFFFFFF
0189
0190 #endif /* ASIC_REG_CPU_CA53_CFG_MASKS_H_ */