include/gaudi2/gaudi2_reg_map.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2020 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007
0008 #ifndef GAUDI2_REG_MAP_H_
0009 #define GAUDI2_REG_MAP_H_
0010
0011 /*
0012  * PSOC scratch-pad registers
0013  */
0014 #define mmHW_STATE              mmCPU_IF_KMD_HW_DIRTY_STATUS
0015 #define mmPID_STATUS_REG            mmPSOC_GLOBAL_CONF_SCRATCHPAD_1
0016 #define mmARM_STATUS_REG            mmPSOC_GLOBAL_CONF_SCRATCHPAD_2
0017 #define mmGIC_TPC_QM_IRQ_CTRL_POLL_REG      mmPSOC_GLOBAL_CONF_SCRATCHPAD_3
0018 #define mmGIC_MME_QM_IRQ_CTRL_POLL_REG      mmPSOC_GLOBAL_CONF_SCRATCHPAD_4
0019 #define mmGIC_DMA_QM_IRQ_CTRL_POLL_REG      mmPSOC_GLOBAL_CONF_SCRATCHPAD_5
0020 #define mmGIC_ROT_QM_IRQ_CTRL_POLL_REG      mmPSOC_GLOBAL_CONF_SCRATCHPAD_6
0021 #define mmGIC_NIC_QM_IRQ_CTRL_POLL_REG      mmPSOC_GLOBAL_CONF_SCRATCHPAD_7
0022 #define mmGIC_DMA_CR_IRQ_CTRL_POLL_REG      mmPSOC_GLOBAL_CONF_SCRATCHPAD_8
0023 #define mmGIC_HOST_PI_UPD_IRQ_POLL_REG      mmPSOC_GLOBAL_CONF_SCRATCHPAD_9
0024 #define mmGIC_HOST_HALT_IRQ_POLL_REG        mmPSOC_GLOBAL_CONF_SCRATCHPAD_10
0025 #define mmGIC_HOST_INTS_IRQ_POLL_REG        mmPSOC_GLOBAL_CONF_SCRATCHPAD_11
0026 #define mmGIC_HOST_SOFT_RST_IRQ_POLL_REG    mmPSOC_GLOBAL_CONF_SCRATCHPAD_12
0027 #define mmEEPROM_COPY_LOCATION_REG      mmPSOC_GLOBAL_CONF_SCRATCHPAD_13
0028 #define mmCPU_RST_STATUS_TO_HOST        mmPSOC_GLOBAL_CONF_SCRATCHPAD_14
0029 #define mmENGINE_ARC_IRQ_CTRL_POLL_REG      mmPSOC_GLOBAL_CONF_SCRATCHPAD_15
0030 #define mmPID_CFG_REG               mmPSOC_GLOBAL_CONF_SCRATCHPAD_18
0031 /*
0032  * TODO: mmGIC_RAZWI_STATUS_REG is temporary
0033  * macro and to be removed after GAUDI2 PO
0034  */
0035 #define mmGIC_RAZWI_STATUS_REG          mmPSOC_GLOBAL_CONF_SCRATCHPAD_19
0036 #define mmCPU_BOOT_DEV_STS0         mmPSOC_GLOBAL_CONF_SCRATCHPAD_20
0037 #define mmCPU_BOOT_DEV_STS1         mmPSOC_GLOBAL_CONF_SCRATCHPAD_21
0038 #define mmCPU_CMD_STATUS_TO_HOST        mmPSOC_GLOBAL_CONF_SCRATCHPAD_23
0039 #define mmCPU_BOOT_ERR0             mmPSOC_GLOBAL_CONF_SCRATCHPAD_24
0040 #define mmCPU_BOOT_ERR1             mmPSOC_GLOBAL_CONF_SCRATCHPAD_25
0041 #define mmUPD_STS               mmPSOC_GLOBAL_CONF_SCRATCHPAD_26
0042 #define mmUPD_CMD               mmPSOC_GLOBAL_CONF_SCRATCHPAD_27
0043 #define mmUBOOT_VER_OFFSET          mmPSOC_GLOBAL_CONF_SCRATCHPAD_29
0044 #define mmRDWR_TEST             mmPSOC_GLOBAL_CONF_SCRATCHPAD_30
0045 #define mmBTL_ID                mmPSOC_GLOBAL_CONF_SCRATCHPAD_31
0046 #define mmRST_SRC               mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_0
0047 #define mmPREBOOT_PCIE_EN           mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_1
0048 #define mmCOLD_RST_DATA             mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_2
0049 #define mmUPD_PENDING_STS           mmPSOC_GLOBAL_CONF_COLD_RST_FLOPS_3
0050 #define mmPID_CMD_REQ_REG           mmPSOC_PID_PID_CMD_0
0051 #define mmPID_CMD_REQ_REG_HI            mmPSOC_PID_PID_CMD_1
0052 #define mmPID_CMD_RSP_REG           mmPSOC_PID_PID_CMD_2
0053 #define mmPID_CMD_RSP_REG_HI            mmPSOC_PID_PID_CMD_3
0054 #define mmPID_CMD_TELEMETRY_REG_0       mmPSOC_PID_PID_CMD_4
0055 #define mmPID_CMD_TELEMETRY_REG_0_HI        mmPSOC_PID_PID_CMD_5
0056 #define mmPID_CMD_TELEMETRY_REG_1       mmPSOC_PID_PID_CMD_6
0057 #define mmPID_CMD_TELEMETRY_REG_1_HI        mmPSOC_PID_PID_CMD_7
0058
0059 #endif /* GAUDI2_REG_MAP_H_ */