include/gaudi2/gaudi2_fw_if.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2019-2021 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007
0008 #ifndef GAUDI2_FW_IF_H
0009 #define GAUDI2_FW_IF_H
0010
0011 #define GAUDI2_EVENT_QUEUE_MSIX_IDX 0
0012
0013 #define UBOOT_FW_OFFSET         0x100000    /* 1MB in SRAM */
0014 #define LINUX_FW_OFFSET         0x800000    /* 8BM in DDR */
0015
0016 #define GAUDI2_PLL_FREQ_LOW     200000000 /* 200 MHz */
0017
0018 #define GAUDI2_SP_SRAM_BASE_ADDR    0x27FE0000
0019 #define GAUDI2_MAILBOX_BASE_ADDR    0x27FE1800
0020
0021 #define GAUDI2_NUM_MME          4
0022
0023 #define GAUDI2_ARCPID_TX_MB_SIZE    0x1000
0024 #define GAUDI2_ARCPID_RX_MB_SIZE    0x400
0025 #define GAUDI2_ARM_TX_MB_SIZE       0x400
0026 #define GAUDI2_ARM_RX_MB_SIZE       0x1800
0027
0028 #define GAUDI2_DCCM_BASE_ADDR       0x27020000
0029 #define GAUDI2_ARCPID_TX_MB_ADDR    GAUDI2_DCCM_BASE_ADDR
0030
0031 #define GAUDI2_ARCPID_RX_MB_ADDR    (GAUDI2_ARCPID_TX_MB_ADDR + \
0032                     GAUDI2_ARCPID_TX_MB_SIZE)
0033
0034 #define GAUDI2_ARM_TX_MB_ADDR       GAUDI2_MAILBOX_BASE_ADDR
0035
0036 #define GAUDI2_ARM_RX_MB_ADDR       (GAUDI2_ARM_TX_MB_ADDR + \
0037                     GAUDI2_ARM_TX_MB_SIZE)
0038
0039 #define GAUDI2_ARM_TX_MB_OFFSET     (GAUDI2_ARM_TX_MB_ADDR - \
0040                     GAUDI2_SP_SRAM_BASE_ADDR)
0041
0042 #define GAUDI2_ARM_RX_MB_OFFSET     (GAUDI2_ARM_RX_MB_ADDR - \
0043                     GAUDI2_SP_SRAM_BASE_ADDR)
0044
0045 enum gaudi2_fw_status {
0046     GAUDI2_PID_STATUS_UP = 0x1, /* PID on ARC0 is up */
0047     GAUDI2_ARM_STATUS_UP = 0x2, /* ARM Linux Boot complete */
0048     GAUDI2_MGMT_STATUS_UP = 0x3,    /* ARC1 Mgmt is up */
0049     GAUDI2_STATUS_LAST = 0xFF
0050 };
0051
0052 struct gaudi2_cold_rst_data {
0053     union {
0054         struct {
0055             u32 recovery_flag: 1;
0056             u32 validation_flag: 1;
0057             u32 efuse_read_flag: 1;
0058             u32 spsram_init_done : 1;
0059             u32 fake_security_enable : 1;
0060             u32 fake_sig_validation_en : 1;
0061             u32 reserved : 26;
0062         };
0063         __le32 data;
0064     };
0065 };
0066
0067 enum gaudi2_rst_src {
0068     HL_COLD_RST = 1,
0069     HL_MANUAL_RST = 2,
0070     HL_PRSTN_RST = 4,
0071     HL_SOFT_RST = 8,
0072     HL_WD_RST = 16,
0073     HL_FW_ALL_RST = 32,
0074     HL_SW_ALL_RST = 64,
0075     HL_FLR_RST = 128,
0076     HL_ECC_DERR_RST = 256
0077 };
0078
0079 struct gaudi2_redundancy_ctx {
0080     int redundant_hbm;
0081     int redundant_edma;
0082     int redundant_tpc;
0083     int redundant_vdec;
0084     __le64 hbm_mask;
0085     __le64 edma_mask;
0086     __le64 tpc_mask;
0087     __le64 vdec_mask;
0088     __le64 mme_mask;
0089     __le64 nic_mask;
0090     __le64 rtr_mask;
0091     __le64 hmmu_hif_iso;
0092     __le64 xbar_edge_iso;
0093     __le64 hmmu_hif_mask;
0094     __le64 xbar_edge_mask;
0095     __u8 mme_pe_iso[GAUDI2_NUM_MME];
0096     __le32 full_hbm_mode;   /* true on full (non binning hbm)*/
0097 } __packed;
0098
0099 #endif /* GAUDI2_FW_IF_H */