OSCL-LXR linux-6.0.1/​drivers/​misc/​habanalabs/​include/​gaudi2/​asic_reg/​pmmu_pif_regs.h	Source navigation Diff markup Identifier search General search
	Version: linux-6.0.1 spark-3.0.0 hadoop-3.2.0-src hadoop-3.3.0-src spark-2.4.7 linux-4.15.13 hadoop-2.7.4-src Revert   Change

 /* SPDX-License-Identifier: GPL-2.0
  *
  * Copyright 2016-2020 HabanaLabs, Ltd.
  * All Rights Reserved.
  *
  */
 
 /************************************
  ** This is an auto-generated file **
  **       DO NOT EDIT BELOW        **
  ************************************/
 
 #ifndef ASIC_REG_PMMU_PIF_REGS_H_
 #define ASIC_REG_PMMU_PIF_REGS_H_
 
 /*
  *****************************************
  *   PMMU_PIF
  *   (Prototype: PIF)
  *****************************************
  */
 
 #define mmPMMU_PIF_WR_CORE_CREDITS_THRESHOLD 0x4D03000
 
 #define mmPMMU_PIF_RD_CORE_CREDITS_THRESHOLD 0x4D03004
 
 #define mmPMMU_PIF_CORE_CREDITS_THRESHOLD 0x4D03008
 
 #define mmPMMU_PIF_CORE_SEPARATION_DISABLE 0x4D0300C
 
 #define mmPMMU_PIF_DISABLE_E2E_CREDITS 0x4D03010
 
 #define mmPMMU_PIF_RATE_LIMITER_ENABLE 0x4D03014
 
 #define mmPMMU_PIF_RATE_LIMITER_TOKEN_RESET 0x4D03018
 
 #define mmPMMU_PIF_RATE_LIMITER_SATURATION 0x4D0301C
 
 #define mmPMMU_PIF_RATE_LIMITER_TIMEOUT_LSB 0x4D03020
 
 #define mmPMMU_PIF_RATE_LIMITER_TIMEOUT_MSB 0x4D03024
 
 #define mmPMMU_PIF_ARB_TYPE 0x4D03028
 
 #define mmPMMU_PIF_CLOCK_GATE_CONFIG 0x4D0302C
 
 #define mmPMMU_PIF_CLOCK_GATE_ACTIVE 0x4D03030
 
 #define mmPMMU_PIF_SPI_INTERRUPT_CAUSE 0x4D03034
 
 #define mmPMMU_PIF_SPI_INTERRUPT_CAUSE_MASK 0x4D03038
 
 #define mmPMMU_PIF_SPI_INTERRUPT_REG 0x4D0303C
 
 #define mmPMMU_PIF_SPI_INTERRUPT_MASK 0x4D03040
 
 #define mmPMMU_PIF_SEI_INTERRUPT_CAUSE 0x4D03044
 
 #define mmPMMU_PIF_SEI_INTERRUPT_CAUSE_MASK 0x4D03048
 
 #define mmPMMU_PIF_SEI_INTERRUPT_REG 0x4D0304C
 
 #define mmPMMU_PIF_SEI_INTERRUPT_MASK 0x4D03050
 
 #define mmPMMU_PIF_DEBUG_BUFFER_CNT_CTRL 0x4D03054
 
 #define mmPMMU_PIF_DEBUG_WR_BUF_CNT 0x4D03058
 
 #define mmPMMU_PIF_DEBUG_RD_BUF_CNT 0x4D0305C
 
 #define mmPMMU_PIF_DEBUG_WR_CORE_BUF_CNT 0x4D03060
 
 #define mmPMMU_PIF_DEBUG_RD_CORE_BUF_CNT 0x4D03070
 
 #define mmPMMU_PIF_DEBUG_WR_BUF_FULL 0x4D03080
 
 #define mmPMMU_PIF_DEBUG_RD_BUF_FULL 0x4D03084
 
 #define mmPMMU_PIF_E2E_ROUTING_CFG 0x4D03090
 
 #define mmPMMU_PIF_E2E_ROUTING_CFG2 0x4D03094
 
 #define mmPMMU_PIF_SPI_INTERRUPT_CLEAR 0x4D03100
 
 #define mmPMMU_PIF_SEI_INTERRUPT_CLEAR 0x4D03104
 
 #define mmPMMU_PIF_BASE_ADDR_PMMU 0x4D03200
 
 #define mmPMMU_PIF_ADDR_MASK_PMMU 0x4D03204
 
 #define mmPMMU_PIF_BASE_ADDR_PCI0 0x4D03208
 
 #define mmPMMU_PIF_ADDR_MASK_PCI0 0x4D0320C
 
 #define mmPMMU_PIF_BASE_ADDR_PCI2 0x4D03210
 
 #define mmPMMU_PIF_ADDR_MASK_PCI1 0x4D03214
 
 #define mmPMMU_PIF_BASE_ADDR_PCI1 0x4D03218
 
 #define mmPMMU_PIF_ADDR_MASK_PCI2 0x4D0321C
 
 #define mmPMMU_PIF_BASE_ADDR_TPC 0x4D03220
 
 #define mmPMMU_PIF_ADDR_MASK_TPC 0x4D03224
 
 #define mmPMMU_PIF_BASE_ADDR_DEC0 0x4D03228
 
 #define mmPMMU_PIF_ADDR_MASK_DEC0 0x4D0322C
 
 #define mmPMMU_PIF_BASE_ADDR_DEC1 0x4D03230
 
 #define mmPMMU_PIF_ADDR_MASK_DEC1 0x4D03234
 
 #define mmPMMU_PIF_PMMU_DBG_BASE_ADDR 0x4D03300
 
 #define mmPMMU_PIF_PMMU_DBG_ADDR_MASK 0x4D03304
 
 #define mmPMMU_PIF_PCI_DBG_BASE_ADDR 0x4D03308
 
 #define mmPMMU_PIF_PCI_DBG_ADDR_MASK 0x4D0330C
 
 #define mmPMMU_PIF_DEC0_DBG_BASE_ADDR 0x4D03310
 
 #define mmPMMU_PIF_DEC0_DBG_ADDR_MASK 0x4D03314
 
 #define mmPMMU_PIF_DEC1_DBG_BASE_ADDR 0x4D03318
 
 #define mmPMMU_PIF_DEC1_DBG_ADDR_MASK 0x4D0331C
 
 #define mmPMMU_PIF_TPC_DBG_BASE_ADDR 0x4D03320
 
 #define mmPMMU_PIF_TPC_DBG_ADDR_MASK 0x4D03324
 
 #endif /* ASIC_REG_PMMU_PIF_REGS_H_ */

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