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0013 #ifndef ASIC_REG_PMMU_HBW_STLB_REGS_H_
0014 #define ASIC_REG_PMMU_HBW_STLB_REGS_H_
0015
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0021
0022
0023 #define mmPMMU_HBW_STLB_BUSY 0x4D01000
0024
0025 #define mmPMMU_HBW_STLB_ASID 0x4D01004
0026
0027 #define mmPMMU_HBW_STLB_HOP0_PA43_12 0x4D01008
0028
0029 #define mmPMMU_HBW_STLB_HOP0_PA63_44 0x4D0100C
0030
0031 #define mmPMMU_HBW_STLB_CACHE_INV 0x4D01010
0032
0033 #define mmPMMU_HBW_STLB_CACHE_INV_BASE_39_8 0x4D01014
0034
0035 #define mmPMMU_HBW_STLB_CACHE_INV_BASE_63_40 0x4D01018
0036
0037 #define mmPMMU_HBW_STLB_STLB_FEATURE_EN 0x4D0101C
0038
0039 #define mmPMMU_HBW_STLB_STLB_AXI_CACHE 0x4D01020
0040
0041 #define mmPMMU_HBW_STLB_HOP_CONFIGURATION 0x4D01024
0042
0043 #define mmPMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_63_32 0x4D01028
0044
0045 #define mmPMMU_HBW_STLB_LINK_LIST_LOOKUP_MASK_31_0 0x4D0102C
0046
0047 #define mmPMMU_HBW_STLB_INV_ALL_START 0x4D01034
0048
0049 #define mmPMMU_HBW_STLB_INV_ALL_SET 0x4D01038
0050
0051 #define mmPMMU_HBW_STLB_INV_PS 0x4D0103C
0052
0053 #define mmPMMU_HBW_STLB_INV_CONSUMER_INDEX 0x4D01040
0054
0055 #define mmPMMU_HBW_STLB_INV_HIT_COUNT 0x4D01044
0056
0057 #define mmPMMU_HBW_STLB_INV_SET 0x4D01048
0058
0059 #define mmPMMU_HBW_STLB_SRAM_INIT 0x4D0104C
0060
0061 #define mmPMMU_HBW_STLB_MEM_CACHE_INVALIDATION 0x4D01050
0062
0063 #define mmPMMU_HBW_STLB_MEM_CACHE_INV_STATUS 0x4D01054
0064
0065 #define mmPMMU_HBW_STLB_MEM_CACHE_BASE_38_7 0x4D01058
0066
0067 #define mmPMMU_HBW_STLB_MEM_CACHE_BASE_63_39 0x4D0105C
0068
0069 #define mmPMMU_HBW_STLB_MEM_CACHE_CONFIG 0x4D01060
0070
0071 #define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP5 0x4D01064
0072
0073 #define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP4 0x4D01068
0074
0075 #define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP3 0x4D0106C
0076
0077 #define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP2 0x4D01070
0078
0079 #define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP1 0x4D01074
0080
0081 #define mmPMMU_HBW_STLB_SET_THRESHOLD_HOP0 0x4D01078
0082
0083 #define mmPMMU_HBW_STLB_MULTI_HIT_INTERRUPT_CLR 0x4D0107C
0084
0085 #define mmPMMU_HBW_STLB_MULTI_HIT_INTERRUPT_MASK 0x4D01080
0086
0087 #define mmPMMU_HBW_STLB_MEM_L0_CACHE_CFG 0x4D01084
0088
0089 #define mmPMMU_HBW_STLB_MEM_READ_ARPROT 0x4D01088
0090
0091 #define mmPMMU_HBW_STLB_RANGE_CACHE_INVALIDATION 0x4D0108C
0092
0093 #define mmPMMU_HBW_STLB_RANGE_INV_START_LSB 0x4D01090
0094
0095 #define mmPMMU_HBW_STLB_RANGE_INV_START_MSB 0x4D01094
0096
0097 #define mmPMMU_HBW_STLB_RANGE_INV_END_LSB 0x4D01098
0098
0099 #define mmPMMU_HBW_STLB_RANGE_INV_END_MSB 0x4D0109C
0100
0101 #define mmPMMU_HBW_STLB_ASID_SCRAMBLER_CTRL 0x4D01100
0102
0103 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_0 0x4D01104
0104
0105 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_1 0x4D01108
0106
0107 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_2 0x4D0110C
0108
0109 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_3 0x4D01110
0110
0111 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_4 0x4D01114
0112
0113 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_5 0x4D01118
0114
0115 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_6 0x4D0111C
0116
0117 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_7 0x4D01120
0118
0119 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_8 0x4D01124
0120
0121 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MATRIX_H3_9 0x4D01128
0122
0123 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_10 0x4D0112C
0124
0125 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_11 0x4D01130
0126
0127 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_12 0x4D01134
0128
0129 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_13 0x4D01138
0130
0131 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_14 0x4D0113C
0132
0133 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_15 0x4D01140
0134
0135 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_16 0x4D01144
0136
0137 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_17 0x4D01148
0138
0139 #define mmPMMU_HBW_STLB_ASID_SCR_POLY_MAT_H3_18 0x4D0114C
0140
0141 #endif