Back to home page

OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2016-2020 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007 
0008 /************************************
0009  ** This is an auto-generated file **
0010  **       DO NOT EDIT BELOW        **
0011  ************************************/
0012 
0013 #ifndef ASIC_REG_NIC0_QPC0_REGS_H_
0014 #define ASIC_REG_NIC0_QPC0_REGS_H_
0015 
0016 /*
0017  *****************************************
0018  *   NIC0_QPC0
0019  *   (Prototype: NIC_QPC)
0020  *****************************************
0021  */
0022 
0023 #define mmNIC0_QPC0_REQ_QPC_CACHE_INVALIDATE 0x541F000
0024 
0025 #define mmNIC0_QPC0_REQ_QPC_CACHE_INV_STATUS 0x541F004
0026 
0027 #define mmNIC0_QPC0_REQ_STATIC_CONFIG 0x541F008
0028 
0029 #define mmNIC0_QPC0_REQ_BASE_ADDRESS_63_32 0x541F00C
0030 
0031 #define mmNIC0_QPC0_REQ_BASE_ADDRESS_31_7 0x541F010
0032 
0033 #define mmNIC0_QPC0_REQ_CLEAN_LINK_LIST 0x541F014
0034 
0035 #define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_63_32 0x541F018
0036 
0037 #define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_31_0 0x541F01C
0038 
0039 #define mmNIC0_QPC0_REQ_ERR_QP_STATE_63_32 0x541F020
0040 
0041 #define mmNIC0_QPC0_REQ_ERR_QP_STATE_31_0 0x541F024
0042 
0043 #define mmNIC0_QPC0_RETRY_COUNT_MAX 0x541F028
0044 
0045 #define mmNIC0_QPC0_AXI_PROT 0x541F030
0046 
0047 #define mmNIC0_QPC0_RES_QPC_CACHE_INVALIDATE 0x541F034
0048 
0049 #define mmNIC0_QPC0_RES_QPC_CACHE_INV_STATUS 0x541F038
0050 
0051 #define mmNIC0_QPC0_RES_STATIC_CONFIG 0x541F03C
0052 
0053 #define mmNIC0_QPC0_RES_BASE_ADDRESS_63_32 0x541F040
0054 
0055 #define mmNIC0_QPC0_RES_BASE_ADDRESS_31_7 0x541F044
0056 
0057 #define mmNIC0_QPC0_RES_CLEAN_LINK_LIST 0x541F048
0058 
0059 #define mmNIC0_QPC0_ERR_FIFO_WRITE_INDEX 0x541F050
0060 
0061 #define mmNIC0_QPC0_ERR_FIFO_PRODUCER_INDEX 0x541F054
0062 
0063 #define mmNIC0_QPC0_ERR_FIFO_CONSUMER_INDEX 0x541F058
0064 
0065 #define mmNIC0_QPC0_ERR_FIFO_MASK 0x541F05C
0066 
0067 #define mmNIC0_QPC0_ERR_FIFO_CREDIT 0x541F060
0068 
0069 #define mmNIC0_QPC0_ERR_FIFO_CFG 0x541F064
0070 
0071 #define mmNIC0_QPC0_ERR_FIFO_INTR_MASK 0x541F068
0072 
0073 #define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_63_32 0x541F06C
0074 
0075 #define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_31_7 0x541F070
0076 
0077 #define mmNIC0_QPC0_GW_BUSY 0x541F080
0078 
0079 #define mmNIC0_QPC0_GW_CTRL 0x541F084
0080 
0081 #define mmNIC0_QPC0_GW_DATA_0 0x541F08C
0082 
0083 #define mmNIC0_QPC0_GW_DATA_1 0x541F090
0084 
0085 #define mmNIC0_QPC0_GW_DATA_2 0x541F094
0086 
0087 #define mmNIC0_QPC0_GW_DATA_3 0x541F098
0088 
0089 #define mmNIC0_QPC0_GW_DATA_4 0x541F09C
0090 
0091 #define mmNIC0_QPC0_GW_DATA_5 0x541F0A0
0092 
0093 #define mmNIC0_QPC0_GW_DATA_6 0x541F0A4
0094 
0095 #define mmNIC0_QPC0_GW_DATA_7 0x541F0A8
0096 
0097 #define mmNIC0_QPC0_GW_DATA_8 0x541F0AC
0098 
0099 #define mmNIC0_QPC0_GW_DATA_9 0x541F0B0
0100 
0101 #define mmNIC0_QPC0_GW_DATA_10 0x541F0B4
0102 
0103 #define mmNIC0_QPC0_GW_DATA_11 0x541F0B8
0104 
0105 #define mmNIC0_QPC0_GW_DATA_12 0x541F0BC
0106 
0107 #define mmNIC0_QPC0_GW_DATA_13 0x541F0C0
0108 
0109 #define mmNIC0_QPC0_GW_DATA_14 0x541F0C4
0110 
0111 #define mmNIC0_QPC0_GW_DATA_15 0x541F0C8
0112 
0113 #define mmNIC0_QPC0_GW_DATA_16 0x541F0CC
0114 
0115 #define mmNIC0_QPC0_GW_DATA_17 0x541F0D0
0116 
0117 #define mmNIC0_QPC0_GW_DATA_18 0x541F0D4
0118 
0119 #define mmNIC0_QPC0_GW_DATA_19 0x541F0D8
0120 
0121 #define mmNIC0_QPC0_GW_DATA_20 0x541F0DC
0122 
0123 #define mmNIC0_QPC0_GW_DATA_21 0x541F0E0
0124 
0125 #define mmNIC0_QPC0_GW_DATA_22 0x541F0E4
0126 
0127 #define mmNIC0_QPC0_GW_DATA_23 0x541F0E8
0128 
0129 #define mmNIC0_QPC0_GW_DATA_24 0x541F0EC
0130 
0131 #define mmNIC0_QPC0_GW_DATA_25 0x541F0F0
0132 
0133 #define mmNIC0_QPC0_GW_DATA_26 0x541F0F4
0134 
0135 #define mmNIC0_QPC0_GW_DATA_27 0x541F0F8
0136 
0137 #define mmNIC0_QPC0_GW_DATA_28 0x541F0FC
0138 
0139 #define mmNIC0_QPC0_GW_DATA_29 0x541F100
0140 
0141 #define mmNIC0_QPC0_GW_DATA_30 0x541F104
0142 
0143 #define mmNIC0_QPC0_GW_DATA_31 0x541F108
0144 
0145 #define mmNIC0_QPC0_GW_MASK_0 0x541F124
0146 
0147 #define mmNIC0_QPC0_GW_MASK_1 0x541F128
0148 
0149 #define mmNIC0_QPC0_GW_MASK_2 0x541F12C
0150 
0151 #define mmNIC0_QPC0_GW_MASK_3 0x541F130
0152 
0153 #define mmNIC0_QPC0_GW_MASK_4 0x541F134
0154 
0155 #define mmNIC0_QPC0_GW_MASK_5 0x541F138
0156 
0157 #define mmNIC0_QPC0_GW_MASK_6 0x541F13C
0158 
0159 #define mmNIC0_QPC0_GW_MASK_7 0x541F140
0160 
0161 #define mmNIC0_QPC0_GW_MASK_8 0x541F144
0162 
0163 #define mmNIC0_QPC0_GW_MASK_9 0x541F148
0164 
0165 #define mmNIC0_QPC0_GW_MASK_10 0x541F14C
0166 
0167 #define mmNIC0_QPC0_GW_MASK_11 0x541F150
0168 
0169 #define mmNIC0_QPC0_GW_MASK_12 0x541F154
0170 
0171 #define mmNIC0_QPC0_GW_MASK_13 0x541F158
0172 
0173 #define mmNIC0_QPC0_GW_MASK_14 0x541F15C
0174 
0175 #define mmNIC0_QPC0_GW_MASK_15 0x541F160
0176 
0177 #define mmNIC0_QPC0_GW_MASK_16 0x541F164
0178 
0179 #define mmNIC0_QPC0_GW_MASK_17 0x541F168
0180 
0181 #define mmNIC0_QPC0_GW_MASK_18 0x541F16C
0182 
0183 #define mmNIC0_QPC0_GW_MASK_19 0x541F170
0184 
0185 #define mmNIC0_QPC0_GW_MASK_20 0x541F174
0186 
0187 #define mmNIC0_QPC0_GW_MASK_21 0x541F178
0188 
0189 #define mmNIC0_QPC0_GW_MASK_22 0x541F17C
0190 
0191 #define mmNIC0_QPC0_GW_MASK_23 0x541F180
0192 
0193 #define mmNIC0_QPC0_GW_MASK_24 0x541F184
0194 
0195 #define mmNIC0_QPC0_GW_MASK_25 0x541F188
0196 
0197 #define mmNIC0_QPC0_GW_MASK_26 0x541F18C
0198 
0199 #define mmNIC0_QPC0_GW_MASK_27 0x541F190
0200 
0201 #define mmNIC0_QPC0_GW_MASK_28 0x541F194
0202 
0203 #define mmNIC0_QPC0_GW_MASK_29 0x541F198
0204 
0205 #define mmNIC0_QPC0_GW_MASK_30 0x541F19C
0206 
0207 #define mmNIC0_QPC0_GW_MASK_31 0x541F1A0
0208 
0209 #define mmNIC0_QPC0_CC_TIMEOUT 0x541F1B0
0210 
0211 #define mmNIC0_QPC0_CC_WINDOW_INC_EN 0x541F1FC
0212 
0213 #define mmNIC0_QPC0_CC_TICK_WRAP 0x541F200
0214 
0215 #define mmNIC0_QPC0_CC_ROLLBACK 0x541F204
0216 
0217 #define mmNIC0_QPC0_CC_MAX_WINDOW_SIZE 0x541F208
0218 
0219 #define mmNIC0_QPC0_CC_MIN_WINDOW_SIZE 0x541F20C
0220 
0221 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_0 0x541F210
0222 
0223 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_1 0x541F214
0224 
0225 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_2 0x541F218
0226 
0227 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_3 0x541F21C
0228 
0229 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_4 0x541F220
0230 
0231 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_5 0x541F224
0232 
0233 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_6 0x541F228
0234 
0235 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_7 0x541F22C
0236 
0237 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_8 0x541F230
0238 
0239 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_9 0x541F234
0240 
0241 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_10 0x541F238
0242 
0243 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_11 0x541F23C
0244 
0245 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_12 0x541F240
0246 
0247 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_13 0x541F244
0248 
0249 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_14 0x541F248
0250 
0251 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_15 0x541F24C
0252 
0253 #define mmNIC0_QPC0_CC_ALPHA_LOG_0 0x541F250
0254 
0255 #define mmNIC0_QPC0_CC_ALPHA_LOG_1 0x541F254
0256 
0257 #define mmNIC0_QPC0_CC_ALPHA_LOG_2 0x541F258
0258 
0259 #define mmNIC0_QPC0_CC_ALPHA_LOG_3 0x541F25C
0260 
0261 #define mmNIC0_QPC0_CC_ALPHA_LOG_4 0x541F260
0262 
0263 #define mmNIC0_QPC0_CC_ALPHA_LOG_5 0x541F264
0264 
0265 #define mmNIC0_QPC0_CC_ALPHA_LOG_6 0x541F268
0266 
0267 #define mmNIC0_QPC0_CC_ALPHA_LOG_7 0x541F26C
0268 
0269 #define mmNIC0_QPC0_CC_ALPHA_LOG_8 0x541F270
0270 
0271 #define mmNIC0_QPC0_CC_ALPHA_LOG_9 0x541F274
0272 
0273 #define mmNIC0_QPC0_CC_ALPHA_LOG_10 0x541F278
0274 
0275 #define mmNIC0_QPC0_CC_ALPHA_LOG_11 0x541F27C
0276 
0277 #define mmNIC0_QPC0_CC_ALPHA_LOG_12 0x541F280
0278 
0279 #define mmNIC0_QPC0_CC_ALPHA_LOG_13 0x541F284
0280 
0281 #define mmNIC0_QPC0_CC_ALPHA_LOG_14 0x541F288
0282 
0283 #define mmNIC0_QPC0_CC_ALPHA_LOG_15 0x541F28C
0284 
0285 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_0 0x541F290
0286 
0287 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_1 0x541F294
0288 
0289 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_2 0x541F298
0290 
0291 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_3 0x541F29C
0292 
0293 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_4 0x541F2A0
0294 
0295 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_5 0x541F2A4
0296 
0297 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_6 0x541F2A8
0298 
0299 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_7 0x541F2AC
0300 
0301 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_8 0x541F2B0
0302 
0303 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_9 0x541F2B4
0304 
0305 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_10 0x541F2B8
0306 
0307 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_11 0x541F2BC
0308 
0309 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_12 0x541F2C0
0310 
0311 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_13 0x541F2C4
0312 
0313 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_14 0x541F2C8
0314 
0315 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_15 0x541F2CC
0316 
0317 #define mmNIC0_QPC0_CC_WINDOW_INC_0 0x541F2D0
0318 
0319 #define mmNIC0_QPC0_CC_WINDOW_INC_1 0x541F2D4
0320 
0321 #define mmNIC0_QPC0_CC_WINDOW_INC_2 0x541F2D8
0322 
0323 #define mmNIC0_QPC0_CC_WINDOW_INC_3 0x541F2DC
0324 
0325 #define mmNIC0_QPC0_CC_WINDOW_INC_4 0x541F2E0
0326 
0327 #define mmNIC0_QPC0_CC_WINDOW_INC_5 0x541F2E4
0328 
0329 #define mmNIC0_QPC0_CC_WINDOW_INC_6 0x541F2E8
0330 
0331 #define mmNIC0_QPC0_CC_WINDOW_INC_7 0x541F2EC
0332 
0333 #define mmNIC0_QPC0_CC_WINDOW_INC_8 0x541F2F0
0334 
0335 #define mmNIC0_QPC0_CC_WINDOW_INC_9 0x541F2F4
0336 
0337 #define mmNIC0_QPC0_CC_WINDOW_INC_10 0x541F2F8
0338 
0339 #define mmNIC0_QPC0_CC_WINDOW_INC_11 0x541F2FC
0340 
0341 #define mmNIC0_QPC0_CC_WINDOW_INC_12 0x541F300
0342 
0343 #define mmNIC0_QPC0_CC_WINDOW_INC_13 0x541F304
0344 
0345 #define mmNIC0_QPC0_CC_WINDOW_INC_14 0x541F308
0346 
0347 #define mmNIC0_QPC0_CC_WINDOW_INC_15 0x541F30C
0348 
0349 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_0 0x541F310
0350 
0351 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_1 0x541F314
0352 
0353 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_2 0x541F318
0354 
0355 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_3 0x541F31C
0356 
0357 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_4 0x541F320
0358 
0359 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_5 0x541F324
0360 
0361 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_6 0x541F328
0362 
0363 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_7 0x541F32C
0364 
0365 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_8 0x541F330
0366 
0367 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_9 0x541F334
0368 
0369 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_10 0x541F338
0370 
0371 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_11 0x541F33C
0372 
0373 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_12 0x541F340
0374 
0375 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_13 0x541F344
0376 
0377 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_14 0x541F348
0378 
0379 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_15 0x541F34C
0380 
0381 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_0 0x541F360
0382 
0383 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_1 0x541F364
0384 
0385 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_2 0x541F368
0386 
0387 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_3 0x541F36C
0388 
0389 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_4 0x541F370
0390 
0391 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_5 0x541F374
0392 
0393 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_6 0x541F378
0394 
0395 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_7 0x541F37C
0396 
0397 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_8 0x541F380
0398 
0399 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_9 0x541F384
0400 
0401 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_10 0x541F388
0402 
0403 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_11 0x541F38C
0404 
0405 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_12 0x541F390
0406 
0407 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_13 0x541F394
0408 
0409 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_14 0x541F398
0410 
0411 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_15 0x541F39C
0412 
0413 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_16 0x541F3A0
0414 
0415 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_17 0x541F3A4
0416 
0417 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_18 0x541F3A8
0418 
0419 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_19 0x541F3AC
0420 
0421 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_20 0x541F3B0
0422 
0423 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_21 0x541F3B4
0424 
0425 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_22 0x541F3B8
0426 
0427 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_23 0x541F3BC
0428 
0429 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_24 0x541F3C0
0430 
0431 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_25 0x541F3C4
0432 
0433 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_26 0x541F3C8
0434 
0435 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_27 0x541F3CC
0436 
0437 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_28 0x541F3D0
0438 
0439 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_29 0x541F3D4
0440 
0441 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_30 0x541F3D8
0442 
0443 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_31 0x541F3DC
0444 
0445 #define mmNIC0_QPC0_DB_FIFO_CFG_0 0x541F3E0
0446 
0447 #define mmNIC0_QPC0_DB_FIFO_CFG_1 0x541F3E4
0448 
0449 #define mmNIC0_QPC0_DB_FIFO_CFG_2 0x541F3E8
0450 
0451 #define mmNIC0_QPC0_DB_FIFO_CFG_3 0x541F3EC
0452 
0453 #define mmNIC0_QPC0_DB_FIFO_CFG_4 0x541F3F0
0454 
0455 #define mmNIC0_QPC0_DB_FIFO_CFG_5 0x541F3F4
0456 
0457 #define mmNIC0_QPC0_DB_FIFO_CFG_6 0x541F3F8
0458 
0459 #define mmNIC0_QPC0_DB_FIFO_CFG_7 0x541F3FC
0460 
0461 #define mmNIC0_QPC0_DB_FIFO_CFG_8 0x541F400
0462 
0463 #define mmNIC0_QPC0_DB_FIFO_CFG_9 0x541F404
0464 
0465 #define mmNIC0_QPC0_DB_FIFO_CFG_10 0x541F408
0466 
0467 #define mmNIC0_QPC0_DB_FIFO_CFG_11 0x541F40C
0468 
0469 #define mmNIC0_QPC0_DB_FIFO_CFG_12 0x541F410
0470 
0471 #define mmNIC0_QPC0_DB_FIFO_CFG_13 0x541F414
0472 
0473 #define mmNIC0_QPC0_DB_FIFO_CFG_14 0x541F418
0474 
0475 #define mmNIC0_QPC0_DB_FIFO_CFG_15 0x541F41C
0476 
0477 #define mmNIC0_QPC0_DB_FIFO_CFG_16 0x541F420
0478 
0479 #define mmNIC0_QPC0_DB_FIFO_CFG_17 0x541F424
0480 
0481 #define mmNIC0_QPC0_DB_FIFO_CFG_18 0x541F428
0482 
0483 #define mmNIC0_QPC0_DB_FIFO_CFG_19 0x541F42C
0484 
0485 #define mmNIC0_QPC0_DB_FIFO_CFG_20 0x541F430
0486 
0487 #define mmNIC0_QPC0_DB_FIFO_CFG_21 0x541F434
0488 
0489 #define mmNIC0_QPC0_DB_FIFO_CFG_22 0x541F438
0490 
0491 #define mmNIC0_QPC0_DB_FIFO_CFG_23 0x541F43C
0492 
0493 #define mmNIC0_QPC0_DB_FIFO_CFG_24 0x541F440
0494 
0495 #define mmNIC0_QPC0_DB_FIFO_CFG_25 0x541F444
0496 
0497 #define mmNIC0_QPC0_DB_FIFO_CFG_26 0x541F448
0498 
0499 #define mmNIC0_QPC0_DB_FIFO_CFG_27 0x541F44C
0500 
0501 #define mmNIC0_QPC0_DB_FIFO_CFG_28 0x541F450
0502 
0503 #define mmNIC0_QPC0_DB_FIFO_CFG_29 0x541F454
0504 
0505 #define mmNIC0_QPC0_DB_FIFO_CFG_30 0x541F458
0506 
0507 #define mmNIC0_QPC0_DB_FIFO_CFG_31 0x541F45C
0508 
0509 #define mmNIC0_QPC0_SECURED_DB_FIRST32 0x541F460
0510 
0511 #define mmNIC0_QPC0_SECURED_DB_SECOND32 0x541F464
0512 
0513 #define mmNIC0_QPC0_SECURED_DB_THIRD32 0x541F468
0514 
0515 #define mmNIC0_QPC0_SECURED_DB_FOURTH32 0x541F46C
0516 
0517 #define mmNIC0_QPC0_PRIVILEGE_DB_FIRST32 0x541F470
0518 
0519 #define mmNIC0_QPC0_PRIVILEGE_DB_SECOND32 0x541F474
0520 
0521 #define mmNIC0_QPC0_PRIVILEGE_DB_THIRD32 0x541F478
0522 
0523 #define mmNIC0_QPC0_PRIVILEGE_DB_FOURTH32 0x541F47C
0524 
0525 #define mmNIC0_QPC0_DBG_INDICATION 0x541F480
0526 
0527 #define mmNIC0_QPC0_WTD_WC_FSM 0x541F484
0528 
0529 #define mmNIC0_QPC0_WTD_SLICE_FSM 0x541F488
0530 
0531 #define mmNIC0_QPC0_REQ_TX_EMPTY_CNT 0x541F48C
0532 
0533 #define mmNIC0_QPC0_RES_TX_EMPTY_CNT 0x541F490
0534 
0535 #define mmNIC0_QPC0_NUM_ROLLBACKS 0x541F494
0536 
0537 #define mmNIC0_QPC0_LAST_QP_ROLLED_BACK 0x541F498
0538 
0539 #define mmNIC0_QPC0_NUM_TIMEOUTS 0x541F49C
0540 
0541 #define mmNIC0_QPC0_LAST_QP_TIMED_OUT 0x541F4A0
0542 
0543 #define mmNIC0_QPC0_WTD_SLICE_FSM_HI 0x541F4A4
0544 
0545 #define mmNIC0_QPC0_INTERRUPT_BASE_0 0x541F4B0
0546 
0547 #define mmNIC0_QPC0_INTERRUPT_BASE_1 0x541F4B4
0548 
0549 #define mmNIC0_QPC0_INTERRUPT_BASE_2 0x541F4B8
0550 
0551 #define mmNIC0_QPC0_INTERRUPT_BASE_3 0x541F4BC
0552 
0553 #define mmNIC0_QPC0_INTERRUPT_BASE_4 0x541F4C0
0554 
0555 #define mmNIC0_QPC0_INTERRUPT_BASE_5 0x541F4C4
0556 
0557 #define mmNIC0_QPC0_INTERRUPT_BASE_6 0x541F4C8
0558 
0559 #define mmNIC0_QPC0_INTERRUPT_BASE_7 0x541F4CC
0560 
0561 #define mmNIC0_QPC0_INTERRUPT_BASE_8 0x541F4D0
0562 
0563 #define mmNIC0_QPC0_INTERRUPT_BASE_9 0x541F4D4
0564 
0565 #define mmNIC0_QPC0_INTERRUPT_BASE_10 0x541F4D8
0566 
0567 #define mmNIC0_QPC0_INTERRUPT_DATA_0 0x541F4DC
0568 
0569 #define mmNIC0_QPC0_INTERRUPT_DATA_1 0x541F4E0
0570 
0571 #define mmNIC0_QPC0_INTERRUPT_DATA_2 0x541F4E4
0572 
0573 #define mmNIC0_QPC0_INTERRUPT_DATA_3 0x541F4E8
0574 
0575 #define mmNIC0_QPC0_INTERRUPT_DATA_4 0x541F4EC
0576 
0577 #define mmNIC0_QPC0_INTERRUPT_DATA_5 0x541F4F0
0578 
0579 #define mmNIC0_QPC0_INTERRUPT_DATA_6 0x541F4F4
0580 
0581 #define mmNIC0_QPC0_INTERRUPT_DATA_7 0x541F4F8
0582 
0583 #define mmNIC0_QPC0_INTERRUPT_DATA_8 0x541F4FC
0584 
0585 #define mmNIC0_QPC0_INTERRUPT_DATA_9 0x541F500
0586 
0587 #define mmNIC0_QPC0_INTERRUPT_DATA_10 0x541F504
0588 
0589 #define mmNIC0_QPC0_DBG_COUNT_SELECT_0 0x541F600
0590 
0591 #define mmNIC0_QPC0_DBG_COUNT_SELECT_1 0x541F604
0592 
0593 #define mmNIC0_QPC0_DBG_COUNT_SELECT_2 0x541F608
0594 
0595 #define mmNIC0_QPC0_DBG_COUNT_SELECT_3 0x541F60C
0596 
0597 #define mmNIC0_QPC0_DBG_COUNT_SELECT_4 0x541F610
0598 
0599 #define mmNIC0_QPC0_DBG_COUNT_SELECT_5 0x541F614
0600 
0601 #define mmNIC0_QPC0_DBG_COUNT_SELECT_6 0x541F618
0602 
0603 #define mmNIC0_QPC0_DBG_COUNT_SELECT_7 0x541F61C
0604 
0605 #define mmNIC0_QPC0_DBG_COUNT_SELECT_8 0x541F620
0606 
0607 #define mmNIC0_QPC0_DBG_COUNT_SELECT_9 0x541F624
0608 
0609 #define mmNIC0_QPC0_DBG_COUNT_SELECT_10 0x541F628
0610 
0611 #define mmNIC0_QPC0_DBG_COUNT_SELECT_11 0x541F62C
0612 
0613 #define mmNIC0_QPC0_DOORBELL_SECURITY 0x541F648
0614 
0615 #define mmNIC0_QPC0_DBG_CFG 0x541F64C
0616 
0617 #define mmNIC0_QPC0_RES_RING0_PI 0x541F650
0618 
0619 #define mmNIC0_QPC0_RES_RING0_CI 0x541F654
0620 
0621 #define mmNIC0_QPC0_RES_RING0_CFG 0x541F658
0622 
0623 #define mmNIC0_QPC0_RES_RING1_PI 0x541F65C
0624 
0625 #define mmNIC0_QPC0_RES_RING1_CI 0x541F660
0626 
0627 #define mmNIC0_QPC0_RES_RING1_CFG 0x541F664
0628 
0629 #define mmNIC0_QPC0_RES_RING2_PI 0x541F668
0630 
0631 #define mmNIC0_QPC0_RES_RING2_CI 0x541F66C
0632 
0633 #define mmNIC0_QPC0_RES_RING2_CFG 0x541F670
0634 
0635 #define mmNIC0_QPC0_RES_RING3_PI 0x541F674
0636 
0637 #define mmNIC0_QPC0_RES_RING3_CI 0x541F678
0638 
0639 #define mmNIC0_QPC0_RES_RING3_CFG 0x541F67C
0640 
0641 #define mmNIC0_QPC0_REQ_RING0_CI 0x541F680
0642 
0643 #define mmNIC0_QPC0_REQ_RING1_CI 0x541F684
0644 
0645 #define mmNIC0_QPC0_REQ_RING2_CI 0x541F688
0646 
0647 #define mmNIC0_QPC0_REQ_RING3_CI 0x541F68C
0648 
0649 #define mmNIC0_QPC0_INTERRUPT_CAUSE 0x541F690
0650 
0651 #define mmNIC0_QPC0_INTERRUPT_MASK 0x541F694
0652 
0653 #define mmNIC0_QPC0_INTERRUPT_CLR 0x541F698
0654 
0655 #define mmNIC0_QPC0_INTERRUPT_EN 0x541F69C
0656 
0657 #define mmNIC0_QPC0_INTERRUPT_CFG 0x541F6F0
0658 
0659 #define mmNIC0_QPC0_INTERRUPT_RESP_ERR_CAUSE 0x541F6F4
0660 
0661 #define mmNIC0_QPC0_INTERRUPT_RESP_ERR_MASK 0x541F6F8
0662 
0663 #define mmNIC0_QPC0_INTERRUPR_RESP_ERR_CLR 0x541F700
0664 
0665 #define mmNIC0_QPC0_TMR_GW_VALID 0x541F704
0666 
0667 #define mmNIC0_QPC0_TMR_GW_DATA0 0x541F708
0668 
0669 #define mmNIC0_QPC0_TMR_GW_DATA1 0x541F70C
0670 
0671 #define mmNIC0_QPC0_RNR_RETRY_COUNT_EN 0x541F710
0672 
0673 #define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32 0x541F830
0674 
0675 #define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7 0x541F834
0676 
0677 #define mmNIC0_QPC0_EVENT_QUE_LOG_SIZE 0x541F838
0678 
0679 #define mmNIC0_QPC0_EVENT_QUE_WRITE_INDEX 0x541F83C
0680 
0681 #define mmNIC0_QPC0_EVENT_QUE_PRODUCER_INDEX 0x541F840
0682 
0683 #define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_63_32 0x541F844
0684 
0685 #define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_31_7 0x541F848
0686 
0687 #define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB 0x541F84C
0688 
0689 #define mmNIC0_QPC0_EVENT_QUE_CFG 0x541F850
0690 
0691 #define mmNIC0_QPC0_LBW_PROT 0x541F858
0692 
0693 #define mmNIC0_QPC0_MEM_WRITE_INIT 0x541F85C
0694 
0695 #define mmNIC0_QPC0_QMAN_DOORBELL 0x541F8E8
0696 
0697 #define mmNIC0_QPC0_QMAN_DOORBELL_QPN 0x541F8EC
0698 
0699 #define mmNIC0_QPC0_SECURED_CQ_NUMBER 0x541F8F0
0700 
0701 #define mmNIC0_QPC0_SECURED_CQ_CONSUMER_INDEX 0x541F8F4
0702 
0703 #define mmNIC0_QPC0_PRIVILEGE_CQ_NUMBER 0x541F8F8
0704 
0705 #define mmNIC0_QPC0_PRIVILEGE_CQ_CONSUMER_INDEX 0x541F8FC
0706 
0707 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_0 0x541F900
0708 
0709 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_1 0x541F904
0710 
0711 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_2 0x541F908
0712 
0713 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_3 0x541F90C
0714 
0715 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_0 0x541F910
0716 
0717 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_1 0x541F914
0718 
0719 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_2 0x541F918
0720 
0721 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_3 0x541F91C
0722 
0723 #define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_0 0x541F920
0724 
0725 #define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_1 0x541F924
0726 
0727 #define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_2 0x541F928
0728 
0729 #define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_3 0x541F92C
0730 
0731 #define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_0 0x541F930
0732 
0733 #define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_1 0x541F934
0734 
0735 #define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_2 0x541F938
0736 
0737 #define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_3 0x541F93C
0738 
0739 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_0 0x541F940
0740 
0741 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_1 0x541F944
0742 
0743 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_2 0x541F948
0744 
0745 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_3 0x541F94C
0746 
0747 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_0 0x541F950
0748 
0749 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_1 0x541F954
0750 
0751 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_2 0x541F958
0752 
0753 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_3 0x541F95C
0754 
0755 #define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_0 0x541F960
0756 
0757 #define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_1 0x541F964
0758 
0759 #define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_2 0x541F968
0760 
0761 #define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_3 0x541F96C
0762 
0763 #define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_0 0x541F970
0764 
0765 #define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_1 0x541F974
0766 
0767 #define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_2 0x541F978
0768 
0769 #define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_3 0x541F97C
0770 
0771 #define mmNIC0_QPC0_WQE_MEM_WRITE_AXI_PROT 0x541F980
0772 
0773 #define mmNIC0_QPC0_WQ_UPPER_THRESHOLD 0x541F984
0774 
0775 #define mmNIC0_QPC0_WQ_LOWER_THRESHOLD 0x541F988
0776 
0777 #define mmNIC0_QPC0_WQ_BP_2ARC_ADDR 0x541F98C
0778 
0779 #define mmNIC0_QPC0_WQ_BP_2QMAN_ADDR 0x541F990
0780 
0781 #define mmNIC0_QPC0_WTD_CONFIG 0x541F994
0782 
0783 #define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_63_32 0x541F998
0784 
0785 #define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_31_0 0x541F99C
0786 
0787 #define mmNIC0_QPC0_REQTX_ERR_QP_STATE_63_32 0x541F9A0
0788 
0789 #define mmNIC0_QPC0_REQTX_ERR_QP_STATE_31_0 0x541F9A4
0790 
0791 #define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX 0x541F9A8
0792 
0793 #define mmNIC0_QPC0_ARM_CQ_NUM 0x541F9AC
0794 
0795 #define mmNIC0_QPC0_ARM_CQ_INDEX 0x541F9B0
0796 
0797 #define mmNIC0_QPC0_QPC_CLOCK_GATE 0x541F9B4
0798 
0799 #define mmNIC0_QPC0_QPC_CLOCK_GATE_DIS 0x541F9B8
0800 
0801 #define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_63_32 0x541F9BC
0802 
0803 #define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_31_7 0x541F9C0
0804 
0805 #define mmNIC0_QPC0_CONG_QUE_LOG_SIZE 0x541F9C4
0806 
0807 #define mmNIC0_QPC0_CONG_QUE_WRITE_INDEX 0x541F9C8
0808 
0809 #define mmNIC0_QPC0_CONG_QUE_PRODUCER_INDEX 0x541F9CC
0810 
0811 #define mmNIC0_QPC0_CONG_QUE_PI_ADDR_63_32 0x541F9D0
0812 
0813 #define mmNIC0_QPC0_CONG_QUE_PI_ADDR_31_7 0x541F9D4
0814 
0815 #define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB 0x541F9D8
0816 
0817 #define mmNIC0_QPC0_CONG_QUE_CFG 0x541F9DC
0818 
0819 #define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX 0x541F9E0
0820 
0821 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_0 0x541FA00
0822 
0823 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_1 0x541FA04
0824 
0825 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_2 0x541FA08
0826 
0827 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_3 0x541FA0C
0828 
0829 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_4 0x541FA10
0830 
0831 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_5 0x541FA14
0832 
0833 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_6 0x541FA18
0834 
0835 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_7 0x541FA1C
0836 
0837 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_8 0x541FA20
0838 
0839 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_9 0x541FA24
0840 
0841 #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0 0x541FA40
0842 
0843 #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1 0x541FA44
0844 
0845 #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2 0x541FA48
0846 
0847 #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3 0x541FA4C
0848 
0849 #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4 0x541FA50
0850 
0851 #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5 0x541FA54
0852 
0853 #define mmNIC0_QPC0_LINEAR_WQE_QPN 0x541FA58
0854 
0855 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0 0x541FA80
0856 
0857 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1 0x541FA84
0858 
0859 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2 0x541FA88
0860 
0861 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3 0x541FA8C
0862 
0863 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4 0x541FA90
0864 
0865 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5 0x541FA94
0866 
0867 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6 0x541FA98
0868 
0869 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7 0x541FA9C
0870 
0871 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8 0x541FAA0
0872 
0873 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9 0x541FAA4
0874 
0875 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10 0x541FAA8
0876 
0877 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11 0x541FAAC
0878 
0879 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12 0x541FAB0
0880 
0881 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13 0x541FAB4
0882 
0883 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14 0x541FAB8
0884 
0885 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15 0x541FABC
0886 
0887 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16 0x541FAC0
0888 
0889 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17 0x541FAC4
0890 
0891 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0 0x541FAE0
0892 
0893 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1 0x541FAE4
0894 
0895 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2 0x541FAE8
0896 
0897 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3 0x541FAEC
0898 
0899 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4 0x541FAF0
0900 
0901 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5 0x541FAF4
0902 
0903 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN 0x541FAF8
0904 
0905 #endif /* ASIC_REG_NIC0_QPC0_REGS_H_ */