gaudi2/asic_reg/gaudi2_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * Copyright 2020-2022 HabanaLabs, Ltd.
0004  * All Rights Reserved.
0005  *
0006  */
0007
0008 #ifndef ASIC_REG_GAUDI2_REGS_H_
0009 #define ASIC_REG_GAUDI2_REGS_H_
0010
0011 #include "gaudi2_blocks_linux_driver.h"
0012 #include "psoc_reset_conf_regs.h"
0013 #include "psoc_global_conf_regs.h"
0014 #include "cpu_if_regs.h"
0015 #include "pcie_aux_regs.h"
0016 #include "pcie_dbi_regs.h"
0017 #include "pcie_wrap_regs.h"
0018 #include "pmmu_hbw_stlb_regs.h"
0019 #include "psoc_timestamp_regs.h"
0020 #include "psoc_etr_regs.h"
0021 #include "xbar_edge_0_regs.h"
0022 #include "xbar_mid_0_regs.h"
0023 #include "arc_farm_kdma_regs.h"
0024 #include "arc_farm_kdma_ctx_regs.h"
0025 #include "arc_farm_kdma_kdma_cgm_regs.h"
0026 #include "arc_farm_arc0_aux_regs.h"
0027 #include "arc_farm_arc0_acp_eng_regs.h"
0028 #include "arc_farm_kdma_ctx_axuser_regs.h"
0029 #include "arc_farm_arc0_dup_eng_axuser_regs.h"
0030 #include "arc_farm_arc0_dup_eng_regs.h"
0031 #include "dcore0_sync_mngr_objs_regs.h"
0032 #include "dcore0_sync_mngr_glbl_regs.h"
0033 #include "dcore0_sync_mngr_mstr_if_axuser_regs.h"
0034 #include "pdma0_qm_arc_aux_regs.h"
0035 #include "pdma0_core_ctx_regs.h"
0036 #include "pdma0_core_regs.h"
0037 #include "pdma0_qm_axuser_secured_regs.h"
0038 #include "pdma0_qm_regs.h"
0039 #include "pdma0_qm_cgm_regs.h"
0040 #include "pdma0_core_ctx_axuser_regs.h"
0041 #include "pdma1_core_ctx_axuser_regs.h"
0042 #include "pdma0_qm_axuser_nonsecured_regs.h"
0043 #include "pdma1_qm_axuser_nonsecured_regs.h"
0044 #include "dcore0_tpc0_qm_regs.h"
0045 #include "dcore0_tpc0_qm_cgm_regs.h"
0046 #include "dcore0_tpc0_qm_axuser_nonsecured_regs.h"
0047 #include "dcore0_tpc0_qm_arc_aux_regs.h"
0048 #include "dcore0_tpc0_cfg_regs.h"
0049 #include "dcore0_tpc0_cfg_qm_regs.h"
0050 #include "dcore0_tpc0_cfg_axuser_regs.h"
0051 #include "dcore0_tpc0_cfg_qm_sync_object_regs.h"
0052 #include "dcore0_tpc0_cfg_kernel_regs.h"
0053 #include "dcore0_tpc0_cfg_kernel_tensor_0_regs.h"
0054 #include "dcore0_tpc0_cfg_qm_tensor_0_regs.h"
0055 #include "dcore0_tpc0_cfg_special_regs.h"
0056 #include "dcore0_tpc0_eml_funnel_regs.h"
0057 #include "dcore0_tpc0_eml_etf_regs.h"
0058 #include "dcore0_tpc0_eml_stm_regs.h"
0059 #include "dcore0_tpc0_eml_busmon_0_regs.h"
0060 #include "dcore0_tpc0_eml_spmu_regs.h"
0061 #include "pmmu_pif_regs.h"
0062 #include "dcore0_edma0_qm_cgm_regs.h"
0063 #include "dcore0_edma0_core_regs.h"
0064 #include "dcore0_edma0_qm_regs.h"
0065 #include "dcore0_edma0_qm_arc_aux_regs.h"
0066 #include "dcore0_edma0_core_ctx_regs.h"
0067 #include "dcore0_edma0_core_ctx_axuser_regs.h"
0068 #include "dcore0_edma0_qm_axuser_nonsecured_regs.h"
0069 #include "dcore0_edma1_core_ctx_axuser_regs.h"
0070 #include "dcore0_edma1_qm_axuser_nonsecured_regs.h"
0071 #include "dcore0_hmmu0_stlb_regs.h"
0072 #include "dcore0_hmmu0_mmu_regs.h"
0073 #include "rot0_qm_regs.h"
0074 #include "rot0_qm_cgm_regs.h"
0075 #include "rot0_qm_arc_aux_regs.h"
0076 #include "rot0_regs.h"
0077 #include "rot0_desc_regs.h"
0078 #include "rot0_qm_axuser_nonsecured_regs.h"
0079 #include "dcore0_rtr0_mstr_if_rr_prvt_hbw_regs.h"
0080 #include "dcore0_rtr0_mstr_if_rr_prvt_lbw_regs.h"
0081 #include "dcore0_rtr0_mstr_if_rr_shrd_hbw_regs.h"
0082 #include "dcore0_rtr0_mstr_if_rr_shrd_lbw_regs.h"
0083 #include "dcore0_rtr0_ctrl_regs.h"
0084 #include "dcore0_dec0_cmd_regs.h"
0085 #include "dcore0_vdec0_brdg_ctrl_regs.h"
0086 #include "dcore0_vdec0_brdg_ctrl_axuser_dec_regs.h"
0087 #include "dcore0_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h"
0088 #include "dcore0_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h"
0089 #include "dcore0_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h"
0090 #include "dcore0_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h"
0091 #include "dcore0_vdec0_ctrl_special_regs.h"
0092 #include "pcie_vdec0_brdg_ctrl_axuser_dec_regs.h"
0093 #include "pcie_vdec0_brdg_ctrl_axuser_msix_abnrm_regs.h"
0094 #include "pcie_vdec0_brdg_ctrl_axuser_msix_l2c_regs.h"
0095 #include "pcie_vdec0_brdg_ctrl_axuser_msix_nrm_regs.h"
0096 #include "pcie_vdec0_brdg_ctrl_axuser_msix_vcd_regs.h"
0097 #include "pcie_dec0_cmd_regs.h"
0098 #include "pcie_vdec0_brdg_ctrl_regs.h"
0099 #include "pcie_vdec0_ctrl_special_regs.h"
0100 #include "dcore0_mme_qm_regs.h"
0101 #include "dcore0_mme_qm_arc_aux_regs.h"
0102 #include "dcore0_mme_qm_axuser_secured_regs.h"
0103 #include "dcore0_mme_qm_cgm_regs.h"
0104 #include "dcore0_mme_qm_arc_acp_eng_regs.h"
0105 #include "dcore0_mme_qm_axuser_nonsecured_regs.h"
0106 #include "dcore0_mme_qm_arc_dup_eng_regs.h"
0107 #include "dcore0_mme_qm_arc_dup_eng_axuser_regs.h"
0108 #include "dcore0_mme_sbte0_mstr_if_axuser_regs.h"
0109 #include "dcore0_mme_wb0_mstr_if_axuser_regs.h"
0110 #include "dcore0_mme_acc_regs.h"
0111 #include "dcore0_mme_ctrl_lo_regs.h"
0112 #include "dcore1_mme_ctrl_lo_regs.h"
0113 #include "dcore3_mme_ctrl_lo_regs.h"
0114 #include "dcore0_mme_ctrl_lo_mme_axuser_regs.h"
0115 #include "dcore0_mme_ctrl_lo_arch_agu_cout0_master_regs.h"
0116 #include "dcore0_mme_ctrl_lo_arch_agu_cout0_slave_regs.h"
0117 #include "dcore0_mme_ctrl_lo_arch_agu_cout1_master_regs.h"
0118 #include "dcore0_mme_ctrl_lo_arch_agu_cout1_slave_regs.h"
0119 #include "dcore0_mme_ctrl_lo_arch_agu_in0_master_regs.h"
0120 #include "dcore0_mme_ctrl_lo_arch_agu_in0_slave_regs.h"
0121 #include "dcore0_mme_ctrl_lo_arch_agu_in1_master_regs.h"
0122 #include "dcore0_mme_ctrl_lo_arch_agu_in1_slave_regs.h"
0123 #include "dcore0_mme_ctrl_lo_arch_agu_in2_master_regs.h"
0124 #include "dcore0_mme_ctrl_lo_arch_agu_in2_slave_regs.h"
0125 #include "dcore0_mme_ctrl_lo_arch_agu_in3_master_regs.h"
0126 #include "dcore0_mme_ctrl_lo_arch_agu_in3_slave_regs.h"
0127 #include "dcore0_mme_ctrl_lo_arch_agu_in4_master_regs.h"
0128 #include "dcore0_mme_ctrl_lo_arch_agu_in4_slave_regs.h"
0129 #include "dcore0_mme_ctrl_lo_arch_base_addr_regs.h"
0130 #include "dcore0_mme_ctrl_lo_arch_non_tensor_end_regs.h"
0131 #include "dcore0_mme_ctrl_lo_arch_non_tensor_start_regs.h"
0132 #include "dcore0_mme_ctrl_lo_arch_tensor_a_regs.h"
0133 #include "dcore0_mme_ctrl_lo_arch_tensor_b_regs.h"
0134 #include "dcore0_mme_ctrl_lo_arch_tensor_cout_regs.h"
0135
0136 #include "pdma0_qm_masks.h"
0137 #include "pdma0_core_masks.h"
0138 #include "pdma0_core_special_masks.h"
0139 #include "psoc_global_conf_masks.h"
0140 #include "psoc_reset_conf_masks.h"
0141 #include "arc_farm_kdma_masks.h"
0142 #include "arc_farm_kdma_ctx_masks.h"
0143 #include "arc_farm_arc0_aux_masks.h"
0144 #include "arc_farm_kdma_ctx_axuser_masks.h"
0145 #include "dcore0_sync_mngr_objs_masks.h"
0146 #include "dcore0_sync_mngr_glbl_masks.h"
0147 #include "dcore0_sync_mngr_mstr_if_axuser_masks.h"
0148 #include "dcore0_tpc0_cfg_masks.h"
0149 #include "dcore0_mme_ctrl_lo_masks.h"
0150 #include "dcore0_mme_sbte0_masks.h"
0151 #include "dcore0_edma0_qm_masks.h"
0152 #include "dcore0_edma0_core_masks.h"
0153 #include "dcore0_hmmu0_stlb_masks.h"
0154 #include "dcore0_hmmu0_mmu_masks.h"
0155 #include "dcore0_dec0_cmd_masks.h"
0156 #include "dcore0_vdec0_brdg_ctrl_masks.h"
0157 #include "pcie_dec0_cmd_masks.h"
0158 #include "pcie_vdec0_brdg_ctrl_masks.h"
0159 #include "rot0_masks.h"
0160 #include "pmmu_hbw_stlb_masks.h"
0161 #include "psoc_etr_masks.h"
0162
0163 #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR    0x4800040
0164
0165 #define SM_OBJS_PROT_BITS_OFFS          0x14000
0166
0167 #define DCORE_OFFSET            (mmDCORE1_TPC0_QM_BASE - mmDCORE0_TPC0_QM_BASE)
0168 #define DCORE_EDMA_OFFSET       (mmDCORE0_EDMA1_QM_BASE - mmDCORE0_EDMA0_QM_BASE)
0169 #define DCORE_TPC_OFFSET        (mmDCORE0_TPC1_QM_BASE - mmDCORE0_TPC0_QM_BASE)
0170 #define DCORE_DEC_OFFSET        (mmDCORE0_DEC1_VSI_BASE - mmDCORE0_DEC0_VSI_BASE)
0171 #define DCORE_HMMU_OFFSET       (mmDCORE0_HMMU1_MMU_BASE - mmDCORE0_HMMU0_MMU_BASE)
0172 #define NIC_QM_OFFSET           (mmNIC0_QM1_BASE - mmNIC0_QM0_BASE)
0173 #define PDMA_OFFSET         (mmPDMA1_QM_BASE - mmPDMA0_QM_BASE)
0174 #define ROT_OFFSET          (mmROT1_BASE - mmROT0_BASE)
0175
0176 #define TPC_CFG_BASE_ADDRESS_HIGH_OFFSET \
0177             (mmDCORE0_TPC0_CFG_CFG_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE)
0178
0179 #define TPC_CFG_SM_BASE_ADDRESS_HIGH_OFFSET \
0180             (mmDCORE0_TPC0_CFG_SM_BASE_ADDRESS_HIGH - mmDCORE0_TPC0_CFG_BASE)
0181
0182 #define TPC_CFG_STALL_OFFSET        (mmDCORE0_TPC0_CFG_TPC_STALL - mmDCORE0_TPC0_CFG_BASE)
0183 #define TPC_CFG_STALL_ON_ERR_OFFSET (mmDCORE0_TPC0_CFG_STALL_ON_ERR - mmDCORE0_TPC0_CFG_BASE)
0184 #define TPC_CFG_TPC_INTR_MASK_OFFSET    (mmDCORE0_TPC0_CFG_TPC_INTR_MASK - mmDCORE0_TPC0_CFG_BASE)
0185 #define TPC_CFG_MSS_CONFIG_OFFSET   (mmDCORE0_TPC0_CFG_MSS_CONFIG - mmDCORE0_TPC0_CFG_BASE)
0186
0187 #define MME_ACC_INTR_MASK_OFFSET    (mmDCORE0_MME_ACC_INTR_MASK - mmDCORE0_MME_ACC_BASE)
0188 #define MME_ACC_WR_AXI_AGG_COUT0_OFFSET (mmDCORE0_MME_ACC_WR_AXI_AGG_COUT0 - mmDCORE0_MME_ACC_BASE)
0189 #define MME_ACC_WR_AXI_AGG_COUT1_OFFSET (mmDCORE0_MME_ACC_WR_AXI_AGG_COUT1 - mmDCORE0_MME_ACC_BASE)
0190 #define MME_ACC_AP_LFSR_POLY_OFFSET (mmDCORE0_MME_ACC_AP_LFSR_POLY - mmDCORE0_MME_ACC_BASE)
0191 #define MME_ACC_AP_LFSR_SEED_SEL_OFFSET (mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL - mmDCORE0_MME_ACC_BASE)
0192 #define MME_ACC_AP_LFSR_SEED_WDATA_OFFSET \
0193     (mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA - mmDCORE0_MME_ACC_BASE)
0194
0195 #define DMA_CORE_CFG_0_OFFSET       (mmARC_FARM_KDMA_CFG_0 - mmARC_FARM_KDMA_BASE)
0196 #define DMA_CORE_CFG_1_OFFSET       (mmARC_FARM_KDMA_CFG_1 - mmARC_FARM_KDMA_BASE)
0197 #define DMA_CORE_PROT_OFFSET        (mmARC_FARM_KDMA_PROT - mmARC_FARM_KDMA_BASE)
0198 #define DMA_CORE_ERRMSG_ADDR_LO_OFFSET  (mmARC_FARM_KDMA_ERRMSG_ADDR_LO - mmARC_FARM_KDMA_BASE)
0199 #define DMA_CORE_ERRMSG_ADDR_HI_OFFSET  (mmARC_FARM_KDMA_ERRMSG_ADDR_HI - mmARC_FARM_KDMA_BASE)
0200 #define DMA_CORE_ERRMSG_WDATA_OFFSET    (mmARC_FARM_KDMA_ERRMSG_WDATA - mmARC_FARM_KDMA_BASE)
0201
0202 #define QM_PQ_BASE_LO_0_OFFSET      (mmPDMA0_QM_PQ_BASE_LO_0 - mmPDMA0_QM_BASE)
0203 #define QM_PQ_BASE_HI_0_OFFSET      (mmPDMA0_QM_PQ_BASE_HI_0 - mmPDMA0_QM_BASE)
0204 #define QM_PQ_SIZE_0_OFFSET     (mmPDMA0_QM_PQ_SIZE_0 - mmPDMA0_QM_BASE)
0205 #define QM_PQ_PI_0_OFFSET       (mmPDMA0_QM_PQ_PI_0 - mmPDMA0_QM_BASE)
0206 #define QM_PQ_CI_0_OFFSET       (mmPDMA0_QM_PQ_CI_0 - mmPDMA0_QM_BASE)
0207 #define QM_CP_FENCE0_CNT_0_OFFSET   (mmPDMA0_QM_CP_FENCE0_CNT_0 - mmPDMA0_QM_BASE)
0208
0209 #define QM_CP_MSG_BASE0_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0 - mmPDMA0_QM_BASE)
0210 #define QM_CP_MSG_BASE0_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0 - mmPDMA0_QM_BASE)
0211 #define QM_CP_MSG_BASE1_ADDR_LO_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0 - mmPDMA0_QM_BASE)
0212 #define QM_CP_MSG_BASE1_ADDR_HI_0_OFFSET (mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0 - mmPDMA0_QM_BASE)
0213
0214 #define QM_CP_CFG_OFFSET        (mmPDMA0_QM_CP_CFG - mmPDMA0_QM_BASE)
0215 #define QM_PQC_HBW_BASE_LO_0_OFFSET (mmPDMA0_QM_PQC_HBW_BASE_LO_0 - mmPDMA0_QM_BASE)
0216 #define QM_PQC_HBW_BASE_HI_0_OFFSET (mmPDMA0_QM_PQC_HBW_BASE_HI_0 - mmPDMA0_QM_BASE)
0217 #define QM_PQC_SIZE_0_OFFSET        (mmPDMA0_QM_PQC_SIZE_0 - mmPDMA0_QM_BASE)
0218 #define QM_PQC_PI_0_OFFSET      (mmPDMA0_QM_PQC_PI_0 - mmPDMA0_QM_BASE)
0219 #define QM_PQC_LBW_WDATA_0_OFFSET   (mmPDMA0_QM_PQC_LBW_WDATA_0 - mmPDMA0_QM_BASE)
0220 #define QM_PQC_LBW_BASE_LO_0_OFFSET (mmPDMA0_QM_PQC_LBW_BASE_LO_0 - mmPDMA0_QM_BASE)
0221 #define QM_PQC_LBW_BASE_HI_0_OFFSET (mmPDMA0_QM_PQC_LBW_BASE_HI_0 - mmPDMA0_QM_BASE)
0222 #define QM_GLBL_ERR_ADDR_LO_OFFSET  (mmPDMA0_QM_GLBL_ERR_ADDR_LO - mmPDMA0_QM_BASE)
0223 #define QM_PQC_CFG_OFFSET       (mmPDMA0_QM_PQC_CFG - mmPDMA0_QM_BASE)
0224 #define QM_ARB_CFG_0_OFFSET     (mmPDMA0_QM_ARB_CFG_0 - mmPDMA0_QM_BASE)
0225 #define QM_GLBL_CFG0_OFFSET     (mmPDMA0_QM_GLBL_CFG0 - mmPDMA0_QM_BASE)
0226 #define QM_GLBL_CFG1_OFFSET     (mmPDMA0_QM_GLBL_CFG1 - mmPDMA0_QM_BASE)
0227 #define QM_GLBL_CFG2_OFFSET     (mmPDMA0_QM_GLBL_CFG2 - mmPDMA0_QM_BASE)
0228 #define QM_GLBL_PROT_OFFSET     (mmPDMA0_QM_GLBL_PROT - mmPDMA0_QM_BASE)
0229 #define QM_GLBL_ERR_CFG_OFFSET      (mmPDMA0_QM_GLBL_ERR_CFG - mmPDMA0_QM_BASE)
0230 #define QM_GLBL_ERR_CFG1_OFFSET     (mmPDMA0_QM_GLBL_ERR_CFG1 - mmPDMA0_QM_BASE)
0231 #define QM_GLBL_ERR_ADDR_HI_OFFSET  (mmPDMA0_QM_GLBL_ERR_ADDR_HI - mmPDMA0_QM_BASE)
0232 #define QM_GLBL_ERR_WDATA_OFFSET    (mmPDMA0_QM_GLBL_ERR_WDATA - mmPDMA0_QM_BASE)
0233 #define QM_ARB_ERR_MSG_EN_OFFSET    (mmPDMA0_QM_ARB_ERR_MSG_EN - mmPDMA0_QM_BASE)
0234 #define QM_ARB_SLV_CHOISE_WDT_OFFSET    (mmPDMA0_QM_ARB_SLV_CHOICE_WDT - mmPDMA0_QM_BASE)
0235 #define QM_FENCE2_OFFSET        (mmPDMA0_QM_CP_FENCE2_RDATA_0 - mmPDMA0_QM_BASE)
0236 #define QM_SEI_STATUS_OFFSET        (mmPDMA0_QM_SEI_STATUS - mmPDMA0_QM_BASE)
0237
0238 #define SFT_OFFSET      (mmSFT1_HBW_RTR_IF0_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE)
0239 #define SFT_IF_RTR_OFFSET   (mmSFT0_HBW_RTR_IF1_RTR_H3_BASE - mmSFT0_HBW_RTR_IF0_RTR_H3_BASE)
0240
0241 #define ARC_HALT_REQ_OFFSET (mmARC_FARM_ARC0_AUX_RUN_HALT_REQ - mmARC_FARM_ARC0_AUX_BASE)
0242
0243 #define ARC_REGION_CFG_OFFSET(region) \
0244     (mmARC_FARM_ARC0_AUX_ARC_REGION_CFG_0 + (region * 4) - mmARC_FARM_ARC0_AUX_BASE)
0245
0246 #define ARC_DCCM_UPPER_EN_OFFSET \
0247     (mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN - mmARC_FARM_ARC0_AUX_BASE)
0248
0249 #define PCIE_VDEC_OFFSET    \
0250     (mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmPCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE)
0251
0252 #define DCORE_MME_SBTE_OFFSET   \
0253     (mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE)
0254
0255 #define DCORE_MME_WB_OFFSET \
0256     (mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE)
0257
0258 #define DCORE_RTR_OFFSET    \
0259     (mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0260
0261 #define DCORE_VDEC_OFFSET   \
0262     (mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE)
0263
0264 #define MMU_OFFSET(REG)         (REG - mmDCORE0_HMMU0_MMU_BASE)
0265 #define MMU_BYPASS_OFFSET       MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_BYPASS)
0266 #define MMU_SPI_SEI_MASK_OFFSET     MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_MASK)
0267 #define MMU_SPI_SEI_CAUSE_OFFSET    MMU_OFFSET(mmDCORE0_HMMU0_MMU_SPI_SEI_CAUSE)
0268 #define MMU_ENABLE_OFFSET       MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_ENABLE)
0269 #define MMU_DDR_RANGE_REG_ENABLE    MMU_OFFSET(mmDCORE0_HMMU0_MMU_DDR_RANGE_REG_ENABLE)
0270 #define MMU_RR_SEC_MIN_63_32_0_OFFSET   MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_63_32_0)
0271 #define MMU_RR_SEC_MIN_31_0_0_OFFSET    MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MIN_31_0_0)
0272 #define MMU_RR_SEC_MAX_63_32_0_OFFSET   MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_63_32_0)
0273 #define MMU_RR_SEC_MAX_31_0_0_OFFSET    MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_SEC_MAX_31_0_0)
0274 #define MMU_RR_PRIV_MIN_63_32_0_OFFSET  MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_63_32_0)
0275 #define MMU_RR_PRIV_MIN_31_0_0_OFFSET   MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MIN_31_0_0)
0276 #define MMU_RR_PRIV_MAX_63_32_0_OFFSET  MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_63_32_0)
0277 #define MMU_RR_PRIV_MAX_31_0_0_OFFSET   MMU_OFFSET(mmDCORE0_HMMU0_MMU_MMU_RR_PRIV_MAX_31_0_0)
0278 #define MMU_INTERRUPT_CLR_OFFSET    MMU_OFFSET(mmDCORE0_HMMU0_MMU_INTERRUPT_CLR)
0279
0280 #define STLB_OFFSET(REG)        (REG - mmDCORE0_HMMU0_STLB_BASE)
0281 #define STLB_BUSY_OFFSET        STLB_OFFSET(mmDCORE0_HMMU0_STLB_BUSY)
0282 #define STLB_ASID_OFFSET        STLB_OFFSET(mmDCORE0_HMMU0_STLB_ASID)
0283 #define STLB_HOP0_PA43_12_OFFSET    STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA43_12)
0284 #define STLB_HOP0_PA63_44_OFFSET    STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP0_PA63_44)
0285 #define STLB_HOP_CONFIGURATION_OFFSET   STLB_OFFSET(mmDCORE0_HMMU0_STLB_HOP_CONFIGURATION)
0286 #define STLB_INV_ALL_START_OFFSET   STLB_OFFSET(mmDCORE0_HMMU0_STLB_INV_ALL_START)
0287 #define STLB_SRAM_INIT_OFFSET       STLB_OFFSET(mmDCORE0_HMMU0_STLB_SRAM_INIT)
0288 #define STLB_SET_THRESHOLD_HOP3_OFFSET  STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3)
0289 #define STLB_SET_THRESHOLD_HOP2_OFFSET  STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2)
0290 #define STLB_SET_THRESHOLD_HOP1_OFFSET  STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1)
0291 #define STLB_SET_THRESHOLD_HOP0_OFFSET  STLB_OFFSET(mmDCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0)
0292 #define STLB_RANGE_INV_START_LSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_LSB)
0293 #define STLB_RANGE_INV_START_MSB_OFFSET STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_START_MSB)
0294 #define STLB_RANGE_INV_END_LSB_OFFSET   STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_LSB)
0295 #define STLB_RANGE_INV_END_MSB_OFFSET   STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_INV_END_MSB)
0296
0297 #define STLB_LL_LOOKUP_MASK_63_32_OFFSET    \
0298             STLB_OFFSET(mmDCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32)
0299
0300 #define STLB_RANGE_CACHE_INVALIDATION_OFFSET    \
0301             STLB_OFFSET(mmDCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION)
0302
0303 /* RTR CTR RAZWI related offsets */
0304 #define RTR_MSTR_IF_OFFSET  (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE)
0305
0306 #define RTR_LBW_MSTR_IF_OFFSET  \
0307             (mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE - mmDCORE0_RTR0_CTRL_BASE)
0308
0309 /* RAZWI captured hbw aw addr high */
0310 #define DEC_RAZWI_HBW_AW_ADDR_HI    \
0311             (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE)
0312
0313 /* RAZWI captured hbw aw addr low */
0314 #define DEC_RAZWI_HBW_AW_ADDR_LO    \
0315             (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE)
0316
0317 /* RAZWI captured hbw aw set */
0318 #define DEC_RAZWI_HBW_AW_SET        \
0319             (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE)
0320
0321 /* RAZWI captured hbw ar addr high */
0322 #define DEC_RAZWI_HBW_AR_ADDR_HI \
0323             (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_HI_ADDR - mmDCORE0_RTR0_CTRL_BASE)
0324
0325 /* RAZWI captured hbw ar addr low */
0326 #define DEC_RAZWI_HBW_AR_ADDR_LO    \
0327             (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_LO_ADDR - mmDCORE0_RTR0_CTRL_BASE)
0328
0329 /* RAZWI captured hbw ar set */
0330 #define DEC_RAZWI_HBW_AR_SET        \
0331             (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE)
0332
0333 /* RAZWI captured lbw aw addr */
0334 #define DEC_RAZWI_LBW_AW_ADDR       \
0335             (mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AW_ADDR - mmDCORE0_RTR0_CTRL_BASE)
0336
0337 /* RAZWI captured lbw aw set */
0338 #define DEC_RAZWI_LBW_AW_SET        \
0339             (mmDCORE0_RTR0_CTRL_DEC_RAZWI_HBW_AW_SET - mmDCORE0_RTR0_CTRL_BASE)
0340
0341 /* RAZWI captured lbw ar addr */
0342 #define DEC_RAZWI_LBW_AR_ADDR       \
0343             (mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_ADDR - mmDCORE0_RTR0_CTRL_BASE)
0344
0345 /* RAZWI captured lbw ar set */
0346 #define DEC_RAZWI_LBW_AR_SET        \
0347             (mmDCORE0_RTR0_CTRL_DEC_RAZWI_LBW_AR_SET - mmDCORE0_RTR0_CTRL_BASE)
0348
0349 /* RAZWI captured shared hbw aw addr high */
0350 #define RR_SHRD_HBW_AW_RAZWI_HI     \
0351     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0352
0353 /* RAZWI captured shared hbw aw addr low */
0354 #define RR_SHRD_HBW_AW_RAZWI_LO     \
0355     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0356
0357 /* RAZWI captured shared hbw ar addr high */
0358 #define RR_SHRD_HBW_AR_RAZWI_HI     \
0359     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HI - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0360
0361 /* RAZWI captured shared hbw ar addr low */
0362 #define RR_SHRD_HBW_AR_RAZWI_LO     \
0363     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_LO - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0364
0365 /* RAZWI captured shared aw XY coordinates */
0366 #define RR_SHRD_HBW_AW_RAZWI_XY     \
0367     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0368
0369 /* RAZWI captured shared ar XY coordinates */
0370 #define RR_SHRD_HBW_AR_RAZWI_XY     \
0371     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_XY - mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0372
0373 /* RAZWI hbw shared occurred due to write access */
0374 #define RR_SHRD_HBW_AW_RAZWI_HAPPENED   \
0375             (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AW_RAZWI_HAPPENED - \
0376                 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0377
0378 /* RAZWI hbw shared occurred due to read access */
0379 #define RR_SHRD_HBW_AR_RAZWI_HAPPENED   \
0380             (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_AR_RAZWI_HAPPENED - \
0381                 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0382
0383 /* RAZWI captured shared lbw aw addr */
0384 #define RR_SHRD_LBW_AW_RAZWI        \
0385             (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI - \
0386                     mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0387
0388 /* RAZWI captured shared lbw ar addr */
0389 #define RR_SHRD_LBW_AR_RAZWI        \
0390             (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI - \
0391                     mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0392
0393 /* RAZWI captured shared lbw aw XY coordinates */
0394 #define RR_SHRD_LBW_AW_RAZWI_XY     \
0395             (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_XY - \
0396                     mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0397
0398 /* RAZWI captured shared lbw ar XY coordinates */
0399 #define RR_SHRD_LBW_AR_RAZWI_XY     \
0400             (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_XY - \
0401                     mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0402
0403 /* RAZWI lbw shared occurred due to write access */
0404 #define RR_SHRD_LBW_AW_RAZWI_HAPPENED   \
0405             (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AW_RAZWI_HAPPENED - \
0406                     mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0407
0408 /* RAZWI lbw shared occurred due to read access */
0409 #define RR_SHRD_LBW_AR_RAZWI_HAPPENED   \
0410             (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_AR_RAZWI_HAPPENED - \
0411                 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0412
0413 #define BRDG_CTRL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_BASE - mmDCORE0_DEC0_CMD_BASE)
0414 #define SPECIAL_BLOCK_OFFSET (mmDCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE - mmDCORE0_DEC0_CMD_BASE)
0415 #define SFT_DCORE_OFFSET (mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE)
0416 #define SFT_IF_OFFSET (mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE)
0417
0418 #define BRDG_CTRL_NRM_MSIX_LBW_AWADDR   \
0419     (mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
0420
0421 #define BRDG_CTRL_NRM_MSIX_LBW_WDATA    \
0422     (mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
0423
0424 #define BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR \
0425     (mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
0426
0427 #define BRDG_CTRL_ABNRM_MSIX_LBW_WDATA  \
0428     (mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
0429
0430 #define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET \
0431     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0 - \
0432             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0433
0434 #define RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET \
0435     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0 - \
0436             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0437
0438 #define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET \
0439     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0 - \
0440             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0441
0442 #define RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET \
0443     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0 - \
0444             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0445
0446 #define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET    \
0447     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0 - \
0448             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0449
0450 #define RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET    \
0451     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0 - \
0452             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0453
0454 #define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET    \
0455     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0 - \
0456             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0457
0458 #define RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET    \
0459     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0 - \
0460             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0461
0462 #define RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET   \
0463     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_HI_0 - \
0464             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0465
0466 #define RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET   \
0467     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MIN_LO_0 - \
0468             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0469
0470 #define RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET   \
0471     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_HI_0 - \
0472             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0473
0474 #define RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET   \
0475     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SEC_RANGE_MAX_LO_0 - \
0476             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0477
0478 #define RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET  \
0479     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0 - \
0480             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0481
0482 #define RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET  \
0483     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0 - \
0484             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0485
0486 #define RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET  \
0487     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0 - \
0488             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0489
0490 #define RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET  \
0491     (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0 - \
0492             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE)
0493
0494 #define RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET \
0495         (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_SHORT_0 - \
0496             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
0497
0498 #define RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET \
0499         (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_SHORT_0 - \
0500             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
0501
0502 #define RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET    \
0503         (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_SHORT_0 - \
0504             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
0505
0506 #define RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET    \
0507         (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_SHORT_0 - \
0508             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
0509
0510 #define RR_LBW_SEC_RANGE_MIN_0_OFFSET   \
0511         (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MIN_0 - \
0512             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
0513
0514 #define RR_LBW_SEC_RANGE_MAX_0_OFFSET   \
0515         (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SEC_RANGE_MAX_0 - \
0516             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
0517
0518 #define RR_LBW_PRIV_RANGE_MIN_0_OFFSET  \
0519         (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MIN_0 - \
0520             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
0521
0522 #define RR_LBW_PRIV_RANGE_MAX_0_OFFSET  \
0523         (mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_PRIV_RANGE_MAX_0 - \
0524             mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE)
0525
0526 #define ARC_AUX_DCCM_QUEUE_PUSH_REG_0_OFFSET    \
0527         (mmARC_FARM_ARC0_AUX_DCCM_QUEUE_PUSH_REG_0 - mmARC_FARM_ARC0_AUX_BASE)
0528
0529 #define MMU_STATIC_MULTI_PAGE_SIZE_OFFSET   \
0530     (mmDCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE - mmDCORE0_HMMU0_MMU_BASE)
0531
0532 #define HBM_MC_SPI_TEMP_PIN_CHG_MASK        BIT(0)
0533 #define HBM_MC_SPI_THR_ENG_MASK         BIT(1)
0534 #define HBM_MC_SPI_THR_DIS_ENG_MASK     BIT(2)
0535 #define HBM_MC_SPI_IEEE1500_COMP_MASK       BIT(3)
0536 #define HBM_MC_SPI_IEEE1500_PAUSED_MASK     BIT(4)
0537
0538 #include "nic0_qpc0_regs.h"
0539 #include "nic0_qm0_regs.h"
0540 #include "nic0_qm_arc_aux0_regs.h"
0541 #include "nic0_qm0_cgm_regs.h"
0542 #include "nic0_umr0_0_completion_queue_ci_1_regs.h"
0543 #include "nic0_umr0_0_unsecure_doorbell0_regs.h"
0544
0545 #define NIC_OFFSET      (mmNIC1_MSTR_IF_RR_SHRD_HBW_BASE - mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE)
0546
0547 #define NIC_UMR_OFFSET \
0548     (mmNIC0_UMR0_1_UNSECURE_DOORBELL0_BASE - mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE)
0549
0550 #endif /* ASIC_REG_GAUDI2_REGS_H_ */